SYZYGY fp files: Refactored to be picked up based on board option selected
Signed-off-by:
Brian Burke <Brian.Burke@microchip.com>
parent
dd95e414
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- sources/FPGA-design/script_support/components/SYZYGY/BOARD_VALIDATION_OPAL_KELLY/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...OPAL_KELLY/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/BOARD_VALIDATION_SEEED_STUDIO/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...EED_STUDIO/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...IO_2_LANES/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/DEFAULT/constraints/mpfs-icicle-kit-es/MPFS250T_ES/FCVG484/SYZYGY.pdc 1 addition, 0 deletions...traints/mpfs-icicle-kit-es/MPFS250T_ES/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/IO_BOARD_VALIDATION/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...VALIDATION/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/IO_STUB/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...GY/IO_STUB/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
- sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc 0 additions, 0 deletions...OPAL_KELLY/constraints/fp/bvf/MPFS025T/FCVG484/SYZYGY.pdc
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