6.1.69-ti-arm64-r24 bb.org_defconfig
TI SDK: 09.02.00.003
6.1 TI Delta: https://github.com/RobertCNelson/ti-linux-kernel/compare/78d2216bc679e98b7edb07ffabddb6d0337b5fcb...2b466a25764b90577292416556566d1971a489ad
BBDTBS: beagleboard/BeagleBoard-DeviceTrees@0bf6415c
WIRELESS_REGDB: https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/commit/?id=37dcea0e6e5effb4228fe385e906edba3cbee389
WPANUSB: beagleconnect/linux/wpanusb@6aa9bf65



Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

Lets drive Sierra clock output and workaround a TIFS/DM bug for now.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

Add the Greybus host driver for BeaglePlay board by BeagleBoard.org.

The current greybus setup involves running SVC in a user-space
application (GBridge) and using netlink to communicate with kernel
space. GBridge itself uses wpanusb kernel driver, so the greybus messages
travel from kernel space (gb_netlink) to user-space (GBridge) and then
back to kernel space (wpanusb) before reaching CC1352.

This driver directly communicates with CC1352 (running SVC Zephyr
application). Thus, it simplifies the complete greybus setup eliminating
user-space GBridge.

This driver is responsible for the following:
- Start SVC (CC1352) on driver load.
- Send/Receive Greybus messages to/from CC1352 using HDLC over UART.
- Print Logs from CC1352.
- Stop SVC (CC1352) on driver load.

Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Link: https://lore.kernel.org/r/20231017101116.178041-3-ayushdevel1325@gmail.com


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Add DT bindings for Texas Instruments Simplelink CC1352P7 wireless MCU

BeaglePlay has CC1352P7 co-processor connected to the main AM62 (running
Linux) over UART. In the BeagleConnect Technology, CC1352 is responsible
for handling 6LoWPAN communication with beagleconnect freedom nodes as
well as their discovery.

Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20231017101116.178041-2-ayushdevel1325@gmail.com


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Reference: rpi-6.1.y
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

Reference: v6.1.77
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

"uio" for generic use
"ti,pruss-shmem" for backwards compatibility

the of_id module parameter is still supported to add another id

Reference: v5.10.209
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

https://openbeagle.org/beagleboard/BeagleBoard-DeviceTrees/-/tree/v6.1.x-Beagle

beagleboard/BeagleBoard-DeviceTrees@0bf6415c


Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/commit/?id=37dcea0e6e5effb4228fe385e906edba3cbee389


Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

From
https://github.com/statropy/wpanusb

beagleconnect/linux/wpanusb@6aa9bf65


Signed-off-by: Robert Nelson <robertcnelson@gmail.com>

The PCIe0 instance of PCIe on TI's J722S SoC is a Gen3 single lane PCIe
controller.

Add the device-tree nodes for it and enable it in Root Complex mode of
operation using Lane 0 of the Serdes1 instance of Serdes.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes, with
the WIZ1 instance of the WIZ wrapper for configuring the Serdes.

Add the serdes1 and serdes_wiz1 device-tree nodes corresponding to them.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

The Serdes1 instance of Serdes can be muxed between PCIe0 and SGMII1.
Update the serdes_ln_ctrl node adding support for it and set the default
muxing for Serdes1 Lane0 to PCIe0.

Additionally, convert the serdes_ln_ctrl node into reg-mux in this
process.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

The DT binding for the reg-mux compatible states it can be used when the
"parent device of mux controller is not syscon device". It also allows
for a reg property. When the reg property is provided, use that to
identify the address space for this mux. If not provided fallback to
using the parent device as a regmap provider.

While here use dev_err_probe() in the error path to prevent printing
a message on probe defer which now can happen in extra ways.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20231025161247.1283319-1-afd@ti.com/


Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
The controller on J722S SoC is similar to the one present on TI's AM64
SoC, with the difference being that the controller on AM64 SoC supports
up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.

Update the bindings with a new compatible for J722S SoC.

Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3

Link: https://lore.kernel.org/r/20240124122936.816142-1-s-vadapalli@ti.com/


Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>

J722S SoC has two instances of Serdes namely Serdes0 and Serdes1.
Each Serdes instance has one lane which is muxed across two IPs.
Define the lane-muxing for both Serdes instances and the respective IPs.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

PSC controller has a limitation that it can only power-up the second core
when the first core is in ON state. Power-state for core0 should be equal
to or higher than core1, else the kernel is seen hanging during rproc
loading.

Make the powering up of cores sequential, by waiting for the current core
to power-up before proceeding to the next core, with a timeout of 2sec.
Add a wait queue event in k3_r5_cluster_rproc_init call, that will wait
for the current core to be released from reset before proceeding with the
next core.

Fixes: 6dedbd1d

 ("remoteproc: k3-r5: Add a remoteproc driver for R5F subsystem")

Signed-off-by: Apurva Nandan <a-nandan@ti.com>

Update the USB0, USB1 nodes and enable them.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>

USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>

Add SERDES0 and its wrapper description to support USB3
and SGMII interfaces.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Acked-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>

commit 729cfcf8

 upstream.

Add overlay to enable the PCIE1 instance of PCIe on J721S2-EVM in
Endpoint mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231211115535.1264353-3-s-vadapalli@ti.com


Signed-off-by: Nishanth Menon <nm@ti.com>

commit 39426979

 upstream.

Add overlay to enable the PCIE0 instance of PCIe on J721E-EVM in
Endpoint mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231211115535.1264353-2-s-vadapalli@ti.com


Signed-off-by: Nishanth Menon <nm@ti.com>

Add the device-id of 0xb012 for the PCIe controller on the J784S4 SoC as
described in the CTRL_MMR_PCI_DEVICE_ID register's PCI_DEVICE_ID_DEVICE_ID
field. The Register descriptions and the Technical Reference Manual for
J784S4 SoC can be found at: https://www.ti.com/lit/zip/spruj52

Link: https://lore.kernel.org/r/20240115055236.1840255-1-s-vadapalli@ti.com


Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring <robh@kernel.org>

The "ti,mac-only" property is used to indicate whether a port is
configured as a MAC Only port or not. Adding the property in the
device-tree node corresponding to a particular MAC Port specifies that
the port will operate in MAC mode of operation. The absence of the
property specifies that the group of ports which do not have the
property set will form a Switch thereby forwarding all broadcast traffic
amongst them in Hardware. Since the intended mode of operation on
device boot up is MAC mode of operation for all CPSW9G ports, add the
missing "ti,mac-only" property for MAC ports 5 to 8.

Fixes: 8bb67762

 ("arm64: dts: ti: k3-j784s4-main: Add CPSW9G nodes")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Add 2G, 1G, 500M and 250M as the supported frequencies for
A72. This enables support for Dynamic Frequency Scaling (DFS).

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

This add suspend-to-ram support.

The derived_table is kept-as is, so the resume is only about
pm_runtime_* calls and restoring the same registers as the probe.

Extract the hardware initialization procedure to a function called at
both probe-time & resume-time.

The probe-time loop is split in two to ensure doing the hardware
initialization before registering thermal zones. That ensures our
callbacks cannot be called while in bad state.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Acked-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>

Enable simple-framebuffer for bootloader splash screen to have a
seamless transition from bootloader splash screen to Linux logo and
thereafter psplash animation without having to wait for TI display
driver to get probed.

Also mark the frame-buffer region as reserved so that Linux doesn't use
the memory area while booting up, thus avoiding flicker.

Signed-off-by: Devarsh Thakkar <devarsht@ti.com>

Arducam V3Link camera adapter (Tx) is a dedicated board with UB953
serializer, that support RPi 22-pin compatible sensors. It is shipped
with an IMX219 sensor. [1]

Add overlays for interfacing these boards with the 4x different RX ports
on the V3Link mini fusion board (UB960 deserializer).

[1]: https://docs.arducam.com/V3Link-Camera-Solution/V3Link-Camera-Solution-on-TI-Platform/Introduction/



Signed-off-by: Jianzhong Xu <xuj@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>

Some sensors, like IMX219, send 8-bit/10-bit RAW bayer data. Add support
for these formats in UB960.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>

The next subdev in the media graph may want to enquire information such
as bus format, virtual channel, bus data type to route the stream from
this sensor correctly.

Add support for sharing this information using a get_frame_desc()
callback.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>

Arducam's UC-A09 is a V3Link "mini" fusion board. [1]

It can be used to connect multiple V3Link (and FPD-III) based cameras to
TI EVMs using a single 22-pin FFC (4-lane) CSI2 connector.

Add an overlay to support it on SK-AM62A, and other boards of the family
with the FFC connector.

[1] https://www.arducam.com/downloads/datasheet/Arducam_V3Link_Datasheet.pdf



Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>