Signed-off-by: Tom Rini <trini@konsulko.com>

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>

- A series of minor cleanups to DISTRO_DEFAULTS and BOOTSTD so that the
  rk3399 bootstd migration can be complete and functional now, and make
  future migrations easier.

The defined altbootcmd was specific to distro_bootcmd which is not
longer in use on these platforms, so drop it.

Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>

When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.

Signed-off-by: Tom Rini <trini@konsulko.com>

These board have moved to standard boot but the old 'distro_bootcmd'
command is still active. Disable DISTRO_DEFAULTS to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>

These two features use a lot of common options. Move them into a common
CONFIG to reduce duplication.

Use 'select' for most options since these are things that boards aren't
supposed to override. For now it is not possible to disable
BOOT_DEFAULTS but we may take another look later.

Note that five options use 'imply' to match existing behaviour.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Rework a bit so we don't grow so many platforms unintentionally]
Signed-off-by: Tom Rini <trini@konsulko.com>

Ramdisk relocation requires LMB, so enable it automatically to avoid
build errors.

Signed-off-by: Simon Glass <sjg@chromium.org>

This relates to booting so move it in to that Kconfig file, before
changing it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Unfortunately the IRAM used to stash the bootstage records in TPL
becomes inaccessible after SPL runs. Presumably this is because of ATF
taking it over.

We could move the stash to another address in SPL, before passing it to
U-Boot proper. But it seems easier to wait until we have support for
standard passage[1] which should not be too far away.

For now, disable it in TPL and SPL.

[1] https://patchwork.ozlabs.org/project/uboot/cover/


    20220117150428.1580273-1-sjg@chromium.org/

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>

- x86: Bug fixes of previous BayTrail platform CONFIG_TEXT_BASE changes

With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Fixes: e23cae30 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Fixes: 5d1c8342 ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Fixes: 388f93f9 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>

With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Fixes: f38be308 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.

Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.

Add documentation on how to make this change safely.

Fixes: 66e2c665 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Pull request for efi-2023.04-rc5

UEFI:

* Create unique device paths for USB devices with the same vendor
  and product id.

EFI device paths for block devices must be unique. If a non-unique device
path is discovered, probing of the block device fails.

Currently we use UsbClass() device path nodes. As multiple devices may
have the same vendor and product id these are non-unique. Instead we
should use Usb() device path nodes. They include the USB port on the
parent hub. Hence they are unique.

A USB storage device may contain multiple logical units. These can be
modeled as Ctrl() nodes.

Reported-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

* Add the definitions for Ctrl() device path nodes.
* Implement Ctrl() nodes in the device path to text protocol.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

- Fixes for booting newer revs of the SoC in the Raspberry Pi 4
- Propagate some firmware DT properties to the loaded DT
- Update the Zero2W upstream DT name

Newer firmware can manage the SDCDIV clock divisor register, allowing
the divisor to scale with the core as necessary.

Leverage this ability if the firmware supports it.

Adapted from the following raspberrypi Linux kernel commit:

  bcm2835-sdhost: Firmware manages the clock divisor
  https://github.com/raspberrypi/linux/commit/08532d242d7702ae0add95096aa49c5e96e066e2



Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

In rpi-firmware 25e2b597ebfb2495eab4816a276758dcc6ea21f1,
the GET_CLOCK_RATE mailbox property was changed to return the last
value set by SET_CLOCK_RATE.

https://github.com/raspberrypi/firmware/issues/1619#issuecomment-917025502



Due to this change in firmware behavior, bcm2835_get_mmc_clock now
returns a clock rate of zero since we do not issue SET_CLOCK_RATE.
This results in degraded MMC performance.

SET_CLOCK_RATE fixes the clock to a specific value and disables scaling
so is not an ideal solution.

Instead, fallback to GET_MAX_CLOCK_RATE in bcm2835_get_mmc_clock if
GET_CLOCK_RATE returns zero.

Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

- Assorted TI platform fixes, correct location of NXP boot format git
  repository, don't try and mount partitions that are too small to be
  ext4 as ext4, handle .bin files in .gitattributes, flush out panic
  messages for sure, and correct console location on Arm total_compute.

Setting RX flow error handling will stall the channel until descriptors
are available to move RX data. Setting this bit causes issues when
tearing down ethernet DMA channel at the end of TFTP transfer as
unrelated network packets can cause teardown to stall indefinitely waiting
for driver to queue add more desc leading to channel hang with error
logs:
udma_stop_dev2mem TIMEOUT !
udma_stop_dev2mem: peer not stopped TIMEOUT !
udma_stop_dev2mem TIMEOUT !

Fix this by clearing rx_error_handling similar to how its done for UDMA
as part of udma_alloc_rchan_sci_req()

This fixes occasional TFTP Failures seen when downloading multiple files
one after the other on AM64/AM62 SoCs.

Fixes: 9a92851c ("dma: ti: k3-udma: Add BCDMA and PKTDMA support")
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

No need to mount a too small partition to handle a EXT4 file system.

This patch add a test on partition size before to read the
SUPERBLOCK_SIZE buffer and avoid error latter in fs_devread() function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Binary files, which are committed to a private fork of this repository,
will be subject to line feed substitution unless marked as binary.

Mark .bin files as binary.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Setting sf default mode to 0x3 breaks sf update when we do SF read
through u-boot console.

This issue arises when we do a splash image through OSPI flash media,
to fix this set the default mode to 0x0.

Fixes: 04150400 ("configs: enable OSPI related configs in AM62x")
Signed-off-by: Nikhil M Jain <n-jain1@ti.com>

Remapping console logs from soc uart2 (s1 terminal)
to css non-secure (uart_ap terminal)

Signed-off-by: Annam Sai Manisha <annam.saimanisha@arm.com>

On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.

This means we will need to move the stack & heap from OCSRAM to HSM RAM
and reduce the size of BSS and the SPL to allow it to fit properly.

To protect us from overflowing our ~256k of HSM SRAM, add limits and
check during the wakeup SPL build.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

On high security devices, ROM enables firewalls to protect the OCSRAM
region access during bootup. Only after TIFS has started (and had
time to disable the OCSRAM firewall region) will we have write access to
the region.

So, move scratch board area to HSM RAM.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

To make sure the panic and the reset messages will go out, console flush() should be used.
Sleep periods do not work in early u-boot phase when timer driver is not initialized yet.

Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html



Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

As explained in the text at the bottom of the page
https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format

:

"QUIC repositories on this site will not receive any updates after
March 31, 2022, and will be deleted on March 31, 2023."

Point to the NXP boot format github repo instead.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>

- odroid-go-ultra: setup PMIC regulators at board init

A single reset controller driver (part of the clock driver) fix
for v2023.04 release.

- Fix for rockchip timer driver;
- Fix for rk3568 and rk3588 boot device and clock driver;
- Fix for rk3568 reset handler;
- Fix for rk3568 sdhci DLL at 52MHz;

The reset identifier must be processed via MOD_CLK_PACK() before it is
used to look up register and bit within reset_regs or reset_clear_regs
arrays, otherwise completely bogus register and bit is picked from the
arrays, one which may even be out of range.

Fixes: 326e05c5 ("clk: renesas: Add and enable CPG reset driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

The Rockchip timer driver has been renamed after the fall back compatible.
There's no need to replace the timer compatible in rk3188-radxarock-u-boot.dtsi
anymore, so remove.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

In the binding for the Rockchip timer the compatible string
consists of a SoC orientated string and a fall back string
"rockchip,rk3288-timer", so remove all unneeded ones and
fix driver name.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

For Rockchip platform, DLL bypass bit and start bit need to be set if
DLL is not locked.

With this change applied eMMC in my NanoPi R5S can run at 52 MHz.

Based on linux commit b75a52b0dda3 ("mmc: sdhci-of-dwcmshc: Update DLL
and pre-change delay for rockchip platform")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

This reverts commit 5bec4b0de7851a254fb4447b3599a60f95550141.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>