- Dec 23, 2021
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Will Eccles authored
When CONFIG_PM is not enabled, the function davinci_mdio_update_dt_from_phymask is not defined. This patch fixes this so that the build does not fail with CONFIG_PM disabled. Signed-off-by:Will Eccles <will@eccles.dev>
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Jay at Control Module Industries authored
I have encountered the same issue(s) on A6A boards. I couldn't find a patch, so I wrote this patch to update the device tree in the davinci_mdio driver in the 3.15.1 tree, it seems to correct it. I would welcome any input on a different approach. https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/SRlnumt0LoMJ v4.1-rcX: added hack around CONFIG_OF_OVERLAY v4.2-rc3+: added if (of_machine_is_compatible("ti,am335x-bone")) so we do not break dual ethernet am335x devices Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
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Robert Nelson authored
This reverts commit 956b200a. Signed-off-by:
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Robert Nelson authored
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Robert Nelson authored
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Robert Nelson authored
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Robert Nelson authored
This reverts commit 26c7295b. Signed-off-by:
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Robert Nelson authored
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Robert Nelson authored
v5.10.9-2021_1020 Signed-off-by: -
Robert Nelson authored
Reference: v5.10.9 Signed-off-by: -
Robert Nelson authored
Reference: v5.15.11 Signed-off-by: -
Robert Nelson authored
Reference: v5.13.19 Signed-off-by: -
Robert Nelson authored
Reference: v5.13.19 Signed-off-by: -
Robert Nelson authored
Reference: v5.12.19 Signed-off-by: -
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Robert Nelson authored
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Robert Nelson authored
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Jason Kridner authoredFrom https://github.com/statropy/wpanusb
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Robert Nelson authored
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Robert Nelson authored
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Robert Nelson authored
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Robert Nelson authored
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Robert Nelson authored
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- Dec 22, 2021
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LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arch: arm64: ti: Add support J721S2 Common Processor Board arm64: dts: ti: Add initial support for J721S2 System on Module arm64: dts: ti: Add initial support for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 dt-bindings: arm: ti: Add bindings for J721s2 SoC dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC soc: ti: k3-socinfo: Add entry for J721S2 SoC family drivers: dma: ti: k3-psil: Add support for J721S2 dmaengine: ti: k3-udma: Add SoC dependent data for J721S2 SoC phy: phy-can-transceiver: Make devm_gpiod_get optional arm64: defconfig: Increase the maximum number of 8250/16550 serial ports ti_config_fragments: v8_baseport.cfg: Increase the number of instance of UARTs Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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Aswath Govindraju authored
commit effb32e9 upstream. The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Common Processor Board: https://www.ti.com/tool/J721EXCPXEVM Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211207080904.14324-6-a-govindraju@ti.com
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Aswath Govindraju authored
commit d502f852 upstream. A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. SoM: https://www.ti.com/lit/zip/sprr439 Signed-off-by:
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Aswath Govindraju authored
commit b8545f9d upstream. The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 â NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
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Aswath Govindraju authored
commit beba81fa upstream. Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211207080904.14324-3-a-govindraju@ti.com
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Aswath Govindraju authored
commit 6b1caf4d upstream. Add binding for J721S2 SoC Signed-off-by:
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Aswath Govindraju authored
commit aff1016220a5970873700a88538b5d254326abc6 upstream. There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by:
Peter Rosin <peda@axentia.se>
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Aswath Govindraju authored
commit a34ff76a upstream. J721S2 SoC's JTAG PARTNO is 0xBB75. Signed-off-by:
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Aswath Govindraju authored
commit 0d6e87ab7c134a920d59610d6f1da60ba3ced3f9 upstream. Add support for J721S2 SOC. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20211119132315.15901-3-a-govindraju@ti.com Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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Aswath Govindraju authored
commit 754cd176161f7a8b8b897619c97a7139eee4a9cf upstream. Add SYSFW defined rchan_oes_offset number for J721S2 SoC in soc data. Signed-off-by:
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