With the required patch already being upstream, we can now redirect
users to the standard vanilla DTC tree.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>

Arduino Due now uses ASF. The timestamps.c file was still
using old register definitions.

Signed-off-by: Justin Watson <jwatson5@gmail.com>

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

The 0.9.1 SDK is now required to cover all architectures and to enable
tests on all plartforms supported.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

This image installs sphinx 1.5.5 which is the version currently
supported by Zephyr. Newer versions seem to have issues building our
documentation.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Check that we have <subsystem>: <subject> in commit messages.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

EEPROM read mode is a specific mode where the controller will TX a
command to the slave, and once done, will read as many bytes requested.
The gain relies in the controller generating all necessary dummy bytes
by itself to read data the from slave, it will only generate RX
interrupts. Thus reducing CPU work.
Obviously TX and RX buffers should be relevantly provided by the user.

If not supported by the controller, the driver can still work (it will
have to generate the dummy bytes) and thus -EINVAL should not be
returned for that configuration bit.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

If CS is controlled over GPIO, it will be possible to keep the slave up
and running (though no transaction will be going on) using this
configuration bit.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Again this is made as generic as possible through driver's
spi_context API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

SPI_HOLD_ON_CS can be used to ask the SPI device to keep CS on, after
the transaction. And this undefinitely, until another config is used.
This will inhibate the gpio cs delay, if any. This might be useful when
doing consecutive calls on one slave without releasing the CS.

SPI_LOCK_ON is to be used with caution as it will keep the SPI device
locked for the current config being used after each transaction. This
can be necessary if one needs to do consecutive calls on a slave without
any olher caller to interfere.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

This gives a quicke example on how to use SPI asynchronous calls with
kernel's k_poll API.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

All is done through the generic spi_context driver's API as it will be
generic to all SPI drivers.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Adding a struct k_poll_signal parameter to driver's API unique
exposed function.

If not NULL, the call will be handled as asynchronous and will
return right after the transaction has started, on the contrary
of current logic where is waits for the transaction to finish
(= synchronous).

In order to save stack, let's move the device pointer to struct
spi_config. So the call is still at a maximum of 4 parameters.

Adapting spi_dw.c and spi driver sample to the change so it still
builts.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

All SPI drivers have this same way to handle synchronous call, thus
let's generalize it in struct spi_context, with a relevant API and apply
the change into SPI DW driver.

spi_context API will prove to be useful once asynchronous call will be
handled as well, through the same completion functions used now only for
synchronous call. It will be transparent for the driver.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Let's improve common SPI driver context by adding a lock and generic
function to get/release it.

It's statically initialized to save a bit of ROM.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

This application intents to test an SPI driver by looping over MISO/MOSI
line where the controller will then send data to itself.

It will test various buffer tx/rx schemes.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Introducing as well a generic driver helper for CS gpio control and
buffer management.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Such API improves many aspects of the former API by reducing the number
of function, allowing more buffer flexibility etc... This leads in
better memory usag and performance as well.

However, as this will take sometime to get into use, the former API is
still present and is the one enabled by default.

Jira: ZEP-852
Jira: ZEP-287
Jira: ZEP-1725

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Set the right definitions to be able to use SPI_DW instead of SPI_QMSI.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

One liners if/for/while statements still need {}
(and line break are cheap for clarity).

Aligning parameters properly.

Also, removing __func__ usage from SYS_LOG_* as these macros already put
it internally.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>

Eliminate following errors:

make[2]: /home/nashif/Work/sdk/xtools/outdir/x-tools//bin/-gcc: Command
not found
make[2]: /home/nashif/Work/sdk/xtools/outdir/x-tools//bin/-gcc: Command
not found
make[2]: /home/nashif/Work/sdk/xtools/outdir/x-tools//bin/-gcc: Command
not found

Also, usage of CROSS_COMPILE with a predefined toolchain is not required and
complicates things, just call CROSS_COMPILE with the full path if you
want to build with a toolchain not supported with Zephyr.

Change-Id: I93ec4ff2e04d22cee82c8e4b74b652927572b30a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Removed the old PWM APIs usage and added support for the new PWM API.

JIRA: ZEP-2018

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

This change moves to a project specific container with the latest SDK
which adds support for xtensa HALs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

The data fragments were stored in reversed order when the RX
data was saved into network buffers. This was caused by net_pkt
changes in commit db11fcd1 "net/net_pkt: Fully separate struct
net_pkt from struct net_buf".

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

Since MSYS2 provides a UNIX-like environment, treating it as a Windows
build caused issues with the paths.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>

Since the PHY update complete event can be generated due to the
procedure being initiated by the peer, use a flag to
differentiate between local auto update initiated on connection
complete versus peer initiated anytime in the connection. This
is necessary to avoid repeated initiation of auto-update
procedures intended only to be issued on connection complete.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>

fixed typo: mnormm -> -mnorm

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

MinGW is old and unsupported, and it does not even download properly
these days. Remove the instructions that rely on MinGW since they are
only confusing for people trying to build on Windows.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>

The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.

This particular controller has the following properties :
 - Up to 2 512KiB banks divided in 2KiB pages
 - Flash can be accessed in any sizes
 - Flash must be written in 64bit aligned 64bit double-words

The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.

To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

A typo was present ion the erase and write function were bit were
uncorrectly unset but all other bit except the mask were unset.
The code still worked because the two typos fixed themselves.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

The RDERR bit is not present on F4x5 and F4x7 SoCs, so only use it when
available in the HAL.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Limit visibility of configurable TX pins to SAME70 series only.
Previously visibility of configurable SAME70 TX pins extended
to the full SAM family.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>

Neither ASF nor CMSIS provide defines that can be processed by
the assembler. Exclude those from soc.h. Before this was done
incorrectly in board.h file.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>

Removed CONFIG_HAS_DTS from the stm32f4_disco_defconfig &
stm32l496g_disco_defconfig files as its automatically selected for all
ARM SoCs at this point.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>