- Bring MMUART1 to P9 cape connector. P9_24: TXD, P9_26: RXD.
- Remove USB, PCM and UART from M.2 connector.

Let I/O pads propagate to the top level of the design and rename as
required.

Couple the pin constraint files with the variant of design blocks.
This should allow us to customize cape I/Os to best suit a specific
cape. It also allows to easily include or excluse a block from the
design. For example, not include cape, M.2, MIPI-CSI or high speed
interface if not required and tight on FPGA resources.

  - Adjust DDR memory layout to match the Icicle Kit's 2022.02 release
    (move to 64-bit address range).

  - Temporary removal of MIPI-CSI interface.

  - Add over-current input to MSS GPIO_1 input 23.
  - Rename USB signal names to match shcematics.

  - Add details of pins usage.
  - List all FPGA pin assignments to headers P8 and P9.

  - Add PLL to generate 4.915MHz clock for ADC_MCLK.
  - Connect ADC interrupt to MSS GPIO 1 input 20.

  - Connect Ethernet management interface to PHY.
  - Connect PHY reset input to FPGA system reset.
  - Connect PHY interrupt to MSS F2M fabric interrupt 2.