Fix syntax error
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- sources/FPGA-design/script_support/components/CAPE/FIREBIRD_CAPE/HDL/CAPE.v 0 additions, 2 deletions...n/script_support/components/CAPE/FIREBIRD_CAPE/HDL/CAPE.v
- sources/FPGA-design/script_support/components/CAPE/FIREBIRD_CAPE/device-tree-overlay/bvf/MPFS025T/FCVG484/verilog-cape.dtso 1 addition, 1 deletion...evice-tree-overlay/bvf/MPFS025T/FCVG484/verilog-cape.dtso
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