Adds Softcore component to BVF gateware

This MR is for GSoC 2024 Project Low-Latency I/O RiscV core on FPGA fabric of BeagleV-Fire.

• Documentation for using the softcore merged: Merge Request
• Working of the project: GSoC Final Report
• Here is the detailed view of new files and changes in existing files.

TCL Scripts

• BVF_gateware.tcl - Adds source file for softcore component.
• BVF_riscv_subsystem.tcl - Adds APB slave bus connections.
• FIC3_Initiator.tcl - Enables the 12th slot for softcore APB bus.
• Build_bvf_gateware.tcl - Adds softcore option and new download cores for softcore AXI DP LSRAM as program memory.
• picorv-softcore.yaml - Adds a PicoRV softcore build option.
• SoftCore/ - Contains all TCL scripts and HDL with directory structure.

Softcore Options

• NONE - No softcore option.
• PICO-RISCV - PicoRV32 softcore option.

Device Tree Overlay

• Device tree overlay - Adds device tree overlay for softcore with AXI LSRAM address and size.

Firmware

• firmware/ - Contains firmware components for PicoRV32 (this directory should be copied to the BVF via SSH).
  • AXI_test.c - Used in BVF Linux to flash program on board.
  • firmware.c - Contains boilerplate code to run on the softcore.
  • firmware.h - Contains custom helper functions for IO operations, called in firmware.c to run on the softcore.
  • latency-test.c - Contains test program to test IO latency of the softcore.
  • generatehex.sh - Compilation script to compile firmware.c into a program hex file.

HDL Code

• HDL/ - Contains all the HDL code for the softcore.
  • IO-controller.v - Holds the memory-mapped IO and register-mapped IO module.
  • picorv32.v - Main CPU model for PicoRV32.
  • BVF_Wrapper.v - Wrapper module for PicoRV32 to interconnect the CPU with memory, IO, etc.
  • APB_ctrl.v - Holds the APB slave for control register for the softcore.
  • Top_control.v - Main module to connect the wrapper module with the CPU and APB slave to CAPE and BVF Subsystem in BVF gateware.

Additional TCL Scripts

• ADD_softcore.tcl - Connects the softcore component in the main component.
• CORE_AXI_Interconnect.tcl - IP block for master-slave AXI connection to the LSRAM from the BVF RISC-V Subsystem.
• LOLA_SOFTCORE.tcl - Generates SmartDesign for softcore.
• PF_SRAM_AHB_AXI_C0.tcl - IP block for Dual-Port AXI-native LSRAM.
• PROGRAM_INIT.tcl - Converts program_dump.hex in firmware to Intel Hex format to initialize in LSRAM (currently will not work with GitLab CI).

Let me know if any changes are to be made here.