- Sep 12, 2016
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LCPD Auto Merger authored
TI-Feature: ti_linux_base_rt TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.4.y * 'ti-linux-4.4.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: ARM: dts: keystone-k2g: Reserve SRAM for MPM ARM: dts: keystone-k2e: Reserve SRAM for MPM ARM: dts: keystone-k2l: Reserve SRAM for MPM ARM: dts: keystone-k2hk: Reserve SRAM for MPM TEMP: soc: ti: keystone-dsp-mem: use sram child nodes for MSM RAM ARM: dts: keystone-k2g-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2e-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2l-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2hk-evm: Remove MSM memory from dspmem node TEMP: soc: ti: keystone_dsp_mem: create sysfs entries for memories ARM: dts: keystone-k2g: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2e: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2l: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2hk: Reserve MSM RAM for boot monitor ARM: configs: keystone: Enable Generic on-chip SRAM driver ARM: dts: keystone-k2g: Add MSM RAM node ARM: dts: keystone-k2e: Add MSM RAM node ARM: dts: keystone-k2l: Add MSM RAM node ARM: dts: keystone-k2hk: Add MSM RAM node Signed-off-by:LCPD Auto Merger <lcpd_integration@list.ti.com>
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git://git.ti.com/rpmsg/rpmsgLCPD Auto Merger authored
TI-Feature: rpmsg TI-Tree: git://git.ti.com/rpmsg/rpmsg.git TI-Branch: rpmsg-ti-linux-4.4.y-intg * 'rpmsg-ti-linux-4.4.y-intg' of git://git.ti.com/rpmsg/rpmsg : ARM: dts: keystone-k2g: Reserve SRAM for MPM ARM: dts: keystone-k2e: Reserve SRAM for MPM ARM: dts: keystone-k2l: Reserve SRAM for MPM ARM: dts: keystone-k2hk: Reserve SRAM for MPM TEMP: soc: ti: keystone-dsp-mem: use sram child nodes for MSM RAM ARM: dts: keystone-k2g-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2e-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2l-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2hk-evm: Remove MSM memory from dspmem node TEMP: soc: ti: keystone_dsp_mem: create sysfs entries for memories ARM: dts: keystone-k2g: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2e: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2l: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2hk: Reserve MSM RAM for boot monitor ARM: configs: keystone: Enable Generic on-chip SRAM driver ARM: dts: keystone-k2g: Add MSM RAM node ARM: dts: keystone-k2e: Add MSM RAM node ARM: dts: keystone-k2l: Add MSM RAM node ARM: dts: keystone-k2hk: Add MSM RAM node Signed-off-by:
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git://git.ti.com/rpmsg/remoteprocSuman Anna authored
Pull in the updated remoteproc feature branch that represents the Multicore Shared Memory (MSM) RAM as mmio-sram nodes, and reserves the portions of it used by Keystone 2 Boot Monitor (BM). The series also enhances the keystone-dsp-mem driver to present sysfs entries to userspace for the memories managed by it. The driver is updated to use the SRAM driver infrastructure, and uses specific child nodes to reserve portions of the MSM RAM for exposing them to userspace for the Multi Proc Manager (MPM) stack on all Keystone 2 SoCs. * 'rproc-linux-4.4.y' of git://git.ti.com/rpmsg/remoteproc : ARM: dts: keystone-k2g: Reserve SRAM for MPM ARM: dts: keystone-k2e: Reserve SRAM for MPM ARM: dts: keystone-k2l: Reserve SRAM for MPM ARM: dts: keystone-k2hk: Reserve SRAM for MPM TEMP: soc: ti: keystone-dsp-mem: use sram child nodes for MSM RAM ARM: dts: keystone-k2g-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2e-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2l-evm: Remove MSM memory from dspmem node ARM: dts: keystone-k2hk-evm: Remove MSM memory from dspmem node TEMP: soc: ti: keystone_dsp_mem: create sysfs entries for memories ARM: dts: keystone-k2g: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2e: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2l: Reserve MSM RAM for boot monitor ARM: dts: keystone-k2hk: Reserve MSM RAM for boot monitor ARM: configs: keystone: Enable Generic on-chip SRAM driver ARM: dts: keystone-k2g: Add MSM RAM node ARM: dts: keystone-k2e: Add MSM RAM node ARM: dts: keystone-k2l: Add MSM RAM node ARM: dts: keystone-k2hk: Add MSM RAM node Signed-off-by:
Suman Anna <s-anna@ti.com>
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Suman Anna authored
Add a child SRAM node to reserve a portion of the Multicore Shared Memory (MSM) RAM for use by the keystone-dsp-mem driver on 66AK2G SoCs. This memory will be exposed to the userspace for meeting the needs of the Multi Proc Manager (MPM) stack. A preliminary size of 512 KB is reserved to begin with and can be adjusted as per need. Signed-off-by: -
Suman Anna authored
Add a child SRAM node to reserve a portion of the Multicore Shared Memory (MSM) RAM for use by the keystone-dsp-mem driver on 66AK2E SoCs. This memory will be exposed to the userspace for meeting the needs of the Multi Proc Manager (MPM) stack. A preliminary size of 512 KB is reserved to begin with and can be adjusted as per need. Signed-off-by: -
Suman Anna authored
Add a child SRAM node to reserve a portion of the Multicore Shared Memory (MSM) RAM for use by the keystone-dsp-mem driver on 66AK2L SoCs. This memory will be exposed to the userspace for meeting the needs of the Multi Proc Manager (MPM) stack. A preliminary size of 512 KB is reserved to begin with and can be adjusted as per need. Signed-off-by: -
Suman Anna authored
Add a child SRAM node to reserve a portion of the Multicore Shared Memory (MSM) RAM for use by the keystone-dsp-mem driver on 66AK2H SoCs. This memory will be exposed to the userspace for meeting the needs of the Multi Proc Manager (MPM) stack. A preliminary size of 512 KB is reserved to begin with and can be adjusted as per need. Signed-off-by: -
Suman Anna authored
The Keystone 2 SoCs have an on-chip RAM controlled by the Multicore Shared Memory Controller (MSMC). The keystone-dsp-mem driver exposes this MSM memory to userspace for the Multi Proc Manager (MPM) stack, and relied on using the standard 'reg' property before. This MSM RAM can be used by different client drivers and so is now represented as a mmio-sram node and managed by the standard SRAM driver. The keystone-dsp-mem driver has been enhanced to switch to use the SRAM driver provided infrastructure to use MSM RAM. The logic depends on marking the required SRAM regions as 'reserved' child nodes under the parent MSM SRAM node with a specific "ti,keystone-dsp-msm-ram" compatible property, and can scale to multiple discrete nodes. Signed-off-by: -
Suman Anna authored
Remove the current MSM RAM memory being defined and used within the dspmem node. The keystone_dsp_mem driver will be enhanced to use the MSM RAM regions by means of defining appropriate child nodes under the MSM SRAM node. While at this, also fix the missing unit name on the dspmem node. Signed-off-by: -
Suman Anna authored
Remove the current MSM RAM memory being defined and used within the dspmem node. The keystone_dsp_mem driver will be enhanced to use the MSM RAM regions by means of defining appropriate child nodes under the MSM SRAM node. While at this, also fix the missing unit name on the dspmem node. Signed-off-by: -
Suman Anna authored
Remove the current MSM RAM memory being defined and used within the dspmem node. The keystone_dsp_mem driver will be enhanced to use the MSM RAM regions by means of defining appropriate child nodes under the MSM SRAM node. While at this, also fix the missing unit name on the dspmem node. Signed-off-by: -
Suman Anna authored
Remove the current MSM RAM memory being defined and used within the dspmem node. The keystone_dsp_mem driver will be enhanced to use the MSM RAM regions by means of defining appropriate child nodes under the MSM SRAM node. While at this, also fix the missing unit name on the dspmem node. Signed-off-by: -
Suman Anna authored
The keystone-dsp-mem driver is enhanced to provide sysfs entries to allow userspace to read the address and size of supported DDR and Multicore Shared Memory (MSM) RAM memories that are exposed to userspace. This sysfs logic provides an agnostic way of presenting the supported memories irrespective of how the driver acquires the memories. Each supported memory region is represented by its own directory, and are created under the dspmem misc device. The directories can be accessed under the /sys/class/misc/dspmem/ path. Signed-off-by: -
Suman Anna authored
The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c0f7000 on 66AK2G SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: -
Suman Anna authored
The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c1f0000 on 66AK2E SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: -
Suman Anna authored
The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c1f8000 on 66AK2L SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: -
Suman Anna authored
The Keystone 2 boot monitor uses 32 KB of the MSM RAM @ 0x0c5f0000 on 66AK2H SoCs, so add a reserved child node for the same. This address is aligned to the values used within the latest boot monitor firmware [1] as of commit cf8b431e8b3b ("soc: Move load address to end of MSMC"). [1] git://git.ti.com/processor-firmware/ks2-boot-monitor.git Signed-off-by: -
Suman Anna authored
All the Keystone 2 SoCs have an on-chip RAM called the MultiCore Shared Memory (MSM) RAM managed by the Multicore Shared Memory Controller (MSMC) that provides faster access compared to normal DDR. This patch enables the Generic on-chip SRAM driver that manages this memory in software. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
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Suman Anna authored
Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2G SoCs have 1 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by:
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Suman Anna authored
Add the RAM managed by the Multicire Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2E SoCs have 2 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by:
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Suman Anna authored
Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2L SoCs have 2 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by:
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Suman Anna authored
Add the RAM managed by the Multicore Shared Memory Controller (MSMC) as a mmio-sram node. The 66AK2H SoCs have 6 MB of such memory. Any specific MSM memory range needed by a software module ought to be reserved using an appropriate child node. Signed-off-by:
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- Sep 08, 2016
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LCPD Auto Merger authored
TI-Feature: ti_linux_base_rt TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.4.y * 'ti-linux-4.4.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: Documentation: DT: net: cpsw: remove no_bd_ram property net: ethernet: ti: cpsw: add support for descs_pool_size dt property Documentation: DT: net: cpsw: allow to specify descriptors pool size net: ethernet: ti: cpsw: use devm_ioremap net: ethernet: ti: cpsw: minimize number of parameters in cpdma_desc_pool_create/destroy() net: ethernet: ti: cpdma: fix desc re-queuing net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr ARM: dts: k2l: Fix serdes phy dt binding Signed-off-by: -
LCPD Auto Merger authored
Merge branch 'connectivity-ti-linux-4.4.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.4.y TI-Feature: connectivity TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git TI-Branch: connectivity-ti-linux-4.4.y * 'connectivity-ti-linux-4.4.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel : Documentation: DT: net: cpsw: remove no_bd_ram property net: ethernet: ti: cpsw: add support for descs_pool_size dt property Documentation: DT: net: cpsw: allow to specify descriptors pool size net: ethernet: ti: cpsw: use devm_ioremap net: ethernet: ti: cpsw: minimize number of parameters in cpdma_desc_pool_create/destroy() net: ethernet: ti: cpdma: fix desc re-queuing net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr ARM: dts: k2l: Fix serdes phy dt binding Signed-off-by:
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Grygorii Strashko authored
Even if no_bd_ram property is described in TI CPSW bindings the support for it has never been introduced in CPSW driver, so there are no real users of it. Hence, remove no_bd_ram property. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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Grygorii Strashko authored
The CPSW CPDMA can process buffer descriptors placed as in internal CPPI RAM as in DDR. This patch adds support in CPSW and CPDMA for descs_pool_size DT property, which defines total number of CPDMA CPPI descriptors to be used for both ingress/egress packets processing: - memory size required for CPDMA descriptor pool is calculated basing on number of descriptors specified by user in descs_pool_size and CPDMA descriptor size; - allocate CPDMA descriptor pool in DDR if pool memory size > internal CPPI RAM or use internal CPPI RAM otherwise; - if descs_pool_size not specified in DT - the default value 256 will be used which will allow to place CPDMA descriptors pool into the internal CPPI RAM (current default behaviour); - CPDMA will ignore descs_pool_size if descs_pool_size = 0 for backward comaptiobility with davinci_emac. Signed-off-by:
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Grygorii Strashko authored
Add optional property "descs_pool_size" to specify buffer descriptor's pool size. The "descs_pool_size" should define total number of CPDMA CPPI descriptors to be used for both ingress/egress packets processing. If not specified - the default value 256 will be used which will allow to place descriptor's pool into the internal CPPI RAM on most of TI SoC. Signed-off-by:
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Grygorii Strashko authored
Use devm_ioremap() and simplify the code. Signed-off-by:
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Grygorii Strashko authored
Update cpdma_desc_pool_create/destroy() to accept only one parameter struct cpdma_ctlr*, as this structure contains all required information for pool creation/destruction. Signed-off-by:
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Grygorii Strashko authored
The currently processing cpdma descriptor with EOQ flag set may contain two values in Next Descriptor Pointer field: - valid pointer: means CPDMA missed addition of new desc in queue; - null: no more descriptors in queue. In the later case, it's not required to write to HDP register, but now CPDMA does it. Hence, add additional check for Next Descriptor Pointer != null in cpdma_chan_process() function before writing in HDP register. Signed-off-by:
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Grygorii Strashko authored
It's observed that cpsw/cpdma is not working properly when CPPI descriptors are placed in DDR instead of internal CPPI RAM on am437x SoC: - rx/tx silently stops processing packets; - or - after boot it's working for sometime, but stuck once Network load is increased (ping is working, but iperf is not). (The same issue has not been reproduced on am335x and am57xx). It seems that write to HDP register processed faster by interconnect than writing of descriptor memory buffer in DDR, which is probably caused by store buffer / write buffer differences as these function are implemented differently across devices. So, to fix this i come up with two changes: 1) all accesses to the channel register HDP/CP/RXFREE registers should be done using sync IO accessors readl()/writel(), because all previous memory writes writes have to be completed before starting channel (write to HDP) or completing desc processing. 2) the change 1 only doesn't work on am437x and additional reading of desc's field is required right after the new descriptor was filled with data and before pointer on it will be stored in prev_desc->hw_next field or HDP register. Signed-off-by:
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Murali Karicheri authored
#phy-cells was missing in the DT bindings for netcp serdes devices that causes netcp driver to spit out following error logs:- [ 1.343696] /soc/netcp@26000000/netcp-devices/gbe@200000/interfaces/interface-0: could not get #phy-cells for /soc/phy@232a000/lane@0 [ 1.355681] /soc/netcp@26000000/netcp-devices/gbe@200000/interfaces/interface-1: could not get #phy-cells for /soc/phy@232a000/lane@1 [ 1.367660] /soc/netcp@26000000/netcp-devices/gbe@200000/secondary-slave-ports/port-2: could not get #phy-cells for /soc/phy@2320000/lane@0 [ 1.893129] /soc/netcp@26000000/netcp-devices/gbe@200000/secondary-slave-ports/port-3: could not get #phy-cells for /soc/phy@2320000/lane@1 [ This patch fixes the issue. Fixes: 762fc5d0 ("ARM: dts: keystone: update SerDes bindings for one PHY per lan") Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: ti_linux_base_rt TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.4.y * 'ti-linux-4.4.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: ARM: dts: DRA7: Fix tbclk phandle for ehrpwm nodes ARM: dts: dra72-evm: Prevent glitch on DCAN1 pinmux Signed-off-by: -
LCPD Auto Merger authored
Merge branch 'connectivity-ti-linux-4.4.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.4.y TI-Feature: connectivity TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git TI-Branch: connectivity-ti-linux-4.4.y * 'connectivity-ti-linux-4.4.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel : ARM: dts: DRA7: Fix tbclk phandle for ehrpwm nodes ARM: dts: dra72-evm: Prevent glitch on DCAN1 pinmux Signed-off-by:
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- Sep 07, 2016
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LCPD Auto Merger authored
TI-Feature: ti_linux_base_rt TI-Tree: git@git.ti.com:ti-linux-kernel/ti-linux-kernel.git TI-Branch: ti-linux-4.4.y * 'ti-linux-4.4.y' of git.ti.com:ti-linux-kernel/ti-linux-kernel: drm/tilcdc: WARN if CRTC is touched without CRTC lock drm/tilcdc: Take CRTC lock when calling tilcdc_crtc_disable() drm/tilcdc: Remove unnecessary tilcdc_crtc_disable() from tilcdc_unload() drm/tilcdc: Flush flip-work workqueue before drm_flip_work_cleanup() drm/tilcdc: Clean up LCDC functional clock rate setting code drm/tilcdc: Take crtc modeset lock while updating the crtc clock rate ARM: dts: K2G: add LCD backlight ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node drm/tilcdc: Choose console BPP that supports RGB drm/tilcdc: Add blue-and-red-crossed devicetree property drm/tilcdc: Write DMA base and ceiling address with single instruction drm/tilcdc: Enable EOF interrupts for v1 LCDC drm/tilcdc: Adjust the FB_CEILING address drm/tilcdc: Fix check for remote port parent Signed-off-by: -
Dan Murphy authored
Merge branch 'audio-display-ti-linux-4.4.y' of git.ti.com:~darrene/ti-linux-kernel/audio-display-linux-feature-tree into ti-linux-4.4.y TI-Feature: audio-display TI-Tree: git@git.ti.com:~darrene/ti-linux-kernel/audio-display-linux-feature-tree.git TI-Branch: audio-display-ti-linux-4.4.y * 'audio-display-ti-linux-4.4.y' of git.ti.com:~darrene/ti-linux-kernel/audio-display-linux-feature-tree: drm/tilcdc: WARN if CRTC is touched without CRTC lock drm/tilcdc: Take CRTC lock when calling tilcdc_crtc_disable() drm/tilcdc: Remove unnecessary tilcdc_crtc_disable() from tilcdc_unload() drm/tilcdc: Flush flip-work workqueue before drm_flip_work_cleanup() drm/tilcdc: Clean up LCDC functional clock rate setting code drm/tilcdc: Take crtc modeset lock while updating the crtc clock rate ARM: dts: K2G: add LCD backlight ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node drm/tilcdc: Choose console BPP that supports RGB drm/tilcdc: Add blue-and-red-crossed devicetree property drm/tilcdc: Write DMA base and ceiling address with single instruction drm/tilcdc: Enable EOF interrupts for v1 LCDC drm/tilcdc: Adjust the FB_CEILING address drm/tilcdc: Fix check for remote port parent Signed-off-by:Dan Murphy <dmurphy@ti.com>
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Vignesh Raghavendra authored
Commit bda9c3d4 ("ARM: dts: dra7xx/am437x/am33xx/da850: Add new ECAP and EPWM bindings") had a copy paste error due which clock phandle of tbclk was not set correctly for ehrpwm1 and ehrpwm2 nodes. Fix this by populating proper phandles. Fixes: bda9c3d4 ("ARM: dts: dra7xx/am437x/am33xx/da850: Add new ECAP and EPWM bindings") Reported-by:
Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by:
Vignesh R <vigneshr@ti.com> Signed-off-by:
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Jyri Sarha authored
Merge branch 'ti/4.4-pull' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into audio-display-ti-linux-4.4.y omapdrm changes for 2016.04, part 2 * 'ti/4.4-pull' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: ARM: dts: K2G: add LCD backlight
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Jyri Sarha authored
LCDC rev 2 (am335x) color errata fix and some other cleanups and fixes. * tiL4.4-tilcdc-atomic-wip: drm/tilcdc: WARN if CRTC is touched without CRTC lock drm/tilcdc: Take CRTC lock when calling tilcdc_crtc_disable() drm/tilcdc: Remove unnecessary tilcdc_crtc_disable() from tilcdc_unload() drm/tilcdc: Flush flip-work workqueue before drm_flip_work_cleanup() drm/tilcdc: Clean up LCDC functional clock rate setting code drm/tilcdc: Take crtc modeset lock while updating the crtc clock rate ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node drm/tilcdc: Choose console BPP that supports RGB drm/tilcdc: Add blue-and-red-crossed devicetree property drm/tilcdc: Write DMA base and ceiling address with single instruction drm/tilcdc: Enable EOF interrupts for v1 LCDC drm/tilcdc: Adjust the FB_CEILING address drm/tilcdc: Fix check for remote port parent
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