- Mar 04, 2024
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Robert Nelson authored
6.6.15-ti-arm64-r1 bb.org_defconfig 6.6 TI Delta: https://github.com/RobertCNelson/ti-linux-kernel/compare/755274496cb38d395e5c7c572d73da596e5f7994...6d076a58afac440c9d108e0db11a35190ea5686f BBDTBS: beagleboard/BeagleBoard-DeviceTrees@81dd4695 WIRELESS_REGDB: https://git.kernel.org/pub/scm/linux/kernel/git/wens/wireless-regdb.git/commit/?id=454130065a5857bc0c534d5c52ed17a97b704c36 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Kishon Vijay Abraham I authored
Lets drive Sierra clock output and workaround a TIFS/DM bug for now. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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Jason Kridner authored
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Robert Nelson authored
Reference: rpi-6.6.y Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Matthijs van Duin authored
"uio" for generic use "ti,pruss-shmem" for backwards compatibility the of_id module parameter is still supported to add another id
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Matthijs van Duin authored
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Robert Nelson authored
Reference: v5.10.211 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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- Feb 28, 2024
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Devarsh Thakkar authored
commit 0f9eb43f upstream. This adds common1 register space for AM62A SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: 36188116 ("arm64: dts: ti: k3-am62a-main: Add node for Display SubSystem (DSS)") Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Reviewed-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20240216062426.4170528-5-devarsht@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Devarsh Thakkar authored
commit 7d8ee2c3 upstream. This adds common1 register space for AM62x SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: 8ccc1073 ("arm64: dts: ti: k3-am62-main: Add node for DSS") Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Reviewed-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20240216062426.4170528-4-devarsht@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Devarsh Thakkar authored
commit 1a5010ea upstream. This adds common1 register space for AM65x SoC which is using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml Fixes: fc539b90 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Reviewed-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20240216062426.4170528-3-devarsht@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Devarsh Thakkar authored
commit b59dcca9 upstream. TI keystone display subsystem present in AM65, AM62 and AM62A SoC support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1]. The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region. This adds binding for "common1" register region too as supported by the hardware. [1]: AM62x TRM: https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) AM65x TRM: https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) AM62A TRM: https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9 Display Subsystem Registers) Fixes: 2d8730f1 ("dt-bindings: display: ti,am65x-dss: Add dt-schema yaml binding") Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Reviewed-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Acked-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240216062426.4170528-2-devarsht@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit 5f0e6ce3 upstream. Add missing bootph-all property for AM62p MMC0 and AM64x MMC0 nodes. Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-10-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit 0ae3113a upstream. Move bus-width property to *main.dtsi, above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if the bus-width property is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing bus-width for MMC2 in k3-am62-main. Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-9-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit 2812d23a upstream. Move ti,clkbuf-sel property above the OTAP/ITAP delay values. While there is no error with where it is currently at, it is easier to read the MMC node if ti,clkbuf-sel is located above the OTAP/ITAP delay values consistently across MMC nodes. Add missing ti,clkbuf-sel for MMC0 in k3-am64-main. Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-8-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit eea929f0 upstream. Remove DLL properties which are not applicable for soft PHYs since these PHYs do not have a DLL to enable. Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Verdin AM62 Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-7-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit 37f28165 upstream. Add OTAP/ITAP values to enable HS400 timing for MMC0 and SDR104 timing for MMC1/MMC2. Remove no-1-8-v property to enable the highest speed mode possible. Update MMC OTAP/ITAP values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2. [0] https://www.ti.com/lit/ds/symlink/am62p.pdf Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-6-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit 379c7752 upstream. Update MMC0/MMC1 OTAP/ITAP values according to the datasheet [0], refer to Table 7-68 for MMC0 and Table 7-77 for MMC1. [0] https://www.ti.com/lit/ds/symlink/am6442.pdf Fixes: 8abae938 ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-5-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Nitin Yadav authored
commit e041ec6e upstream. Add support for 32GB eMMC card on AM62A7 SK. Includes adding mmc0 pins settings. Add mmc0 alias for sdhci0 in k3-am62a7-sk.dts. Signed-off-by:
Nitin Yadav <n-yadav@ti.com> Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-4-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Judith Mendez authored
commit feb5d68c upstream. Add sdhci2 DT node in k3-am62a-main for mmc2. Add otap/itap values according to the datasheet[0], Refer to Table 7-97. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-3-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Nitin Yadav authored
commit d3ae4e8d upstream. Add sdhci0 DT node in k3-am62a-main for eMMC support. Add otap/itap values according to the datasheet[0], refer to Table 7-79. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by:
Nitin Yadav <n-yadav@ti.com> Signed-off-by:
Judith Mendez <jm@ti.com> Tested-by:
Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240213235701.2438513-2-jm@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Bhavya Kapoor authored
commit d29a6cf9 upstream. Only Tx and Rx Signal lines for wkup_uart0 are brought out on the J784S4 EVM from SoC, but CTS and RTS signal lines are not brought on the EVM. Thus, remove pinmux for CTS and RTS signal lines for wkup_uart0 in J784S4. Fixes: 6fa5d37a ("arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts") Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-5-b-kapoor@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Bhavya Kapoor authored
commit 28e5b74d upstream. Only Tx and Rx Signal lines for wkup_uart0 are brought out on the Common Proc Board through SoM, but CTS and RTS signal lines are not brought on the board. Thus, remove pinmux for CTS and RTS signal lines for wkup_uart0 in J721S2. Fixes: f5e9ee0b ("arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux") Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-4-b-kapoor@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Bhavya Kapoor authored
commit 0fa8b0e2 upstream. Clock-frequency property is already present in mcu_uart0 node of the k3-j7200-mcu-wakeup.dtsi file. Thus, remove redundant clock-frequency property from mcu_uart0 node. Fixes: 3709ea7f ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-3-b-kapoor@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Bhavya Kapoor authored
commit 566feddd upstream. WKUP_PADCONFIG registers for wkup_uart0 and mcu_uart0 lies under wkup_pmx2 for J7200. Thus, modify pinmux for both of them. Fixes: 3709ea7f ("arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux") Signed-off-by:
Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20240214105846.1096733-2-b-kapoor@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit f767eb91 upstream. RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-10-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit 2ba8f21a upstream. J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-9-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit 6aac9199 upstream. J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-8-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit 491821ce upstream. J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-7-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit f87c8894 upstream. J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-6-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit 12d82b15 upstream. CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-5-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit 5dcc1aaf upstream. CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-4-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit fa646b70 upstream. CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-3-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Vaishnav Achath authored
commit f00c6ead upstream. CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20240215085518.552692-2-vaishnav.a@ti.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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Li Hua Qian authored
commit 14a65ea5 upstream. This patch adds a reserved memory for the TI AM65X platform watchdog to reserve the specific info, triggering the watchdog reset in last boot, to know if the board reboot is due to a watchdog reset. Signed-off-by:
Li Hua Qian <huaqian.li@siemens.com> Link: https://lore.kernel.org/r/20240117060654.109424-1-huaqian.li@siemens.com Signed-off-by:
Manorit Chawdhry <m-chawdhry@ti.com>
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