Signed-off-by: Tom Rini <trini@konsulko.com>

clock changes for u-boot/master

This has some clock fixes which should go in before the release. It's a bit
late in the cycle, but most of these have tests to go along with them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Fix unused variable error produced by building tests

Fixes: d3061824 (test: dm: clk_ccf: test ccf_clk_ops)
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216-b4-fix_build-v1-1-b8e79c94744f@outlook.com

Assign ccf_clk_ops to .ops of clk_ccf driver so that it can act as an
clk provider. Also add "#clock-cells=<1>" to its device tree node.

Add "i2c_root" to clk_test in the device tree and driver for testing.

Get "i2c_root" clock in CCF unit tests and add tests for it.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231111-enable_count-v3-2-08a821892fa9@outlook.com

Add a simple test case which sets clock rate to its current value.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-3-ivprusov@salutedevices.com

It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it will cause NULL dereference during
clk_set_rate().

This patch adds rate_ops->set_rate check tp clk_composite_set_rate().

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231205232334.2931-2-ivprusov@salutedevices.com

assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.

This fixes the incorrect enable_count issue as described in [1].

[1]: https://lore.kernel.org/all/SEZPR06MB695927A6DEEEF8489A06897396A7A@SEZPR06MB6959.apcprd06.prod.outlook.com/



Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231111-enable_count-v2-2-20e3728600b5@outlook.com

For some gate clocks and fixed clocks without a parent, calling
clk_register will print an useless error message indicating that parent
is missing. Fix that by gaurding log_xxx() with an if-statement.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Suggested-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20230807-clk-fix-v2-1-0b688e21fb4e@outlook.com

- Fix for i.MX8M Plus eDM SBC DDR timings with inline ECC
- Switch to FPWM mode on Data Modul i.MX8M Plus eDM SBC so that DRAM
  EDAC detects more correctable errors
- Fix for imx8mp-venice board DDR initialization

The imx8mp venice boards can support 2000Mhz DRAM.
Update the DRAM config to support this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

The DRAM configuration for the 1GB and 4GB imx8mp venice boards had a
bus mapping issue (channel A and B swapped) which creates an invalid
deskewing configuration during training causing the DRAM to not be able
to run at its full bus speed.

Update the various config structures to resolve this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Remove lpddr4_timing_imx8mm_512mb.c mistakenly committed

Fixes: a1c71104 "(board: gateworks: venice: add imx8mm-gw7903 support)"
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.

Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.

Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Enable CAAM in U-Boot to make crypto available early in the boot process.

This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Enable CAAM in U-Boot to make crypto available early in the boot process.

This has a side-effect that in case an older kernel version contains a
broken CAAM initialization timeout code, initialization in bootloader
will help that old kernel version function correctly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Inhibit DTC warning in imx8mp-dhcom-pdk3-overlay-rev100.dts:
"
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (reg_format): /fragment@0/__overlay__:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #address-cells value
arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtbo: Warning (avoid_default_addr_size): /fragment@0/__overlay__: Relying on default #size-cells value
"

The DTO overwrites the 'reg' property of an ethernet PHY and is only
used on specific combination of old prototype SoM and old prototype
PDK3 carrier board, which had incorrectly placed pull resistor, which
made the PHY change its MDIO address in that specific combination and
which is already fixed on production hardware.

The DTO is implemented in this simple manner because if it contained a
full MDIO bus node reference to define #address-cells and #size-cells,
it would also require a full new copy of the PHY node, i.e.
ethernet-phy@5 { ... reg = <5>; ... }, to avoid DTC warnings about
mismatch between node unit and reg value. The node unit in SoM DT is
ethernet-phy@7 { ... }; .

This simpler approach avoids unnecessary duplication without adverse
side effects.

Reported-by: Fabio Estevam <festevam@denx.de>
Reported-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

- A few MAINTAINERS updates and Kconfig wording fixes

Remove Akash Gajjar <akash@openedev.com> from
MAINTAINERS as email is bouncing.

Signed-off-by: Shantur Rathore <i@shantur.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Remove Bharat Gooty as a maintainer as his mail is
bouncing.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>

Fixes a filepath in MAINTAINERS file that wasn't updated when
renaming the files to match the new SoC name.

Fixes: a4bd5e41 ('arm: apple: Change SoC name from "m1" into "apple"')
Signed-off-by: Moritz Fischer <moritzf@google.com>

Both FS_LOADER and SPL_FS_LOADER have the same menu prompt.
To avoid confusion, make prompt for SPL_FS_LOADER different.

Signed-off-by: Alexander Gendin <agendin@matrox.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

The correct symbol to enable to have SMBIOS populate fields based on the
device tree is SYSINFO_SMBIOS and not SMBIOS_SYSINFO.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

- Fix emmc detection on colibri_imx7
- Fix DDR configuration on tqma6 to improve Ethernet performance
- Fix aliases and chosen nodes indentation on imx7s-warp
- Convert pico-imx6ul to DM_SERIAL
- Convert pico-pi-imx7d to watchdog driver model to fix 'reset' command
- Select CONFIG_NET_RANDOM_ETHADDR on imx8mp_evk to fix networking on
  older boards
- Add USBH_EN gpio hog to fix USB host interface not working on some
  Apalis Toradex carrier boards with Apalis iMX8 SoM
- Add PCI fixup for GW73xx-F+
- Fix broken EEPROM read on imx8mn-var-som

Later versions of Colibri iMX7D V1.1B modules use a "new" SoC fusing. The
difference lies in whether we enable the boot ROM to use the eMMC reset
signal. Depending on the SoC fuse, the boot ROM configures this pin as a
GPIO output to drive the reset signal. Our eMMC vs NAND detection
currently only sets that signal to a GPIO without explicitly setting any
direction. Previously, by default, it was set as an input. As the boot ROM
now configures it as an output, we receive a value of zero instead of one,
indicating the absence of the pull-up on eMMC modules.

To fix this, set the SION bit, allowing the reading back of the value
even if it is configured as an output by the boot ROM. It's important to
note that with the new SoC fusing, we now read back what the boot ROM
drives rather than the real value caused by the pull-up resistor. However,
if it were ever driven low, the eMMC would permanently be reset.

In addition, remove hard-coded variant in the eMMC build case as since the
commit 0c39564d ("toradex: colibri_imx7: Enable nand/emmc detection
and set boot variant") will anyways always get overridden by the detection
routing in board code.

Fixes: 0c39564d ("toradex: colibri_imx7: Enable nand/emmc detection and set boot variant")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>

Initially investigating a Linux network issue causing a lot of drop and
poor network performances on a custom system based on a TQMA6A module
(based on an iMX6Q), [1st link below].

I eventually correlated my observations with a contention at the NIC
level when in concurrency with the graphics pipeline. Troubleshooting
this in the kernel lead to disabling DMA bursts accesses made by the IPU
in order to avoid triggering the QoS at the interconnect level, reducing
from 50 to 10% the drop rate on eth0, [2nd link below]. The solution
worked on my setup but not on others, which still suffered from
abnormally high drop rates even with this "fix".

After looking a while into TQ Systems BSP I figured out a number of
differences in recent U-Boot out-of-tree patches they had in their
repository [3rd link]. Parsing the differences one after the other lead
me to this final solution.

The reset pad of the DDR controller was apparently misconfigured, Bit
18-19 picturing the "DDR select field". The current value b11 is
reserved. The only defined value as of version 6 of the iMX6Q manual was
b00 "DDR3 and LPDDR2 mode". In practice no register difference has been
spotted after changing this configuration but all issues tracked thus
far just vanished. All previous fixes have been proven irrelevant. Just
clearing this field solved all our network issues and the drop rate as
measured by iperf3 felt back to 0%.

Link: https://lore.kernel.org/netdev/20231012193410.3d1812cf@xps-13/
Link: https://lists.freedesktop.org/archives/dri-devel/2023-October/428251.html
Link: https://github.com/tq-systems/u-boot-tqmaxx/commit/15eb6abbefbf6916c28467b85485911dad3da6bc


Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

The aliases and chosen nodes are currently indented using spaces.

Fix them to use the standard tab indentation.

Signed-off-by: Fabio Estevam <festevam@denx.de>

The conversion to DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>

Commit 68dcbdd5 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset

Signed-off-by: Fabio Estevam <festevam@denx.de>

On an early revision of the imx8mp-evk that I have access to,
the MAC addresses fuses are not programmed, causing failure to bring
the Ethernet interfaces.

Fix this problema by selecting CONFIG_NET_RANDOM_ETHADDR so that
random MAC addresses are assigned and the Ethernet ports become
functional out of the box.

Signed-off-by: Fabio Estevam <festevam@denx.de>

USB host interface is not working on some Apalis Toradex carrier
boards with Apalis iMX8 SoM. This is due to USBH_EN pin, which
powers USB peripherals, having a strong pull-down on some boards,
and a weak pull-down on the others. This USBH_EN pin is left
unconfigured, which means it is in its default state at cold boot:
input with a strong pull-up. As a result, carrier boards with a
weak pull-down have this signal high enough to trigger power
delivery to USB peripherals, and opposite - boards with strong
pull-down on USBH_EN have this signal below the threshold needed
to trigger USB power delivery.
This change configures the USBH_EN pin as gpio hog, fixing this
issue for all Apalis carrier boards regardless of pull-down
resistor value.

Also, update apalis-imx8_defconfig via savedefconfig.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

GW73xx-F board revision switched back to the original PCIe switch due to
part availability.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

On branch WIP/17Oct2023, the EEPROM can no longer be read:

    U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400)
    CPU:   Freescale i.MX8MNano Quad rev1.0 at 1200 MHz
    Reset cause: POR
    Model: Variscite VAR-SOM-MX8MN Symphony evaluation board
    var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19
    initcall failed at call 000000004022207c (err=-19)

Convert EEPROM-related properties to bootph-all so that the EEPROM can
also be read outside of SPL.

Fixes: 9e644284 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

Recently pylint has started to complain about:
No name 'fs_helper' in module 'tests' (no-name-in-module)

Due to:
from tests import fs_helper

However, we have:
test/py/tests/fs_helper.py

And since we do not want to add a dummy test/py/tests/__init__.py to
silence this warning we instead just disable it as needed.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

- StarFive: Add StarFive watchdog driver
- VisionFive2: Support device tree overlay for VisionFive2 board
- Andes: Fix PLIC-SW setting
- RISC-V: Fix NVMe support by implying NVME_PCI for QEMU
- RISC-V: Fix binman for 64 bit format load address

To quote the author:

Currently bootmeth_efi crashes while doing a network (dhcp) boot.
This patch series fixes issues and both network and disk boot works.

# Do not modify or remove the line above.
# Everything below it will be ignored.
#
# Please enter a commit message to explain why this merge is necessary,
# especially if it merges an updated upstream into a topic branch.
#
# An empty message aborts the commit.

bootmeth_efi doesn't allocate any buffer to load efi in any case.
enable static buffer flag for all cases.

Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Shantur Rathore <i@shantur.com>

While booting with efi, if fdt isn't available externally,
just use the built-in one.

Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Shantur Rathore <i@shantur.com>