diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index ccf79c35d90d4007c3ebf85f1fe9087e802a5bae..08944e83f49784c6eace28485f5188cbde645125 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -128,17 +128,17 @@ new_project \
# // Download required cores
#
-download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_OSC:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_CCC:*} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
-download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:DirectCore:CORERESET_PF:*} -location {www.microchip-ip.com/repositories/DirectCore}
+download_core -vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
-download_core -vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_DRI:1.1.104} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_NGMUX:1.0.101} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_CLK_DIV:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_DRI:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_NGMUX:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_PCIE:*} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_TX_PLL:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
@@ -148,9 +148,9 @@ download_core -vlnv {Actel:Simulation:RESET_GEN:1.0.1} -location {www.microchip-
download_core -vlnv {Actel:DirectCore:corepwm:4.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREI2C:7.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
-download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SgCore:PF_IO:2.0.104} -location {www.microchip-ip.com/repositories/SgCore}
-download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SgCore:PF_IO:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -location {www.microchip-ip.com/repositories/SgCore}
#
# // Generate base design
diff --git a/script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl b/script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl
index 6f6f7abbb777b253479ee6d406425069ee162b65..ead43b8ddf0d05651bc83fbbb1af2bc1f91ea366 100644
--- a/script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/CLK_DIV.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component CLK_DIV
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:1.0.103} -component_name {CLK_DIV} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CLK_DIV:*} -component_name {CLK_DIV} -params {\
"DIVIDER:2" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
diff --git a/script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl b/script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl
index 689e1fcae6a56a306d092669b86aa3fe5d1ce483..f39d61af35efe1df7561b5a76f19bf756ef37d97 100644
--- a/script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/GLITCHLESS_MUX.tcl
@@ -2,6 +2,6 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component GLITCHLESS_MUX
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_NGMUX:1.0.101} -component_name {GLITCHLESS_MUX} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_NGMUX:*} -component_name {GLITCHLESS_MUX} -params {\
"ENABLE_NON_TOGGLING_CLK_SWITCH_SUPPORT:false" }
# Exporting Component Description of GLITCHLESS_MUX to TCL done
diff --git a/script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl b/script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl
index ee1c8d8437972eab1032ec8d2613bef313d731d2..8684541de7bac0ee121421d2fc468b3761a5eee2 100644
--- a/script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/INIT_MONITOR.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component INIT_MONITOR
-create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:1.0.304} -component_name {INIT_MONITOR} -params {\
+create_and_configure_core -core_vlnv {Microsemi:SgCore:PFSOC_INIT_MONITOR:*} -component_name {INIT_MONITOR} -params {\
"BANK_0_CALIB_STATUS_ENABLED:false" \
"BANK_0_CALIB_STATUS_SIMULATION_DELAY:1" \
"BANK_0_RECALIBRATION_ENABLED:false" \
diff --git a/script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl b/script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl
index 832238af5c17f59e2b2f54dda34ceb4922a47a34..4e616813247d46323fdcbccb1559018d4a7e1183 100644
--- a/script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/OSCILLATOR_160MHz.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component OSCILLATOR_160MHz
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:1.0.102} -component_name {OSCILLATOR_160MHz} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_OSC:*} -component_name {OSCILLATOR_160MHz} -params {\
"RCOSC_2MHZ_CLK_DIV_EN:false" \
"RCOSC_2MHZ_GL_EN:false" \
"RCOSC_2MHZ_NGMUX_EN:false" \
diff --git a/script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl b/script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl
index d8d937fa7e490fd803ea499f05ea1fa7048a44f0..5f230aaeda43a50850d6bbdc68379df7797e72b6 100644
--- a/script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/PCIE_REF_CLK.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component PCIE_REF_CLK
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PCIE_REF_CLK} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PCIE_REF_CLK} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl b/script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl
index 51320d22c076c601df06a623524e32f9c393b4d9..f464694955ddc2407f085e184d0ce9ea3e0081e5 100644
--- a/script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl
+++ b/script_support/components/CLOCKS_AND_RESETS/TRANSMIT_PLL.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T_ES-FCVG484E
# Create and Configure the core component TRANSMIT_PLL
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {TRANSMIT_PLL} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {TRANSMIT_PLL} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_TX_PLL_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_TX_PLL_C0.tcl
index 49a07da5497f5939d0a1a03dc35c47229d848a58..d4fc66fb291b39bdf409e0ae843615db3dfc4356 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_TX_PLL_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_TX_PLL_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_TX_PLL_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_C0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
index 8e15847ca749470b9f5aba9c5778bdba9327969f..a747ec81b4f4703cacbf40035750151063a7cc52 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_REF_CLK_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
index c4e5dec04541294c821ace45859f296e784aadbc..c6a23b9f703efb211edfa25d6940f2b99ac7e395 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
index d13849b11c0207d5003568859480bc98aeae07b0..71025d8d90ecd943216aafe39490b91ce194c088 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_TX_PLL_0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
index efa10b031f536d45ba96950ef37298d62a198287..1d1081ec160cd8363161ebfe5f701fbe0100bdb1 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_XCVR_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
index ea07e4507db8fbbaefb9664e73236980cad6b8b0..94d64dcd93d485c9bbf6390c658c51370dde6bad 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_XCVR_REF_CLK_0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
index e8dc11d935415b2de275f5d20811d9e3493a7727..55f816c6b1239c3e90a999a4c2dd90033ae9c06e 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
# Create and Configure the core component PF_XCVR_REF_CLK_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
index c4e5dec04541294c821ace45859f296e784aadbc..c6a23b9f703efb211edfa25d6940f2b99ac7e395 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
index d13849b11c0207d5003568859480bc98aeae07b0..71025d8d90ecd943216aafe39490b91ce194c088 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_TX_PLL_0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
index efa10b031f536d45ba96950ef37298d62a198287..1d1081ec160cd8363161ebfe5f701fbe0100bdb1 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_XCVR_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
index ea07e4507db8fbbaefb9664e73236980cad6b8b0..94d64dcd93d485c9bbf6390c658c51370dde6bad 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_XCVR_REF_CLK_0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
index e8dc11d935415b2de275f5d20811d9e3493a7727..55f816c6b1239c3e90a999a4c2dd90033ae9c06e 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/PF_XCVR_REF_CLK_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
# Create and Configure the core component PF_XCVR_REF_CLK_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
index c4e5dec04541294c821ace45859f296e784aadbc..c6a23b9f703efb211edfa25d6940f2b99ac7e395 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CLK_DIV_C0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:1.0.103 -component_name {PF_CLK_DIV_C0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
"DIVIDER:4" \
"ENABLE_BIT_SLIP:false" \
"ENABLE_SRESET:false" }
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
index d13849b11c0207d5003568859480bc98aeae07b0..71025d8d90ecd943216aafe39490b91ce194c088 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_TX_PLL_0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
index efa10b031f536d45ba96950ef37298d62a198287..1d1081ec160cd8363161ebfe5f701fbe0100bdb1 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-1FCVG484I
# Create and Configure the core component PF_XCVR_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_0} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
index ea07e4507db8fbbaefb9664e73236980cad6b8b0..94d64dcd93d485c9bbf6390c658c51370dde6bad 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_XCVR_REF_CLK_0
-create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:1.0.103 -component_name {PF_XCVR_REF_CLK_0} -params {\
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_TX_PLL_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_TX_PLL_C0.tcl
index 49a07da5497f5939d0a1a03dc35c47229d848a58..d4fc66fb291b39bdf409e0ae843615db3dfc4356 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_TX_PLL_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_TX_PLL_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_TX_PLL_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_C0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C0.tcl
index e133a7a92019a097db4b405c45ccc7e41a372aef..b9f085aa21f702ca2bd52729314b2d54039d8d1f 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_ERM_C0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_ERM_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_ERM_C0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C1.tcl
index f882b2ce7781d8f5b73ac5a0ec7c69fd588d7221..46dd25683e285af499a511563458786eef76bff4 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C1.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_ERM_C1.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_ERM_C1
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_ERM_C1} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_ERM_C1} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_REF_CLK_C0.tcl
index 8e15847ca749470b9f5aba9c5778bdba9327969f..a747ec81b4f4703cacbf40035750151063a7cc52 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_REF_CLK_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/PF_XCVR_REF_CLK_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_REF_CLK_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C0.tcl
index 47819e1f1330f088c7db4223a4a3581e274a6908..9ece9047fa7ec935fd9406f28512ea070c839543 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C0} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:1" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C1.tcl
index d8ce8efcdef1c0a33310959ea5a9f5d2f8dfa5e7..5180696052143f01fe023b3b282d987b598c6bf9 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C1.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C1.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C1
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C1} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C1} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:2" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C2.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C2.tcl
index f9293144330898a3ec328098763b2d2e64d278d5..4927590c7a3e1f3e8a0153e030990bd49c1c745f 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C2.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C2.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C2
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C2} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C2} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:1" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C3.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C3.tcl
index 378242146600d745ff1797aeddd154f41ff00fb3..15e36db3c77b10451bf60ed841d0bff2a1f41886 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C3.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C3.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C3
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C3} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C3} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:2" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C4.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C4.tcl
index 153391eadbea624191643625f34662ec6187309c..41b4c41da9d594e2ebaadb3c2ef597af6046c140 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C4.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C4.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C4
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C4} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C4} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:1" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C5.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C5.tcl
index f7d9534db9a9a708940be6c0e6c4a7e0e40ec8c8..27519cdca458e70b31ddac3b55c77cf1f56416c9 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C5.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_IO_C5.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_IO_C5
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:2.0.104} -component_name {PF_IO_C5} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_IO:*} -component_name {PF_IO_C5} -params {\
"DIFFERENTIAL:true" \
"DIRECTION:2" \
"DYN_DELAY_LINE_EN:false" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_TX_PLL_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_TX_PLL_C0.tcl
index 49a07da5497f5939d0a1a03dc35c47229d848a58..d4fc66fb291b39bdf409e0ae843615db3dfc4356 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_TX_PLL_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_TX_PLL_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_TX_PLL_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_C0} -params {\
"CORE:PF_TX_PLL" \
"INIT:0x0" \
"TxPLL_AUX_LOW_SEL:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C0.tcl
index e133a7a92019a097db4b405c45ccc7e41a372aef..b9f085aa21f702ca2bd52729314b2d54039d8d1f 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_ERM_C0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_ERM_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_ERM_C0} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C1.tcl
index f882b2ce7781d8f5b73ac5a0ec7c69fd588d7221..46dd25683e285af499a511563458786eef76bff4 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C1.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_ERM_C1.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_ERM_C1
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -component_name {PF_XCVR_ERM_C1} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_ERM_C1} -params {\
"EXPOSE_ALL_DEBUG_PORTS:false" \
"EXPOSE_FWF_EN_PORTS:false" \
"SHOW_UNIVERSAL_SOLN_PORTS:true" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_REF_CLK_C0.tcl
index 8e15847ca749470b9f5aba9c5778bdba9327969f..a747ec81b4f4703cacbf40035750151063a7cc52 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_REF_CLK_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/PF_XCVR_REF_CLK_C0.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component PF_XCVR_REF_CLK_C0
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
"ENABLE_FAB_CLK_0:false" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
diff --git a/script_support/components/M2/DEFAULT/RECONFIGURATION_INTERFACE.tcl b/script_support/components/M2/DEFAULT/RECONFIGURATION_INTERFACE.tcl
index 0040ec654a113748e4fd5d053766a4d723fca6ae..751725a977c8564d7c55b240f5f2052220bc1c3f 100644
--- a/script_support/components/M2/DEFAULT/RECONFIGURATION_INTERFACE.tcl
+++ b/script_support/components/M2/DEFAULT/RECONFIGURATION_INTERFACE.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484_EVALE
# Create and Configure the core component RECONFIGURATION_INTERFACE
-create_and_configure_core -core_vlnv {Actel:SgCore:PF_DRI:1.1.104} -component_name {RECONFIGURATION_INTERFACE} -params {\
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_DRI:*} -component_name {RECONFIGURATION_INTERFACE} -params {\
"CRYPTO:false" \
"DLL0_NE:false" \
"DLL0_NW:false" \
diff --git a/script_support/components/MIPI_CSI/IO_STUB/MIPI_CSI2_RX_IOD.tcl b/script_support/components/MIPI_CSI/IO_STUB/MIPI_CSI2_RX_IOD.tcl
index 793e9dce4fdfb77ab9dccea61c27ea5e1a5ba1ab..830c88d0bcb681e3d279d75d9bedf99a503621d9 100644
--- a/script_support/components/MIPI_CSI/IO_STUB/MIPI_CSI2_RX_IOD.tcl
+++ b/script_support/components/MIPI_CSI/IO_STUB/MIPI_CSI2_RX_IOD.tcl
@@ -2,7 +2,7 @@
# Family: PolarFireSoC
# Part Number: MPFS250T-FCVG484E
# Create and Configure the core component MIPI_CSI2_RX_IOD
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.109} -component_name {MIPI_CSI2_RX_IOD} -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:*} -component_name {MIPI_CSI2_RX_IOD} -params {\
"CLOCK_DELAY_VALUE:0" \
"DATA_RATE:250" \
"DATA_RATIO:2" \