From 02e3847b22e7783809e5900656eebf3d02cbabd5 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 5 Feb 2023 10:03:39 +0000
Subject: [PATCH] Documentation: Add skeleton documentation for gateware
overview and GPIO.
---
.../BeagleVFire-ImmutableConnections.svg | 324 ++++++++++
doc/diagrams/BeagleVFire-overview.svg | 578 ++++++++++++++++++
doc/gateware_design_overview.md | 9 +
doc/mss_gpio.md | 41 ++
doc/user_leds.md | 20 +
5 files changed, 972 insertions(+)
create mode 100644 doc/diagrams/BeagleVFire-ImmutableConnections.svg
create mode 100644 doc/diagrams/BeagleVFire-overview.svg
create mode 100644 doc/gateware_design_overview.md
create mode 100644 doc/mss_gpio.md
create mode 100644 doc/user_leds.md
diff --git a/doc/diagrams/BeagleVFire-ImmutableConnections.svg b/doc/diagrams/BeagleVFire-ImmutableConnections.svg
new file mode 100644
index 0000000..3843cc9
--- /dev/null
+++ b/doc/diagrams/BeagleVFire-ImmutableConnections.svg
@@ -0,0 +1,324 @@
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new file mode 100644
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <g id="shape27-112" v:mID="27" v:groupContext="shape" transform="translate(516.756,-475.37)">
+ <title>Rectangle.27</title>
+ <desc>SD-Card</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ <text x="12.01" y="584.1" class="st10" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>SD-Card</text> </g>
+ <g id="shape28-115" v:mID="28" v:groupContext="shape" transform="translate(261.638,-92.6929)">
+ <title>Rectangle.28</title>
+ <desc>M.2 Key E Connector</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ <text x="8.22" y="578.1" class="st10" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>M.2 Key E<v:newlineChar/><tspan
+ x="7.13" dy="1.2em" class="st6">Connector</tspan></text> </g>
+ <g id="shape29-119" v:mID="29" v:groupContext="shape" transform="translate(360.85,-92.6929)">
+ <title>Rectangle.29</title>
+ <desc>Cape Connectors</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ x="5.18" dy="1.2em" class="st6">Connectors</tspan></text> </g>
+ <g id="shape30-123" v:mID="30" v:groupContext="shape" transform="translate(530.929,-206.079)">
+ <title>Rectangle.30</title>
+ <desc>Transceiver lanes 1, 2, 3</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <g id="shape31-127" v:mID="31" v:groupContext="shape" transform="translate(261.638,-206.079)">
+ <title>Rectangle.31</title>
+ <desc>Transceiver lane 0</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ <g id="shape32-131" v:mID="32" v:groupContext="shape" transform="translate(360.85,-163.559)">
+ <title>Rectangle.32</title>
+ <desc>I/Os</desc>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ <g id="shape34-134" v:mID="34" v:groupContext="shape" transform="translate(204.945,-163.559)">
+ <title>Rectangle.34</title>
+ <desc>I/Os</desc>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <text x="19.89" y="584.1" class="st10" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>I/Os</text> </g>
+ <g id="shape35-137" v:mID="35" v:groupContext="shape" transform="translate(587.622,-163.559)">
+ <title>Rectangle.35</title>
+ <desc>High-Speed I/Os</desc>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <g id="shape36-141" v:mID="36" v:groupContext="shape" v:layerMember="0" transform="translate(233.291,-163.559)">
+ <title>Dynamic connector.36</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape37-146" v:mID="37" v:groupContext="shape" v:layerMember="0" transform="translate(382.11,-163.559)">
+ <title>Dynamic connector.37</title>
+ <v:userDefs>
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+ </g>
+ <g id="shape38-151" v:mID="38" v:groupContext="shape" v:layerMember="0" transform="translate(396.283,-262.772)">
+ <title>Dynamic connector.38</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape39-156" v:mID="39" v:groupContext="shape" v:layerMember="0" transform="translate(282.898,-262.772)">
+ <title>Dynamic connector.39</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ </g>
+ <g id="shape40-161" v:mID="40" v:groupContext="shape" v:layerMember="0" transform="translate(552.189,-262.772)">
+ <title>Dynamic connector.40</title>
+ <v:userDefs>
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+ </v:userDefs>
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+ </g>
+ <g id="shape41-166" v:mID="41" v:groupContext="shape" v:layerMember="0" transform="translate(623.055,-262.772)">
+ <title>Dynamic connector.41</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape42-171" v:mID="42" v:groupContext="shape" v:layerMember="0" transform="translate(297.071,-206.079)">
+ <title>Dynamic connector.42</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape43-176" v:mID="43" v:groupContext="shape" v:layerMember="0" transform="translate(559.276,-206.079)">
+ <title>Dynamic connector.43</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape44-181" v:mID="44" v:groupContext="shape" v:layerMember="0" transform="translate(615.969,-163.559)">
+ <title>Dynamic connector.44</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape45-186" v:mID="45" v:groupContext="shape" v:layerMember="0" transform="translate(545.102,-475.37)">
+ <title>Dynamic connector.45</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <path d="M0 595.28 L0 615.94 L-120.47 615.94 L-120.47 659.95" class="st11"/>
+ </g>
+ <g id="shape48-191" v:mID="48" v:groupContext="shape" transform="translate(389.197,-517.89)">
+ <title>Rectangle.48</title>
+ <desc>ADC</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ <text x="19.71" y="584.1" class="st10" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>ADC</text> </g>
+ <g id="shape49-194" v:mID="49" v:groupContext="shape" transform="translate(559.276,-517.89)">
+ <title>Rectangle.49</title>
+ <desc>USB</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ <text x="20.12" y="584.1" class="st10" v:langID="6153"><v:paragraph v:horizAlign="1"/><v:tabList/>USB</text> </g>
+ <g id="shape51-197" v:mID="51" v:groupContext="shape" transform="translate(460.063,-92.6929)">
+ <title>Rectangle.51</title>
+ <desc>MIPI-CSI Connector</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ x="7.13" dy="1.2em" class="st6">Connector</tspan></text> </g>
+ <g id="shape52-201" v:mID="52" v:groupContext="shape" transform="translate(445.89,-262.772)">
+ <title>Rectangle.52</title>
+ <desc>MIPI CSI FPGA Block</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ <g id="shape53-205" v:mID="53" v:groupContext="shape" transform="translate(460.063,-163.559)">
+ <title>Rectangle.53</title>
+ <desc>High-Speed I/Os</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)" v:tabSpace="42.5197"/>
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+ <g id="shape54-209" v:mID="54" v:groupContext="shape" v:layerMember="0" transform="translate(481.323,-163.559)">
+ <title>Dynamic connector.54</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape55-214" v:mID="55" v:groupContext="shape" v:layerMember="0" transform="translate(481.323,-262.772)">
+ <title>Dynamic connector.55</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape56-219" v:mID="56" v:groupContext="shape" v:layerMember="0" transform="translate(417.543,-348.402)">
+ <title>Dynamic connector.56</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape57-224" v:mID="57" v:groupContext="shape" v:layerMember="0" transform="translate(417.543,-517.89)">
+ <title>Dynamic connector.57</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape58-229" v:mID="58" v:groupContext="shape" v:layerMember="0" transform="translate(587.622,-517.89)">
+ <title>Dynamic connector.58</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape61-234" v:mID="61" v:groupContext="shape" transform="translate(304.157,-517.89)">
+ <title>Rectangle.61</title>
+ <desc>Debug UART</desc>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ x="17.09" dy="1.2em" class="st6">UART</tspan></text> </g>
+ <g id="shape62-238" v:mID="62" v:groupContext="shape" v:layerMember="0" transform="translate(332.504,-517.89)">
+ <title>Dynamic connector.62</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape63-243" v:mID="63" v:groupContext="shape" v:layerMember="0" transform="translate(360.85,-376.748)">
+ <title>Dynamic connector.63</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ <g id="shape64-249" v:mID="64" v:groupContext="shape" v:layerMember="0" transform="translate(445.89,-376.748)">
+ <title>Dynamic connector.64</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
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+ </g>
+ </g>
+</svg>
diff --git a/doc/gateware_design_overview.md b/doc/gateware_design_overview.md
new file mode 100644
index 0000000..4449f78
--- /dev/null
+++ b/doc/gateware_design_overview.md
@@ -0,0 +1,9 @@
+# Gateware Design Overview
+
+## BeagleV-Fire Overview
+
+
+
+Part of the gateware design is not flexible, mainly due to physical connections of dedicated PolarFire SoC I/Os. These parts of the design are concentrated within the base core gateware design [TODO: nomenclature].
+
+
diff --git a/doc/mss_gpio.md b/doc/mss_gpio.md
new file mode 100644
index 0000000..d7d1fc4
--- /dev/null
+++ b/doc/mss_gpio.md
@@ -0,0 +1,41 @@
+# Microprocessor Subsystem GPIO Controllers Pin Assignment
+The Microprocess Subsystem's (MSS) includes 3 GPIO controllers.
+
+
+| Name | Base Address | Linux Name |
+|--------|--------------|------------|
+| GPIO_0 | 0x20120000 | gpio0 |
+| GPIO_1 | 0x20121000 | gpio1 |
+| GPIO_2 | 0x20122000 | gpio2 |
+
+
+## GPIO_0 pin assignment
+1.8V I/Os connected to I/O bank4. These GPIOs share pins with other MSS functions. As a result only a limited number of GPIOs from this controller are usable.
+
+| GPIO # | Type | Function |
+|--------|-------|----------------|
+| 0-11 | n/a | Unused |
+| 12 | out | SD_CARD_CS |
+| 13 | in | User button |
+
+
+## GPIO_1 pin assignment
+3.3V I/Os connected to I/O bank2. These GPIOs share pins with other MSS functions. As a result only a limited number of GPIOs from this controller are usable.
+
+| GPIO # | Type | Function |
+|--------|-------|----------------|
+| 0-19 | n/a | Unused |
+| 20 | in | ADC_IRQn |
+| 21-22 | n/a | Unused |
+| 23 | in | USB_OCn |
+
+## GPIO_2 pin assignment
+The MSS GPIO_2 block's inputs and output are routed through the FPGA fabric to the PolarFire SoC's pins. The function of these GPIOs can be customized by the content of the FPGA. However, there is GPIOs expected to remain constant across designs.
+
+| GPIO # | Type | Function |
+|--------|-------|----------------|
+| 0-26 | inout | Routed to FPGA |
+| 27-29 | n/a | Non-assigned |
+| 30 | out | VIO_ENABLE |
+| 31 | in | SD_DET |
+
diff --git a/doc/user_leds.md b/doc/user_leds.md
new file mode 100644
index 0000000..7e13407
--- /dev/null
+++ b/doc/user_leds.md
@@ -0,0 +1,20 @@
+# User LEDs
+The user LEDs are controlled from an FPGA fabric GPIO controller included within the RISC-V Processor Subsystem. GPIOs are connected to their respective pins through a User LED Pads FPGA logic block. Keeping the USer LED Pads block at the top of the gateware design allows esily overiding LEDs control by logic from another part of the FPGA design.
+
+The GPIO controller for the user LEDs is located at address 0x40000000.
+
+| LED # | GPIO # | Cape pin # |
+|-------|--------|------------|
+| 0 | 0 | P8 pin 3 |
+| 1 | 1 | P8 pin 4 |
+| 2 | 2 | P8 pin 5 |
+| 3 | 3 | P8 pin 6 |
+| 4 | 4 | P8 pin 7 |
+| 5 | 5 | P8 pin 8 |
+| 6 | 6 | P8 pin 9 |
+| 7 | 7 | P8 pin 10 |
+| 8 | 8 | P8 pin 11 |
+| 9 | 9 | P8 pin 12 |
+| 10 | 10 | P8 pin 13 |
+| 11 | 11 | P8 pin 14 |
+
--
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