diff --git a/custom-fpga-design/my_custom_fpga_design.yaml b/custom-fpga-design/my_custom_fpga_design.yaml
index e6cc1c2c978b08a2f6d6f3c8155e3fc526d6e620..f6fb8f0ce489d16645b44223dbd8d89269b12426 100644
--- a/custom-fpga-design/my_custom_fpga_design.yaml
+++ b/custom-fpga-design/my_custom_fpga_design.yaml
@@ -6,5 +6,5 @@ HSS:
board: bvf
gateware:
type: sources
- build-args: "M2_OPTION:NONE CAPE_OPTION:VERILOG_TUTORIAL"
+ build-args: "M2_OPTION:NONE CAPE_OPTION:MY_LOVELY_CAPE"
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/ADD_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b64e536efa798f6346cdbdcc5e3ab82543f01ee8
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/ADD_CAPE.tcl
@@ -0,0 +1,131 @@
+puts "======== Add cape option: MY_LOVELY_CAPE ========"
+
+#-------------------------------------------------------------------------------
+# Import HDL source files
+#-------------------------------------------------------------------------------
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v}
+import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v}
+
+build_design_hierarchy
+
+create_hdl_core -file $project_dir/hdl/CAPE.v -module {CAPE} -library {work} -package {}
+
+hdl_core_add_bif -hdl_core_name {CAPE} -bif_definition {APB:AMBA:AMBA2:slave} -bif_name {BIF_1} -signal_map {}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PADDR} -core_signal_name {APB_SLAVE_SLAVE_PADDR}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PSELx} -core_signal_name {APB_SLAVE_SLAVE_PSEL}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PENABLE} -core_signal_name {APB_SLAVE_SLAVE_PENABLE}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWRITE} -core_signal_name {APB_SLAVE_SLAVE_PWRITE}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PRDATA} -core_signal_name {APB_SLAVE_SLAVE_PRDATA}
+hdl_core_assign_bif_signal -hdl_core_name {CAPE} -bif_name {BIF_1} -bif_signal_name {PWDATA} -core_signal_name {APB_SLAVE_SLAVE_PWDATA}
+hdl_core_rename_bif -hdl_core_name {CAPE} -current_bif_name {BIF_1} -new_bif_name {APB_TARGET}
+
+#-------------------------------------------------------------------------------
+# Build the Cape module
+#-------------------------------------------------------------------------------
+set sd_name ${top_level_name}
+
+#-------------------------------------------------------------------------------
+# Cape pins
+#-------------------------------------------------------------------------------
+
+#-------------------------------------------------------------------------------
+# Instantiate.
+#-------------------------------------------------------------------------------
+
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CAPE} -instance_name {CAPE}
+
+#-------------------------------------------------------------------------------
+# Connections.
+#-------------------------------------------------------------------------------
+
+# Clocks and resets
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "CAPE:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "CAPE:PRESETN" }
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M" "CAPE:GPIO_IN"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_3} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_4} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_5} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_6} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_7} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_8} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_9} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_10} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_11} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_12} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_13} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_14} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_15} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_16} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_17} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_18} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_19} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_20} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_21} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_22} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_23} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_24} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_25} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_26} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_27} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_28} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_29} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_30} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_31} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_32} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_33} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_34} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_35} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_36} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_37} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_38} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_39} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_40} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_41} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_42} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_43} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_44} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_45} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P8_46} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_11} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_12} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_13} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_14} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_15} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_16} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_17} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_18} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_21} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_22} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_23} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_24} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_25} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_26} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_27} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_28} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_29} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_30} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_31} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_41} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE:P9_42} -port_name {}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_TARGET" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v
new file mode 100644
index 0000000000000000000000000000000000000000..af36b748ed7711caa18f7ee3f9d806e352b997d1
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/CAPE.v
@@ -0,0 +1,456 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Sun Dec 3 10:18:21 2023
+// Version: 2022.3 2022.3.0.8
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// CAPE
+module CAPE(
+ // Inputs
+ APB_SLAVE_SLAVE_PADDR,
+ APB_SLAVE_SLAVE_PENABLE,
+ APB_SLAVE_SLAVE_PSEL,
+ APB_SLAVE_SLAVE_PWDATA,
+ APB_SLAVE_SLAVE_PWRITE,
+ GPIO_OE,
+ GPIO_OUT,
+ PCLK,
+ PRESETN,
+ // Outputs
+ APB_SLAVE_SLAVE_PRDATA,
+ GPIO_IN,
+ INT_A,
+ INT_B,
+ INT_C,
+ // Inouts
+ P8_3,
+ P8_4,
+ P8_5,
+ P8_6,
+ P8_7,
+ P8_8,
+ P8_9,
+ P8_10,
+ P8_11,
+ P8_12,
+ P8_13,
+ P8_14,
+ P8_15,
+ P8_16,
+ P8_17,
+ P8_18,
+ P8_19,
+ P8_20,
+ P8_21,
+ P8_22,
+ P8_23,
+ P8_24,
+ P8_25,
+ P8_26,
+ P8_27,
+ P8_28,
+ P8_29,
+ P8_30,
+ P8_31,
+ P8_32,
+ P8_33,
+ P8_34,
+ P8_35,
+ P8_36,
+ P8_37,
+ P8_38,
+ P8_39,
+ P8_40,
+ P8_41,
+ P8_42,
+ P8_43,
+ P8_44,
+ P8_45,
+ P8_46,
+ P9_11,
+ P9_12,
+ P9_13,
+ P9_14,
+ P9_15,
+ P9_16,
+ P9_17,
+ P9_18,
+ P9_21,
+ P9_22,
+ P9_23,
+ P9_24,
+ P9_25,
+ P9_26,
+ P9_27,
+ P9_28,
+ P9_29,
+ P9_30,
+ P9_31,
+ P9_41,
+ P9_42
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input [31:0] APB_SLAVE_SLAVE_PADDR;
+input APB_SLAVE_SLAVE_PENABLE;
+input APB_SLAVE_SLAVE_PSEL;
+input [31:0] APB_SLAVE_SLAVE_PWDATA;
+input APB_SLAVE_SLAVE_PWRITE;
+input [27:0] GPIO_OE;
+input [27:0] GPIO_OUT;
+input PCLK;
+input PRESETN;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [31:0] APB_SLAVE_SLAVE_PRDATA;
+output [27:0] GPIO_IN;
+output [7:0] INT_A;
+output [7:0] INT_B;
+output [7:0] INT_C;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout P8_3;
+inout P8_4;
+inout P8_5;
+inout P8_6;
+inout P8_7;
+inout P8_8;
+inout P8_9;
+inout P8_10;
+inout P8_11;
+inout P8_12;
+inout P8_13;
+inout P8_14;
+inout P8_15;
+inout P8_16;
+inout P8_17;
+inout P8_18;
+inout P8_19;
+inout P8_20;
+inout P8_21;
+inout P8_22;
+inout P8_23;
+inout P8_24;
+inout P8_25;
+inout P8_26;
+inout P8_27;
+inout P8_28;
+inout P8_29;
+inout P8_30;
+inout P8_31;
+inout P8_32;
+inout P8_33;
+inout P8_34;
+inout P8_35;
+inout P8_36;
+inout P8_37;
+inout P8_38;
+inout P8_39;
+inout P8_40;
+inout P8_41;
+inout P8_42;
+inout P8_43;
+inout P8_44;
+inout P8_45;
+inout P8_46;
+inout P9_11;
+inout P9_12;
+inout P9_13;
+inout P9_14;
+inout P9_15;
+inout P9_16;
+inout P9_17;
+inout P9_18;
+inout P9_21;
+inout P9_22;
+inout P9_23;
+inout P9_24;
+inout P9_25;
+inout P9_26;
+inout P9_27;
+inout P9_28;
+inout P9_29;
+inout P9_30;
+inout P9_31;
+inout P9_41;
+inout P9_42;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire [31:0] apb_ctrl_status_0_control;
+wire APB_SLAVE_SLAVE_PENABLE;
+wire [31:0] APB_SLAVE_PRDATA;
+wire APB_SLAVE_SLAVE_PSEL;
+wire [31:0] APB_SLAVE_SLAVE_PWDATA;
+wire APB_SLAVE_SLAVE_PWRITE;
+wire [30:3] GPIO_IN_net_0;
+wire [27:0] GPIO_OE;
+wire [27:0] GPIO_OUT;
+wire P8_3;
+wire P8_4;
+wire P8_5;
+wire P8_6;
+wire P8_7;
+wire P8_8;
+wire P8_9;
+wire P8_10;
+wire P8_11;
+wire P8_12;
+wire P8_13;
+wire P8_14;
+wire P8_15;
+wire P8_16;
+wire P8_17;
+wire P8_18;
+wire P8_19;
+wire P8_20;
+wire P8_21;
+wire P8_22;
+wire P8_23;
+wire P8_24;
+wire P8_25;
+wire P8_26;
+wire P8_27;
+wire P8_28;
+wire P8_29;
+wire P8_30;
+wire P8_31;
+wire P8_32;
+wire P8_33;
+wire P8_34;
+wire P8_35;
+wire P8_36;
+wire P8_37;
+wire P8_38;
+wire P8_39;
+wire P8_40;
+wire P8_41;
+wire P8_42;
+wire P8_43;
+wire P8_44;
+wire P8_45;
+wire P8_46;
+wire P9_11;
+wire P9_12;
+wire P9_13;
+wire P9_14;
+wire P9_15;
+wire P9_16;
+wire P9_17;
+wire P9_18;
+wire P9_21;
+wire P9_22;
+wire P9_23;
+wire P9_24;
+wire P9_25;
+wire P9_26;
+wire P9_27;
+wire P9_28;
+wire P9_29;
+wire P9_30;
+wire P9_31;
+wire P9_41;
+wire P9_42;
+wire PCLK;
+wire PRESETN;
+wire BLINK;
+wire [31:0] APB_SLAVE_PRDATA_net_0;
+wire [27:0] GPIO_IN_net_1;
+wire [46:31] GPIO_IN_slice_0;
+wire [46:3] GPIO_OE_net_0;
+wire [46:3] GPIO_OUT_net_0;
+wire [46:3] GPIO_IN_net_2;
+//--------------------------------------------------------------------
+// TiedOff Nets
+//--------------------------------------------------------------------
+wire [46:31] GPIO_OE_const_net_0;
+wire [46:31] GPIO_OUT_const_net_0;
+wire [18:11] GPIO_OE_const_net_1;
+wire [18:11] GPIO_OUT_const_net_1;
+wire [31:21] GPIO_OE_const_net_2;
+wire [31:21] GPIO_OUT_const_net_2;
+wire [42:41] GPIO_OE_const_net_3;
+wire [42:41] GPIO_OUT_const_net_3;
+//--------------------------------------------------------------------
+// Bus Interface Nets Declarations - Unequal Pin Widths
+//--------------------------------------------------------------------
+wire [31:0] APB_SLAVE_SLAVE_PADDR;
+wire [7:0] APB_SLAVE_SLAVE_PADDR_0;
+wire [7:0] APB_SLAVE_SLAVE_PADDR_0_7to0;
+//--------------------------------------------------------------------
+// Constant assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_const_net_0 = 16'h0000;
+assign GPIO_OUT_const_net_0 = 16'h0000;
+assign GPIO_OE_const_net_1 = 8'h00;
+assign GPIO_OUT_const_net_1 = 8'h00;
+assign GPIO_OE_const_net_2 = 11'h000;
+assign GPIO_OUT_const_net_2 = 11'h000;
+assign GPIO_OE_const_net_3 = 2'h0;
+assign GPIO_OUT_const_net_3 = 2'h0;
+//--------------------------------------------------------------------
+// TieOff assignments
+//--------------------------------------------------------------------
+assign INT_A[7:0] = 8'h00;
+assign INT_B[7:0] = 8'h00;
+assign INT_C[7:0] = 8'h00;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign APB_SLAVE_PRDATA_net_0 = APB_SLAVE_PRDATA;
+assign APB_SLAVE_SLAVE_PRDATA[31:0] = APB_SLAVE_PRDATA_net_0;
+assign GPIO_IN_net_1 = GPIO_IN_net_0;
+assign GPIO_IN[27:0] = GPIO_IN_net_1;
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign GPIO_IN_net_0 = GPIO_IN_net_2[30:3];
+assign GPIO_IN_slice_0 = GPIO_IN_net_2[46:31];
+//--------------------------------------------------------------------
+// Concatenation assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE[27:6], 1'b1, GPIO_OE[4:0] };
+assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:6], BLINK, GPIO_OUT[4:0] };
+//--------------------------------------------------------------------
+// Bus Interface Nets Assignments - Unequal Pin Widths
+//--------------------------------------------------------------------
+assign APB_SLAVE_SLAVE_PADDR_0 = { APB_SLAVE_SLAVE_PADDR_0_7to0 };
+assign APB_SLAVE_SLAVE_PADDR_0_7to0 = APB_SLAVE_SLAVE_PADDR[7:0];
+
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------apb_ctrl_status
+apb_ctrl_status apb_ctrl_status_0(
+ // Inputs
+ .presetn ( PRESETN ),
+ .pclk ( PCLK ),
+ .psel ( APB_SLAVE_SLAVE_PSEL ),
+ .penable ( APB_SLAVE_SLAVE_PENABLE ),
+ .pwrite ( APB_SLAVE_SLAVE_PWRITE ),
+ .paddr ( APB_SLAVE_SLAVE_PADDR_0 ),
+ .pwdata ( APB_SLAVE_SLAVE_PWDATA ),
+ .status ( apb_ctrl_status_0_control ),
+ // Outputs
+ .prdata ( APB_SLAVE_PRDATA ),
+ .control ( apb_ctrl_status_0_control )
+ );
+
+//--------P8_IOPADS
+P8_IOPADS P8_IOPADS_0(
+ // Inputs
+ .GPIO_OE ( GPIO_OE_net_0 ),
+ .GPIO_OUT ( GPIO_OUT_net_0 ),
+ // Outputs
+ .GPIO_IN ( GPIO_IN_net_2 ),
+ // Inouts
+ .P8_3 ( P8_3 ),
+ .P8_4 ( P8_4 ),
+ .P8_5 ( P8_5 ),
+ .P8_6 ( P8_6 ),
+ .P8_7 ( P8_7 ),
+ .P8_8 ( P8_8 ),
+ .P8_9 ( P8_9 ),
+ .P8_10 ( P8_10 ),
+ .P8_11 ( P8_11 ),
+ .P8_12 ( P8_12 ),
+ .P8_13 ( P8_13 ),
+ .P8_14 ( P8_14 ),
+ .P8_15 ( P8_15 ),
+ .P8_16 ( P8_16 ),
+ .P8_17 ( P8_17 ),
+ .P8_18 ( P8_18 ),
+ .P8_19 ( P8_19 ),
+ .P8_20 ( P8_20 ),
+ .P8_21 ( P8_21 ),
+ .P8_22 ( P8_22 ),
+ .P8_23 ( P8_23 ),
+ .P8_24 ( P8_24 ),
+ .P8_25 ( P8_25 ),
+ .P8_26 ( P8_26 ),
+ .P8_27 ( P8_27 ),
+ .P8_28 ( P8_28 ),
+ .P8_29 ( P8_29 ),
+ .P8_30 ( P8_30 ),
+ .P8_31 ( P8_31 ),
+ .P8_32 ( P8_32 ),
+ .P8_33 ( P8_33 ),
+ .P8_34 ( P8_34 ),
+ .P8_35 ( P8_35 ),
+ .P8_36 ( P8_36 ),
+ .P8_37 ( P8_37 ),
+ .P8_38 ( P8_38 ),
+ .P8_39 ( P8_39 ),
+ .P8_40 ( P8_40 ),
+ .P8_41 ( P8_41 ),
+ .P8_42 ( P8_42 ),
+ .P8_43 ( P8_43 ),
+ .P8_44 ( P8_44 ),
+ .P8_45 ( P8_45 ),
+ .P8_46 ( P8_46 )
+ );
+
+//--------P9_11_18_IOPADS
+P9_11_18_IOPADS P9_11_18_IOPADS_0(
+ // Inputs
+ .GPIO_OE ( GPIO_OE_const_net_1 ),
+ .GPIO_OUT ( GPIO_OUT_const_net_1 ),
+ // Outputs
+ .GPIO_IN ( ),
+ // Inouts
+ .P9_11 ( P9_11 ),
+ .P9_12 ( P9_12 ),
+ .P9_13 ( P9_13 ),
+ .P9_14 ( P9_14 ),
+ .P9_15 ( P9_15 ),
+ .P9_16 ( P9_16 ),
+ .P9_17 ( P9_17 ),
+ .P9_18 ( P9_18 )
+ );
+
+//--------P9_21_31_IOPADS
+P9_21_31_IOPADS P9_21_31_IOPADS_0(
+ // Inputs
+ .GPIO_OE ( GPIO_OE_const_net_2 ),
+ .GPIO_OUT ( GPIO_OUT_const_net_2 ),
+ // Outputs
+ .GPIO_IN ( ),
+ // Inouts
+ .P9_21 ( P9_21 ),
+ .P9_22 ( P9_22 ),
+ .P9_23 ( P9_23 ),
+ .P9_24 ( P9_24 ),
+ .P9_25 ( P9_25 ),
+ .P9_26 ( P9_26 ),
+ .P9_27 ( P9_27 ),
+ .P9_28 ( P9_28 ),
+ .P9_29 ( P9_29 ),
+ .P9_30 ( P9_30 ),
+ .P9_31 ( P9_31 )
+ );
+
+//--------P9_41_42_IOPADS
+P9_41_42_IOPADS P9_41_42_IOPADS_0(
+ // Inputs
+ .GPIO_OE ( GPIO_OE_const_net_3 ),
+ .GPIO_OUT ( GPIO_OUT_const_net_3 ),
+ // Outputs
+ .GPIO_IN ( ),
+ // Inouts
+ .P9_41 ( P9_41 ),
+ .P9_42 ( P9_42 )
+ );
+
+//--------blinky
+blinky blinky_0(
+ .clk ( PCLK ),
+ .resetn ( PRESETN ),
+ .blink ( BLINK )
+ );
+
+endmodule
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v
new file mode 100644
index 0000000000000000000000000000000000000000..a0ed0565dec55d6216e6fdc9677d0d6864329f83
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v
@@ -0,0 +1,1013 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Sat Dec 2 16:38:15 2023
+// Version: 2022.3 2022.3.0.8
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// P8_IOPADS
+module P8_IOPADS(
+ // Inputs
+ GPIO_OE,
+ GPIO_OUT,
+ // Outputs
+ GPIO_IN,
+ // Inouts
+ P8_3,
+ P8_4,
+ P8_5,
+ P8_6,
+ P8_7,
+ P8_8,
+ P8_9,
+ P8_10,
+ P8_11,
+ P8_12,
+ P8_13,
+ P8_14,
+ P8_15,
+ P8_16,
+ P8_17,
+ P8_18,
+ P8_19,
+ P8_20,
+ P8_21,
+ P8_22,
+ P8_23,
+ P8_24,
+ P8_25,
+ P8_26,
+ P8_27,
+ P8_28,
+ P8_29,
+ P8_30,
+ P8_31,
+ P8_32,
+ P8_33,
+ P8_34,
+ P8_35,
+ P8_36,
+ P8_37,
+ P8_38,
+ P8_39,
+ P8_40,
+ P8_41,
+ P8_42,
+ P8_43,
+ P8_44,
+ P8_45,
+ P8_46
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input [46:3] GPIO_OE;
+input [46:3] GPIO_OUT;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [46:3] GPIO_IN;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout P8_3;
+inout P8_4;
+inout P8_5;
+inout P8_6;
+inout P8_7;
+inout P8_8;
+inout P8_9;
+inout P8_10;
+inout P8_11;
+inout P8_12;
+inout P8_13;
+inout P8_14;
+inout P8_15;
+inout P8_16;
+inout P8_17;
+inout P8_18;
+inout P8_19;
+inout P8_20;
+inout P8_21;
+inout P8_22;
+inout P8_23;
+inout P8_24;
+inout P8_25;
+inout P8_26;
+inout P8_27;
+inout P8_28;
+inout P8_29;
+inout P8_30;
+inout P8_31;
+inout P8_32;
+inout P8_33;
+inout P8_34;
+inout P8_35;
+inout P8_36;
+inout P8_37;
+inout P8_38;
+inout P8_39;
+inout P8_40;
+inout P8_41;
+inout P8_42;
+inout P8_43;
+inout P8_44;
+inout P8_45;
+inout P8_46;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire GPIO_IN_net_0;
+wire GPIO_IN_0;
+wire GPIO_IN_1;
+wire GPIO_IN_2;
+wire GPIO_IN_3;
+wire GPIO_IN_4;
+wire GPIO_IN_5;
+wire GPIO_IN_6;
+wire GPIO_IN_7;
+wire GPIO_IN_8;
+wire GPIO_IN_9;
+wire GPIO_IN_10;
+wire GPIO_IN_11;
+wire GPIO_IN_12;
+wire GPIO_IN_13;
+wire GPIO_IN_14;
+wire GPIO_IN_15;
+wire GPIO_IN_16;
+wire GPIO_IN_17;
+wire GPIO_IN_18;
+wire GPIO_IN_19;
+wire GPIO_IN_20;
+wire GPIO_IN_21;
+wire GPIO_IN_22;
+wire GPIO_IN_23;
+wire GPIO_IN_24;
+wire GPIO_IN_25;
+wire GPIO_IN_26;
+wire GPIO_IN_27;
+wire GPIO_IN_28;
+wire GPIO_IN_29;
+wire GPIO_IN_30;
+wire GPIO_IN_31;
+wire GPIO_IN_32;
+wire GPIO_IN_33;
+wire GPIO_IN_34;
+wire GPIO_IN_35;
+wire GPIO_IN_36;
+wire GPIO_IN_37;
+wire GPIO_IN_38;
+wire GPIO_IN_39;
+wire GPIO_IN_40;
+wire GPIO_IN_41;
+wire GPIO_IN_42;
+wire [3:3] GPIO_OE_slice_0;
+wire [4:4] GPIO_OE_slice_1;
+wire [5:5] GPIO_OE_slice_2;
+wire [6:6] GPIO_OE_slice_3;
+wire [7:7] GPIO_OE_slice_4;
+wire [8:8] GPIO_OE_slice_5;
+wire [9:9] GPIO_OE_slice_6;
+wire [10:10] GPIO_OE_slice_7;
+wire [11:11] GPIO_OE_slice_8;
+wire [12:12] GPIO_OE_slice_9;
+wire [13:13] GPIO_OE_slice_10;
+wire [14:14] GPIO_OE_slice_11;
+wire [15:15] GPIO_OE_slice_12;
+wire [16:16] GPIO_OE_slice_13;
+wire [17:17] GPIO_OE_slice_14;
+wire [18:18] GPIO_OE_slice_15;
+wire [19:19] GPIO_OE_slice_16;
+wire [20:20] GPIO_OE_slice_17;
+wire [21:21] GPIO_OE_slice_18;
+wire [22:22] GPIO_OE_slice_19;
+wire [23:23] GPIO_OE_slice_20;
+wire [24:24] GPIO_OE_slice_21;
+wire [25:25] GPIO_OE_slice_22;
+wire [26:26] GPIO_OE_slice_23;
+wire [27:27] GPIO_OE_slice_24;
+wire [28:28] GPIO_OE_slice_25;
+wire [29:29] GPIO_OE_slice_26;
+wire [30:30] GPIO_OE_slice_27;
+wire [31:31] GPIO_OE_slice_28;
+wire [32:32] GPIO_OE_slice_29;
+wire [33:33] GPIO_OE_slice_30;
+wire [34:34] GPIO_OE_slice_31;
+wire [35:35] GPIO_OE_slice_32;
+wire [36:36] GPIO_OE_slice_33;
+wire [37:37] GPIO_OE_slice_34;
+wire [38:38] GPIO_OE_slice_35;
+wire [39:39] GPIO_OE_slice_36;
+wire [40:40] GPIO_OE_slice_37;
+wire [41:41] GPIO_OE_slice_38;
+wire [42:42] GPIO_OE_slice_39;
+wire [43:43] GPIO_OE_slice_40;
+wire [44:44] GPIO_OE_slice_41;
+wire [45:45] GPIO_OE_slice_42;
+wire [46:46] GPIO_OE_slice_43;
+wire [3:3] GPIO_OUT_slice_0;
+wire [4:4] GPIO_OUT_slice_1;
+wire [5:5] GPIO_OUT_slice_2;
+wire [6:6] GPIO_OUT_slice_3;
+wire [7:7] GPIO_OUT_slice_4;
+wire [8:8] GPIO_OUT_slice_5;
+wire [9:9] GPIO_OUT_slice_6;
+wire [10:10] GPIO_OUT_slice_7;
+wire [11:11] GPIO_OUT_slice_8;
+wire [12:12] GPIO_OUT_slice_9;
+wire [13:13] GPIO_OUT_slice_10;
+wire [14:14] GPIO_OUT_slice_11;
+wire [15:15] GPIO_OUT_slice_12;
+wire [16:16] GPIO_OUT_slice_13;
+wire [17:17] GPIO_OUT_slice_14;
+wire [18:18] GPIO_OUT_slice_15;
+wire [19:19] GPIO_OUT_slice_16;
+wire [20:20] GPIO_OUT_slice_17;
+wire [21:21] GPIO_OUT_slice_18;
+wire [22:22] GPIO_OUT_slice_19;
+wire [23:23] GPIO_OUT_slice_20;
+wire [24:24] GPIO_OUT_slice_21;
+wire [25:25] GPIO_OUT_slice_22;
+wire [26:26] GPIO_OUT_slice_23;
+wire [27:27] GPIO_OUT_slice_24;
+wire [28:28] GPIO_OUT_slice_25;
+wire [29:29] GPIO_OUT_slice_26;
+wire [30:30] GPIO_OUT_slice_27;
+wire [31:31] GPIO_OUT_slice_28;
+wire [32:32] GPIO_OUT_slice_29;
+wire [33:33] GPIO_OUT_slice_30;
+wire [34:34] GPIO_OUT_slice_31;
+wire [35:35] GPIO_OUT_slice_32;
+wire [36:36] GPIO_OUT_slice_33;
+wire [37:37] GPIO_OUT_slice_34;
+wire [38:38] GPIO_OUT_slice_35;
+wire [39:39] GPIO_OUT_slice_36;
+wire [40:40] GPIO_OUT_slice_37;
+wire [41:41] GPIO_OUT_slice_38;
+wire [42:42] GPIO_OUT_slice_39;
+wire [43:43] GPIO_OUT_slice_40;
+wire [44:44] GPIO_OUT_slice_41;
+wire [45:45] GPIO_OUT_slice_42;
+wire [46:46] GPIO_OUT_slice_43;
+wire P8_3;
+wire P8_4;
+wire P8_5;
+wire P8_6;
+wire P8_7;
+wire P8_8;
+wire P8_9;
+wire P8_10;
+wire P8_11;
+wire P8_12;
+wire P8_13;
+wire P8_14;
+wire P8_15;
+wire P8_16;
+wire P8_17;
+wire P8_18;
+wire P8_19;
+wire P8_20;
+wire P8_21;
+wire P8_22;
+wire P8_23;
+wire P8_24;
+wire P8_25;
+wire P8_26;
+wire P8_27;
+wire P8_28;
+wire P8_29;
+wire P8_30;
+wire P8_31;
+wire P8_32;
+wire P8_33;
+wire P8_34;
+wire P8_35;
+wire P8_36;
+wire P8_37;
+wire P8_38;
+wire P8_39;
+wire P8_40;
+wire P8_41;
+wire P8_42;
+wire P8_43;
+wire P8_44;
+wire P8_45;
+wire P8_46;
+wire [10:10] GPIO_IN_6_net_0;
+wire [11:11] GPIO_IN_7_net_0;
+wire [12:12] GPIO_IN_8_net_0;
+wire [13:13] GPIO_IN_9_net_0;
+wire [14:14] GPIO_IN_10_net_0;
+wire [15:15] GPIO_IN_11_net_0;
+wire [16:16] GPIO_IN_12_net_0;
+wire [17:17] GPIO_IN_13_net_0;
+wire [18:18] GPIO_IN_14_net_0;
+wire [19:19] GPIO_IN_15_net_0;
+wire [20:20] GPIO_IN_16_net_0;
+wire [21:21] GPIO_IN_17_net_0;
+wire [22:22] GPIO_IN_18_net_0;
+wire [23:23] GPIO_IN_19_net_0;
+wire [24:24] GPIO_IN_20_net_0;
+wire [25:25] GPIO_IN_21_net_0;
+wire [26:26] GPIO_IN_22_net_0;
+wire [27:27] GPIO_IN_23_net_0;
+wire [28:28] GPIO_IN_24_net_0;
+wire [29:29] GPIO_IN_25_net_0;
+wire [30:30] GPIO_IN_26_net_0;
+wire [31:31] GPIO_IN_27_net_0;
+wire [32:32] GPIO_IN_28_net_0;
+wire [33:33] GPIO_IN_29_net_0;
+wire [34:34] GPIO_IN_30_net_0;
+wire [35:35] GPIO_IN_31_net_0;
+wire [36:36] GPIO_IN_32_net_0;
+wire [37:37] GPIO_IN_33_net_0;
+wire [38:38] GPIO_IN_34_net_0;
+wire [39:39] GPIO_IN_35_net_0;
+wire [3:3] GPIO_IN_net_1;
+wire [40:40] GPIO_IN_36_net_0;
+wire [41:41] GPIO_IN_37_net_0;
+wire [42:42] GPIO_IN_38_net_0;
+wire [43:43] GPIO_IN_39_net_0;
+wire [44:44] GPIO_IN_40_net_0;
+wire [45:45] GPIO_IN_41_net_0;
+wire [46:46] GPIO_IN_42_net_0;
+wire [4:4] GPIO_IN_0_net_0;
+wire [5:5] GPIO_IN_1_net_0;
+wire [6:6] GPIO_IN_2_net_0;
+wire [7:7] GPIO_IN_3_net_0;
+wire [8:8] GPIO_IN_4_net_0;
+wire [9:9] GPIO_IN_5_net_0;
+wire [46:3] GPIO_OUT;
+wire [46:3] GPIO_OE;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign GPIO_IN_6_net_0[10] = GPIO_IN_6;
+assign GPIO_IN[10:10] = GPIO_IN_6_net_0[10];
+assign GPIO_IN_7_net_0[11] = GPIO_IN_7;
+assign GPIO_IN[11:11] = GPIO_IN_7_net_0[11];
+assign GPIO_IN_8_net_0[12] = GPIO_IN_8;
+assign GPIO_IN[12:12] = GPIO_IN_8_net_0[12];
+assign GPIO_IN_9_net_0[13] = GPIO_IN_9;
+assign GPIO_IN[13:13] = GPIO_IN_9_net_0[13];
+assign GPIO_IN_10_net_0[14] = GPIO_IN_10;
+assign GPIO_IN[14:14] = GPIO_IN_10_net_0[14];
+assign GPIO_IN_11_net_0[15] = GPIO_IN_11;
+assign GPIO_IN[15:15] = GPIO_IN_11_net_0[15];
+assign GPIO_IN_12_net_0[16] = GPIO_IN_12;
+assign GPIO_IN[16:16] = GPIO_IN_12_net_0[16];
+assign GPIO_IN_13_net_0[17] = GPIO_IN_13;
+assign GPIO_IN[17:17] = GPIO_IN_13_net_0[17];
+assign GPIO_IN_14_net_0[18] = GPIO_IN_14;
+assign GPIO_IN[18:18] = GPIO_IN_14_net_0[18];
+assign GPIO_IN_15_net_0[19] = GPIO_IN_15;
+assign GPIO_IN[19:19] = GPIO_IN_15_net_0[19];
+assign GPIO_IN_16_net_0[20] = GPIO_IN_16;
+assign GPIO_IN[20:20] = GPIO_IN_16_net_0[20];
+assign GPIO_IN_17_net_0[21] = GPIO_IN_17;
+assign GPIO_IN[21:21] = GPIO_IN_17_net_0[21];
+assign GPIO_IN_18_net_0[22] = GPIO_IN_18;
+assign GPIO_IN[22:22] = GPIO_IN_18_net_0[22];
+assign GPIO_IN_19_net_0[23] = GPIO_IN_19;
+assign GPIO_IN[23:23] = GPIO_IN_19_net_0[23];
+assign GPIO_IN_20_net_0[24] = GPIO_IN_20;
+assign GPIO_IN[24:24] = GPIO_IN_20_net_0[24];
+assign GPIO_IN_21_net_0[25] = GPIO_IN_21;
+assign GPIO_IN[25:25] = GPIO_IN_21_net_0[25];
+assign GPIO_IN_22_net_0[26] = GPIO_IN_22;
+assign GPIO_IN[26:26] = GPIO_IN_22_net_0[26];
+assign GPIO_IN_23_net_0[27] = GPIO_IN_23;
+assign GPIO_IN[27:27] = GPIO_IN_23_net_0[27];
+assign GPIO_IN_24_net_0[28] = GPIO_IN_24;
+assign GPIO_IN[28:28] = GPIO_IN_24_net_0[28];
+assign GPIO_IN_25_net_0[29] = GPIO_IN_25;
+assign GPIO_IN[29:29] = GPIO_IN_25_net_0[29];
+assign GPIO_IN_26_net_0[30] = GPIO_IN_26;
+assign GPIO_IN[30:30] = GPIO_IN_26_net_0[30];
+assign GPIO_IN_27_net_0[31] = GPIO_IN_27;
+assign GPIO_IN[31:31] = GPIO_IN_27_net_0[31];
+assign GPIO_IN_28_net_0[32] = GPIO_IN_28;
+assign GPIO_IN[32:32] = GPIO_IN_28_net_0[32];
+assign GPIO_IN_29_net_0[33] = GPIO_IN_29;
+assign GPIO_IN[33:33] = GPIO_IN_29_net_0[33];
+assign GPIO_IN_30_net_0[34] = GPIO_IN_30;
+assign GPIO_IN[34:34] = GPIO_IN_30_net_0[34];
+assign GPIO_IN_31_net_0[35] = GPIO_IN_31;
+assign GPIO_IN[35:35] = GPIO_IN_31_net_0[35];
+assign GPIO_IN_32_net_0[36] = GPIO_IN_32;
+assign GPIO_IN[36:36] = GPIO_IN_32_net_0[36];
+assign GPIO_IN_33_net_0[37] = GPIO_IN_33;
+assign GPIO_IN[37:37] = GPIO_IN_33_net_0[37];
+assign GPIO_IN_34_net_0[38] = GPIO_IN_34;
+assign GPIO_IN[38:38] = GPIO_IN_34_net_0[38];
+assign GPIO_IN_35_net_0[39] = GPIO_IN_35;
+assign GPIO_IN[39:39] = GPIO_IN_35_net_0[39];
+assign GPIO_IN_net_1[3] = GPIO_IN_net_0;
+assign GPIO_IN[3:3] = GPIO_IN_net_1[3];
+assign GPIO_IN_36_net_0[40] = GPIO_IN_36;
+assign GPIO_IN[40:40] = GPIO_IN_36_net_0[40];
+assign GPIO_IN_37_net_0[41] = GPIO_IN_37;
+assign GPIO_IN[41:41] = GPIO_IN_37_net_0[41];
+assign GPIO_IN_38_net_0[42] = GPIO_IN_38;
+assign GPIO_IN[42:42] = GPIO_IN_38_net_0[42];
+assign GPIO_IN_39_net_0[43] = GPIO_IN_39;
+assign GPIO_IN[43:43] = GPIO_IN_39_net_0[43];
+assign GPIO_IN_40_net_0[44] = GPIO_IN_40;
+assign GPIO_IN[44:44] = GPIO_IN_40_net_0[44];
+assign GPIO_IN_41_net_0[45] = GPIO_IN_41;
+assign GPIO_IN[45:45] = GPIO_IN_41_net_0[45];
+assign GPIO_IN_42_net_0[46] = GPIO_IN_42;
+assign GPIO_IN[46:46] = GPIO_IN_42_net_0[46];
+assign GPIO_IN_0_net_0[4] = GPIO_IN_0;
+assign GPIO_IN[4:4] = GPIO_IN_0_net_0[4];
+assign GPIO_IN_1_net_0[5] = GPIO_IN_1;
+assign GPIO_IN[5:5] = GPIO_IN_1_net_0[5];
+assign GPIO_IN_2_net_0[6] = GPIO_IN_2;
+assign GPIO_IN[6:6] = GPIO_IN_2_net_0[6];
+assign GPIO_IN_3_net_0[7] = GPIO_IN_3;
+assign GPIO_IN[7:7] = GPIO_IN_3_net_0[7];
+assign GPIO_IN_4_net_0[8] = GPIO_IN_4;
+assign GPIO_IN[8:8] = GPIO_IN_4_net_0[8];
+assign GPIO_IN_5_net_0[9] = GPIO_IN_5;
+assign GPIO_IN[9:9] = GPIO_IN_5_net_0[9];
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_slice_0[3] = GPIO_OE[3:3];
+assign GPIO_OE_slice_1[4] = GPIO_OE[4:4];
+assign GPIO_OE_slice_2[5] = GPIO_OE[5:5];
+assign GPIO_OE_slice_3[6] = GPIO_OE[6:6];
+assign GPIO_OE_slice_4[7] = GPIO_OE[7:7];
+assign GPIO_OE_slice_5[8] = GPIO_OE[8:8];
+assign GPIO_OE_slice_6[9] = GPIO_OE[9:9];
+assign GPIO_OE_slice_7[10] = GPIO_OE[10:10];
+assign GPIO_OE_slice_8[11] = GPIO_OE[11:11];
+assign GPIO_OE_slice_9[12] = GPIO_OE[12:12];
+assign GPIO_OE_slice_10[13] = GPIO_OE[13:13];
+assign GPIO_OE_slice_11[14] = GPIO_OE[14:14];
+assign GPIO_OE_slice_12[15] = GPIO_OE[15:15];
+assign GPIO_OE_slice_13[16] = GPIO_OE[16:16];
+assign GPIO_OE_slice_14[17] = GPIO_OE[17:17];
+assign GPIO_OE_slice_15[18] = GPIO_OE[18:18];
+assign GPIO_OE_slice_16[19] = GPIO_OE[19:19];
+assign GPIO_OE_slice_17[20] = GPIO_OE[20:20];
+assign GPIO_OE_slice_18[21] = GPIO_OE[21:21];
+assign GPIO_OE_slice_19[22] = GPIO_OE[22:22];
+assign GPIO_OE_slice_20[23] = GPIO_OE[23:23];
+assign GPIO_OE_slice_21[24] = GPIO_OE[24:24];
+assign GPIO_OE_slice_22[25] = GPIO_OE[25:25];
+assign GPIO_OE_slice_23[26] = GPIO_OE[26:26];
+assign GPIO_OE_slice_24[27] = GPIO_OE[27:27];
+assign GPIO_OE_slice_25[28] = GPIO_OE[28:28];
+assign GPIO_OE_slice_26[29] = GPIO_OE[29:29];
+assign GPIO_OE_slice_27[30] = GPIO_OE[30:30];
+assign GPIO_OE_slice_28[31] = GPIO_OE[31:31];
+assign GPIO_OE_slice_29[32] = GPIO_OE[32:32];
+assign GPIO_OE_slice_30[33] = GPIO_OE[33:33];
+assign GPIO_OE_slice_31[34] = GPIO_OE[34:34];
+assign GPIO_OE_slice_32[35] = GPIO_OE[35:35];
+assign GPIO_OE_slice_33[36] = GPIO_OE[36:36];
+assign GPIO_OE_slice_34[37] = GPIO_OE[37:37];
+assign GPIO_OE_slice_35[38] = GPIO_OE[38:38];
+assign GPIO_OE_slice_36[39] = GPIO_OE[39:39];
+assign GPIO_OE_slice_37[40] = GPIO_OE[40:40];
+assign GPIO_OE_slice_38[41] = GPIO_OE[41:41];
+assign GPIO_OE_slice_39[42] = GPIO_OE[42:42];
+assign GPIO_OE_slice_40[43] = GPIO_OE[43:43];
+assign GPIO_OE_slice_41[44] = GPIO_OE[44:44];
+assign GPIO_OE_slice_42[45] = GPIO_OE[45:45];
+assign GPIO_OE_slice_43[46] = GPIO_OE[46:46];
+assign GPIO_OUT_slice_0[3] = GPIO_OUT[3:3];
+assign GPIO_OUT_slice_1[4] = GPIO_OUT[4:4];
+assign GPIO_OUT_slice_2[5] = GPIO_OUT[5:5];
+assign GPIO_OUT_slice_3[6] = GPIO_OUT[6:6];
+assign GPIO_OUT_slice_4[7] = GPIO_OUT[7:7];
+assign GPIO_OUT_slice_5[8] = GPIO_OUT[8:8];
+assign GPIO_OUT_slice_6[9] = GPIO_OUT[9:9];
+assign GPIO_OUT_slice_7[10] = GPIO_OUT[10:10];
+assign GPIO_OUT_slice_8[11] = GPIO_OUT[11:11];
+assign GPIO_OUT_slice_9[12] = GPIO_OUT[12:12];
+assign GPIO_OUT_slice_10[13] = GPIO_OUT[13:13];
+assign GPIO_OUT_slice_11[14] = GPIO_OUT[14:14];
+assign GPIO_OUT_slice_12[15] = GPIO_OUT[15:15];
+assign GPIO_OUT_slice_13[16] = GPIO_OUT[16:16];
+assign GPIO_OUT_slice_14[17] = GPIO_OUT[17:17];
+assign GPIO_OUT_slice_15[18] = GPIO_OUT[18:18];
+assign GPIO_OUT_slice_16[19] = GPIO_OUT[19:19];
+assign GPIO_OUT_slice_17[20] = GPIO_OUT[20:20];
+assign GPIO_OUT_slice_18[21] = GPIO_OUT[21:21];
+assign GPIO_OUT_slice_19[22] = GPIO_OUT[22:22];
+assign GPIO_OUT_slice_20[23] = GPIO_OUT[23:23];
+assign GPIO_OUT_slice_21[24] = GPIO_OUT[24:24];
+assign GPIO_OUT_slice_22[25] = GPIO_OUT[25:25];
+assign GPIO_OUT_slice_23[26] = GPIO_OUT[26:26];
+assign GPIO_OUT_slice_24[27] = GPIO_OUT[27:27];
+assign GPIO_OUT_slice_25[28] = GPIO_OUT[28:28];
+assign GPIO_OUT_slice_26[29] = GPIO_OUT[29:29];
+assign GPIO_OUT_slice_27[30] = GPIO_OUT[30:30];
+assign GPIO_OUT_slice_28[31] = GPIO_OUT[31:31];
+assign GPIO_OUT_slice_29[32] = GPIO_OUT[32:32];
+assign GPIO_OUT_slice_30[33] = GPIO_OUT[33:33];
+assign GPIO_OUT_slice_31[34] = GPIO_OUT[34:34];
+assign GPIO_OUT_slice_32[35] = GPIO_OUT[35:35];
+assign GPIO_OUT_slice_33[36] = GPIO_OUT[36:36];
+assign GPIO_OUT_slice_34[37] = GPIO_OUT[37:37];
+assign GPIO_OUT_slice_35[38] = GPIO_OUT[38:38];
+assign GPIO_OUT_slice_36[39] = GPIO_OUT[39:39];
+assign GPIO_OUT_slice_37[40] = GPIO_OUT[40:40];
+assign GPIO_OUT_slice_38[41] = GPIO_OUT[41:41];
+assign GPIO_OUT_slice_39[42] = GPIO_OUT[42:42];
+assign GPIO_OUT_slice_40[43] = GPIO_OUT[43:43];
+assign GPIO_OUT_slice_41[44] = GPIO_OUT[44:44];
+assign GPIO_OUT_slice_42[45] = GPIO_OUT[45:45];
+assign GPIO_OUT_slice_43[46] = GPIO_OUT[46:46];
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------BIBUF
+BIBUF P8_3_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_0 ),
+ .E ( GPIO_OE_slice_0 ),
+ // Outputs
+ .Y ( GPIO_IN_net_0 ),
+ // Inouts
+ .PAD ( P8_3 )
+ );
+
+//--------BIBUF
+BIBUF P8_4_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_1 ),
+ .E ( GPIO_OE_slice_1 ),
+ // Outputs
+ .Y ( GPIO_IN_0 ),
+ // Inouts
+ .PAD ( P8_4 )
+ );
+
+//--------BIBUF
+BIBUF P8_5_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_2 ),
+ .E ( GPIO_OE_slice_2 ),
+ // Outputs
+ .Y ( GPIO_IN_1 ),
+ // Inouts
+ .PAD ( P8_5 )
+ );
+
+//--------BIBUF
+BIBUF P8_6_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_3 ),
+ .E ( GPIO_OE_slice_3 ),
+ // Outputs
+ .Y ( GPIO_IN_2 ),
+ // Inouts
+ .PAD ( P8_6 )
+ );
+
+//--------BIBUF
+BIBUF P8_7_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_4 ),
+ .E ( GPIO_OE_slice_4 ),
+ // Outputs
+ .Y ( GPIO_IN_3 ),
+ // Inouts
+ .PAD ( P8_7 )
+ );
+
+//--------BIBUF
+BIBUF P8_8_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_5 ),
+ .E ( GPIO_OE_slice_5 ),
+ // Outputs
+ .Y ( GPIO_IN_4 ),
+ // Inouts
+ .PAD ( P8_8 )
+ );
+
+//--------BIBUF
+BIBUF P8_9_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_6 ),
+ .E ( GPIO_OE_slice_6 ),
+ // Outputs
+ .Y ( GPIO_IN_5 ),
+ // Inouts
+ .PAD ( P8_9 )
+ );
+
+//--------BIBUF
+BIBUF P8_10_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_7 ),
+ .E ( GPIO_OE_slice_7 ),
+ // Outputs
+ .Y ( GPIO_IN_6 ),
+ // Inouts
+ .PAD ( P8_10 )
+ );
+
+//--------BIBUF
+BIBUF P8_11_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_8 ),
+ .E ( GPIO_OE_slice_8 ),
+ // Outputs
+ .Y ( GPIO_IN_7 ),
+ // Inouts
+ .PAD ( P8_11 )
+ );
+
+//--------BIBUF
+BIBUF P8_12_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_9 ),
+ .E ( GPIO_OE_slice_9 ),
+ // Outputs
+ .Y ( GPIO_IN_8 ),
+ // Inouts
+ .PAD ( P8_12 )
+ );
+
+//--------BIBUF
+BIBUF P8_13_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_10 ),
+ .E ( GPIO_OE_slice_10 ),
+ // Outputs
+ .Y ( GPIO_IN_9 ),
+ // Inouts
+ .PAD ( P8_13 )
+ );
+
+//--------BIBUF
+BIBUF P8_14_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_11 ),
+ .E ( GPIO_OE_slice_11 ),
+ // Outputs
+ .Y ( GPIO_IN_10 ),
+ // Inouts
+ .PAD ( P8_14 )
+ );
+
+//--------BIBUF
+BIBUF P8_15_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_12 ),
+ .E ( GPIO_OE_slice_12 ),
+ // Outputs
+ .Y ( GPIO_IN_11 ),
+ // Inouts
+ .PAD ( P8_15 )
+ );
+
+//--------BIBUF
+BIBUF P8_16_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_13 ),
+ .E ( GPIO_OE_slice_13 ),
+ // Outputs
+ .Y ( GPIO_IN_12 ),
+ // Inouts
+ .PAD ( P8_16 )
+ );
+
+//--------BIBUF
+BIBUF P8_17_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_14 ),
+ .E ( GPIO_OE_slice_14 ),
+ // Outputs
+ .Y ( GPIO_IN_13 ),
+ // Inouts
+ .PAD ( P8_17 )
+ );
+
+//--------BIBUF
+BIBUF P8_18_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_15 ),
+ .E ( GPIO_OE_slice_15 ),
+ // Outputs
+ .Y ( GPIO_IN_14 ),
+ // Inouts
+ .PAD ( P8_18 )
+ );
+
+//--------BIBUF
+BIBUF P8_19_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_16 ),
+ .E ( GPIO_OE_slice_16 ),
+ // Outputs
+ .Y ( GPIO_IN_15 ),
+ // Inouts
+ .PAD ( P8_19 )
+ );
+
+//--------BIBUF
+BIBUF P8_20_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_17 ),
+ .E ( GPIO_OE_slice_17 ),
+ // Outputs
+ .Y ( GPIO_IN_16 ),
+ // Inouts
+ .PAD ( P8_20 )
+ );
+
+//--------BIBUF
+BIBUF P8_21_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_18 ),
+ .E ( GPIO_OE_slice_18 ),
+ // Outputs
+ .Y ( GPIO_IN_17 ),
+ // Inouts
+ .PAD ( P8_21 )
+ );
+
+//--------BIBUF
+BIBUF P8_22_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_19 ),
+ .E ( GPIO_OE_slice_19 ),
+ // Outputs
+ .Y ( GPIO_IN_18 ),
+ // Inouts
+ .PAD ( P8_22 )
+ );
+
+//--------BIBUF
+BIBUF P8_23_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_20 ),
+ .E ( GPIO_OE_slice_20 ),
+ // Outputs
+ .Y ( GPIO_IN_19 ),
+ // Inouts
+ .PAD ( P8_23 )
+ );
+
+//--------BIBUF
+BIBUF P8_24_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_21 ),
+ .E ( GPIO_OE_slice_21 ),
+ // Outputs
+ .Y ( GPIO_IN_20 ),
+ // Inouts
+ .PAD ( P8_24 )
+ );
+
+//--------BIBUF
+BIBUF P8_25_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_22 ),
+ .E ( GPIO_OE_slice_22 ),
+ // Outputs
+ .Y ( GPIO_IN_21 ),
+ // Inouts
+ .PAD ( P8_25 )
+ );
+
+//--------BIBUF
+BIBUF P8_26_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_23 ),
+ .E ( GPIO_OE_slice_23 ),
+ // Outputs
+ .Y ( GPIO_IN_22 ),
+ // Inouts
+ .PAD ( P8_26 )
+ );
+
+//--------BIBUF
+BIBUF P8_27_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_24 ),
+ .E ( GPIO_OE_slice_24 ),
+ // Outputs
+ .Y ( GPIO_IN_23 ),
+ // Inouts
+ .PAD ( P8_27 )
+ );
+
+//--------BIBUF
+BIBUF P8_28_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_25 ),
+ .E ( GPIO_OE_slice_25 ),
+ // Outputs
+ .Y ( GPIO_IN_24 ),
+ // Inouts
+ .PAD ( P8_28 )
+ );
+
+//--------BIBUF
+BIBUF P8_29_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_26 ),
+ .E ( GPIO_OE_slice_26 ),
+ // Outputs
+ .Y ( GPIO_IN_25 ),
+ // Inouts
+ .PAD ( P8_29 )
+ );
+
+//--------BIBUF
+BIBUF P8_30_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_27 ),
+ .E ( GPIO_OE_slice_27 ),
+ // Outputs
+ .Y ( GPIO_IN_26 ),
+ // Inouts
+ .PAD ( P8_30 )
+ );
+
+//--------BIBUF
+BIBUF P8_31_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_28 ),
+ .E ( GPIO_OE_slice_28 ),
+ // Outputs
+ .Y ( GPIO_IN_27 ),
+ // Inouts
+ .PAD ( P8_31 )
+ );
+
+//--------BIBUF
+BIBUF P8_32_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_29 ),
+ .E ( GPIO_OE_slice_29 ),
+ // Outputs
+ .Y ( GPIO_IN_28 ),
+ // Inouts
+ .PAD ( P8_32 )
+ );
+
+//--------BIBUF
+BIBUF P8_33_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_30 ),
+ .E ( GPIO_OE_slice_30 ),
+ // Outputs
+ .Y ( GPIO_IN_29 ),
+ // Inouts
+ .PAD ( P8_33 )
+ );
+
+//--------BIBUF
+BIBUF P8_34_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_31 ),
+ .E ( GPIO_OE_slice_31 ),
+ // Outputs
+ .Y ( GPIO_IN_30 ),
+ // Inouts
+ .PAD ( P8_34 )
+ );
+
+//--------BIBUF
+BIBUF P8_35_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_32 ),
+ .E ( GPIO_OE_slice_32 ),
+ // Outputs
+ .Y ( GPIO_IN_31 ),
+ // Inouts
+ .PAD ( P8_35 )
+ );
+
+//--------BIBUF
+BIBUF P8_36_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_33 ),
+ .E ( GPIO_OE_slice_33 ),
+ // Outputs
+ .Y ( GPIO_IN_32 ),
+ // Inouts
+ .PAD ( P8_36 )
+ );
+
+//--------BIBUF
+BIBUF P8_37_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_34 ),
+ .E ( GPIO_OE_slice_34 ),
+ // Outputs
+ .Y ( GPIO_IN_33 ),
+ // Inouts
+ .PAD ( P8_37 )
+ );
+
+//--------BIBUF
+BIBUF P8_38_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_35 ),
+ .E ( GPIO_OE_slice_35 ),
+ // Outputs
+ .Y ( GPIO_IN_34 ),
+ // Inouts
+ .PAD ( P8_38 )
+ );
+
+//--------BIBUF
+BIBUF P8_39_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_36 ),
+ .E ( GPIO_OE_slice_36 ),
+ // Outputs
+ .Y ( GPIO_IN_35 ),
+ // Inouts
+ .PAD ( P8_39 )
+ );
+
+//--------BIBUF
+BIBUF P8_40_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_37 ),
+ .E ( GPIO_OE_slice_37 ),
+ // Outputs
+ .Y ( GPIO_IN_36 ),
+ // Inouts
+ .PAD ( P8_40 )
+ );
+
+//--------BIBUF
+BIBUF P8_41_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_38 ),
+ .E ( GPIO_OE_slice_38 ),
+ // Outputs
+ .Y ( GPIO_IN_37 ),
+ // Inouts
+ .PAD ( P8_41 )
+ );
+
+//--------BIBUF
+BIBUF P8_42_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_39 ),
+ .E ( GPIO_OE_slice_39 ),
+ // Outputs
+ .Y ( GPIO_IN_38 ),
+ // Inouts
+ .PAD ( P8_42 )
+ );
+
+//--------BIBUF
+BIBUF P8_43_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_40 ),
+ .E ( GPIO_OE_slice_40 ),
+ // Outputs
+ .Y ( GPIO_IN_39 ),
+ // Inouts
+ .PAD ( P8_43 )
+ );
+
+//--------BIBUF
+BIBUF P8_44_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_41 ),
+ .E ( GPIO_OE_slice_41 ),
+ // Outputs
+ .Y ( GPIO_IN_40 ),
+ // Inouts
+ .PAD ( P8_44 )
+ );
+
+//--------BIBUF
+BIBUF P8_45_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_42 ),
+ .E ( GPIO_OE_slice_42 ),
+ // Outputs
+ .Y ( GPIO_IN_41 ),
+ // Inouts
+ .PAD ( P8_45 )
+ );
+
+//--------BIBUF
+BIBUF P8_46_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_43 ),
+ .E ( GPIO_OE_slice_43 ),
+ // Outputs
+ .Y ( GPIO_IN_42 ),
+ // Inouts
+ .PAD ( P8_46 )
+ );
+
+
+endmodule
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v
new file mode 100644
index 0000000000000000000000000000000000000000..afda4e23b2f214f8a08d3b6ead6c6f86ea0cdef4
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v
@@ -0,0 +1,221 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Sat Dec 2 16:38:15 2023
+// Version: 2022.3 2022.3.0.8
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// P9_11_18_IOPADS
+module P9_11_18_IOPADS(
+ // Inputs
+ GPIO_OE,
+ GPIO_OUT,
+ // Outputs
+ GPIO_IN,
+ // Inouts
+ P9_11,
+ P9_12,
+ P9_13,
+ P9_14,
+ P9_15,
+ P9_16,
+ P9_17,
+ P9_18
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input [18:11] GPIO_OE;
+input [18:11] GPIO_OUT;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [18:11] GPIO_IN;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout P9_11;
+inout P9_12;
+inout P9_13;
+inout P9_14;
+inout P9_15;
+inout P9_16;
+inout P9_17;
+inout P9_18;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire GPIO_IN_net_0;
+wire GPIO_IN_0;
+wire GPIO_IN_1;
+wire GPIO_IN_2;
+wire GPIO_IN_3;
+wire GPIO_IN_4;
+wire GPIO_IN_5;
+wire GPIO_IN_6;
+wire [11:11] GPIO_OE_slice_0;
+wire [12:12] GPIO_OE_slice_1;
+wire [13:13] GPIO_OE_slice_2;
+wire [14:14] GPIO_OE_slice_3;
+wire [15:15] GPIO_OE_slice_4;
+wire [16:16] GPIO_OE_slice_5;
+wire [17:17] GPIO_OE_slice_6;
+wire [18:18] GPIO_OE_slice_7;
+wire [11:11] GPIO_OUT_slice_0;
+wire [12:12] GPIO_OUT_slice_1;
+wire [13:13] GPIO_OUT_slice_2;
+wire [14:14] GPIO_OUT_slice_3;
+wire [15:15] GPIO_OUT_slice_4;
+wire [16:16] GPIO_OUT_slice_5;
+wire [17:17] GPIO_OUT_slice_6;
+wire [18:18] GPIO_OUT_slice_7;
+wire P9_11;
+wire P9_12;
+wire P9_13;
+wire P9_14;
+wire P9_15;
+wire P9_16;
+wire P9_17;
+wire P9_18;
+wire [11:11] GPIO_IN_net_1;
+wire [12:12] GPIO_IN_0_net_0;
+wire [13:13] GPIO_IN_1_net_0;
+wire [14:14] GPIO_IN_2_net_0;
+wire [15:15] GPIO_IN_3_net_0;
+wire [16:16] GPIO_IN_4_net_0;
+wire [17:17] GPIO_IN_5_net_0;
+wire [18:18] GPIO_IN_6_net_0;
+wire [18:11] GPIO_OUT;
+wire [18:11] GPIO_OE;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign GPIO_IN_net_1[11] = GPIO_IN_net_0;
+assign GPIO_IN[11:11] = GPIO_IN_net_1[11];
+assign GPIO_IN_0_net_0[12] = GPIO_IN_0;
+assign GPIO_IN[12:12] = GPIO_IN_0_net_0[12];
+assign GPIO_IN_1_net_0[13] = GPIO_IN_1;
+assign GPIO_IN[13:13] = GPIO_IN_1_net_0[13];
+assign GPIO_IN_2_net_0[14] = GPIO_IN_2;
+assign GPIO_IN[14:14] = GPIO_IN_2_net_0[14];
+assign GPIO_IN_3_net_0[15] = GPIO_IN_3;
+assign GPIO_IN[15:15] = GPIO_IN_3_net_0[15];
+assign GPIO_IN_4_net_0[16] = GPIO_IN_4;
+assign GPIO_IN[16:16] = GPIO_IN_4_net_0[16];
+assign GPIO_IN_5_net_0[17] = GPIO_IN_5;
+assign GPIO_IN[17:17] = GPIO_IN_5_net_0[17];
+assign GPIO_IN_6_net_0[18] = GPIO_IN_6;
+assign GPIO_IN[18:18] = GPIO_IN_6_net_0[18];
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_slice_0[11] = GPIO_OE[11:11];
+assign GPIO_OE_slice_1[12] = GPIO_OE[12:12];
+assign GPIO_OE_slice_2[13] = GPIO_OE[13:13];
+assign GPIO_OE_slice_3[14] = GPIO_OE[14:14];
+assign GPIO_OE_slice_4[15] = GPIO_OE[15:15];
+assign GPIO_OE_slice_5[16] = GPIO_OE[16:16];
+assign GPIO_OE_slice_6[17] = GPIO_OE[17:17];
+assign GPIO_OE_slice_7[18] = GPIO_OE[18:18];
+assign GPIO_OUT_slice_0[11] = GPIO_OUT[11:11];
+assign GPIO_OUT_slice_1[12] = GPIO_OUT[12:12];
+assign GPIO_OUT_slice_2[13] = GPIO_OUT[13:13];
+assign GPIO_OUT_slice_3[14] = GPIO_OUT[14:14];
+assign GPIO_OUT_slice_4[15] = GPIO_OUT[15:15];
+assign GPIO_OUT_slice_5[16] = GPIO_OUT[16:16];
+assign GPIO_OUT_slice_6[17] = GPIO_OUT[17:17];
+assign GPIO_OUT_slice_7[18] = GPIO_OUT[18:18];
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------BIBUF
+BIBUF P9_11_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_0 ),
+ .E ( GPIO_OE_slice_0 ),
+ // Outputs
+ .Y ( GPIO_IN_net_0 ),
+ // Inouts
+ .PAD ( P9_11 )
+ );
+
+//--------BIBUF
+BIBUF P9_12_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_1 ),
+ .E ( GPIO_OE_slice_1 ),
+ // Outputs
+ .Y ( GPIO_IN_0 ),
+ // Inouts
+ .PAD ( P9_12 )
+ );
+
+//--------BIBUF
+BIBUF P9_13_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_2 ),
+ .E ( GPIO_OE_slice_2 ),
+ // Outputs
+ .Y ( GPIO_IN_1 ),
+ // Inouts
+ .PAD ( P9_13 )
+ );
+
+//--------BIBUF
+BIBUF P9_14_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_3 ),
+ .E ( GPIO_OE_slice_3 ),
+ // Outputs
+ .Y ( GPIO_IN_2 ),
+ // Inouts
+ .PAD ( P9_14 )
+ );
+
+//--------BIBUF
+BIBUF P9_15_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_4 ),
+ .E ( GPIO_OE_slice_4 ),
+ // Outputs
+ .Y ( GPIO_IN_3 ),
+ // Inouts
+ .PAD ( P9_15 )
+ );
+
+//--------BIBUF
+BIBUF P9_16_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_5 ),
+ .E ( GPIO_OE_slice_5 ),
+ // Outputs
+ .Y ( GPIO_IN_4 ),
+ // Inouts
+ .PAD ( P9_16 )
+ );
+
+//--------BIBUF
+BIBUF P9_17_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_6 ),
+ .E ( GPIO_OE_slice_6 ),
+ // Outputs
+ .Y ( GPIO_IN_5 ),
+ // Inouts
+ .PAD ( P9_17 )
+ );
+
+//--------BIBUF
+BIBUF P9_18_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_7 ),
+ .E ( GPIO_OE_slice_7 ),
+ // Outputs
+ .Y ( GPIO_IN_6 ),
+ // Inouts
+ .PAD ( P9_18 )
+ );
+
+
+endmodule
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v
new file mode 100644
index 0000000000000000000000000000000000000000..bb3671ed9bd860825436c684f6de0904dfe17d13
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_21_31_IOPADS.v
@@ -0,0 +1,287 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Sat Dec 2 16:38:15 2023
+// Version: 2022.3 2022.3.0.8
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// P9_21_31_IOPADS
+module P9_21_31_IOPADS(
+ // Inputs
+ GPIO_OE,
+ GPIO_OUT,
+ // Outputs
+ GPIO_IN,
+ // Inouts
+ P9_21,
+ P9_22,
+ P9_23,
+ P9_24,
+ P9_25,
+ P9_26,
+ P9_27,
+ P9_28,
+ P9_29,
+ P9_30,
+ P9_31
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input [31:21] GPIO_OE;
+input [31:21] GPIO_OUT;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [31:21] GPIO_IN;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout P9_21;
+inout P9_22;
+inout P9_23;
+inout P9_24;
+inout P9_25;
+inout P9_26;
+inout P9_27;
+inout P9_28;
+inout P9_29;
+inout P9_30;
+inout P9_31;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire GPIO_IN_net_0;
+wire GPIO_IN_0;
+wire GPIO_IN_1;
+wire GPIO_IN_2;
+wire GPIO_IN_3;
+wire GPIO_IN_4;
+wire GPIO_IN_5;
+wire GPIO_IN_6;
+wire GPIO_IN_7;
+wire GPIO_IN_8;
+wire GPIO_IN_9;
+wire [21:21] GPIO_OE_slice_0;
+wire [22:22] GPIO_OE_slice_1;
+wire [23:23] GPIO_OE_slice_2;
+wire [24:24] GPIO_OE_slice_3;
+wire [25:25] GPIO_OE_slice_4;
+wire [26:26] GPIO_OE_slice_5;
+wire [27:27] GPIO_OE_slice_6;
+wire [28:28] GPIO_OE_slice_7;
+wire [29:29] GPIO_OE_slice_8;
+wire [30:30] GPIO_OE_slice_9;
+wire [31:31] GPIO_OE_slice_10;
+wire [21:21] GPIO_OUT_slice_0;
+wire [22:22] GPIO_OUT_slice_1;
+wire [23:23] GPIO_OUT_slice_2;
+wire [24:24] GPIO_OUT_slice_3;
+wire [25:25] GPIO_OUT_slice_4;
+wire [26:26] GPIO_OUT_slice_5;
+wire [27:27] GPIO_OUT_slice_6;
+wire [28:28] GPIO_OUT_slice_7;
+wire [29:29] GPIO_OUT_slice_8;
+wire [30:30] GPIO_OUT_slice_9;
+wire [31:31] GPIO_OUT_slice_10;
+wire P9_21;
+wire P9_22;
+wire P9_23;
+wire P9_24;
+wire P9_25;
+wire P9_26;
+wire P9_27;
+wire P9_28;
+wire P9_29;
+wire P9_30;
+wire P9_31;
+wire [21:21] GPIO_IN_net_1;
+wire [22:22] GPIO_IN_0_net_0;
+wire [23:23] GPIO_IN_1_net_0;
+wire [24:24] GPIO_IN_2_net_0;
+wire [25:25] GPIO_IN_3_net_0;
+wire [26:26] GPIO_IN_4_net_0;
+wire [27:27] GPIO_IN_5_net_0;
+wire [28:28] GPIO_IN_6_net_0;
+wire [29:29] GPIO_IN_7_net_0;
+wire [30:30] GPIO_IN_8_net_0;
+wire [31:31] GPIO_IN_9_net_0;
+wire [31:21] GPIO_OUT;
+wire [31:21] GPIO_OE;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign GPIO_IN_net_1[21] = GPIO_IN_net_0;
+assign GPIO_IN[21:21] = GPIO_IN_net_1[21];
+assign GPIO_IN_0_net_0[22] = GPIO_IN_0;
+assign GPIO_IN[22:22] = GPIO_IN_0_net_0[22];
+assign GPIO_IN_1_net_0[23] = GPIO_IN_1;
+assign GPIO_IN[23:23] = GPIO_IN_1_net_0[23];
+assign GPIO_IN_2_net_0[24] = GPIO_IN_2;
+assign GPIO_IN[24:24] = GPIO_IN_2_net_0[24];
+assign GPIO_IN_3_net_0[25] = GPIO_IN_3;
+assign GPIO_IN[25:25] = GPIO_IN_3_net_0[25];
+assign GPIO_IN_4_net_0[26] = GPIO_IN_4;
+assign GPIO_IN[26:26] = GPIO_IN_4_net_0[26];
+assign GPIO_IN_5_net_0[27] = GPIO_IN_5;
+assign GPIO_IN[27:27] = GPIO_IN_5_net_0[27];
+assign GPIO_IN_6_net_0[28] = GPIO_IN_6;
+assign GPIO_IN[28:28] = GPIO_IN_6_net_0[28];
+assign GPIO_IN_7_net_0[29] = GPIO_IN_7;
+assign GPIO_IN[29:29] = GPIO_IN_7_net_0[29];
+assign GPIO_IN_8_net_0[30] = GPIO_IN_8;
+assign GPIO_IN[30:30] = GPIO_IN_8_net_0[30];
+assign GPIO_IN_9_net_0[31] = GPIO_IN_9;
+assign GPIO_IN[31:31] = GPIO_IN_9_net_0[31];
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_slice_0[21] = GPIO_OE[21:21];
+assign GPIO_OE_slice_1[22] = GPIO_OE[22:22];
+assign GPIO_OE_slice_2[23] = GPIO_OE[23:23];
+assign GPIO_OE_slice_3[24] = GPIO_OE[24:24];
+assign GPIO_OE_slice_4[25] = GPIO_OE[25:25];
+assign GPIO_OE_slice_5[26] = GPIO_OE[26:26];
+assign GPIO_OE_slice_6[27] = GPIO_OE[27:27];
+assign GPIO_OE_slice_7[28] = GPIO_OE[28:28];
+assign GPIO_OE_slice_8[29] = GPIO_OE[29:29];
+assign GPIO_OE_slice_9[30] = GPIO_OE[30:30];
+assign GPIO_OE_slice_10[31] = GPIO_OE[31:31];
+assign GPIO_OUT_slice_0[21] = GPIO_OUT[21:21];
+assign GPIO_OUT_slice_1[22] = GPIO_OUT[22:22];
+assign GPIO_OUT_slice_2[23] = GPIO_OUT[23:23];
+assign GPIO_OUT_slice_3[24] = GPIO_OUT[24:24];
+assign GPIO_OUT_slice_4[25] = GPIO_OUT[25:25];
+assign GPIO_OUT_slice_5[26] = GPIO_OUT[26:26];
+assign GPIO_OUT_slice_6[27] = GPIO_OUT[27:27];
+assign GPIO_OUT_slice_7[28] = GPIO_OUT[28:28];
+assign GPIO_OUT_slice_8[29] = GPIO_OUT[29:29];
+assign GPIO_OUT_slice_9[30] = GPIO_OUT[30:30];
+assign GPIO_OUT_slice_10[31] = GPIO_OUT[31:31];
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------BIBUF
+BIBUF P9_21_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_0 ),
+ .E ( GPIO_OE_slice_0 ),
+ // Outputs
+ .Y ( GPIO_IN_net_0 ),
+ // Inouts
+ .PAD ( P9_21 )
+ );
+
+//--------BIBUF
+BIBUF P9_22_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_1 ),
+ .E ( GPIO_OE_slice_1 ),
+ // Outputs
+ .Y ( GPIO_IN_0 ),
+ // Inouts
+ .PAD ( P9_22 )
+ );
+
+//--------BIBUF
+BIBUF P9_23_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_2 ),
+ .E ( GPIO_OE_slice_2 ),
+ // Outputs
+ .Y ( GPIO_IN_1 ),
+ // Inouts
+ .PAD ( P9_23 )
+ );
+
+//--------BIBUF
+BIBUF P9_24_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_3 ),
+ .E ( GPIO_OE_slice_3 ),
+ // Outputs
+ .Y ( GPIO_IN_2 ),
+ // Inouts
+ .PAD ( P9_24 )
+ );
+
+//--------BIBUF
+BIBUF P9_25_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_4 ),
+ .E ( GPIO_OE_slice_4 ),
+ // Outputs
+ .Y ( GPIO_IN_3 ),
+ // Inouts
+ .PAD ( P9_25 )
+ );
+
+//--------BIBUF
+BIBUF P9_26_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_5 ),
+ .E ( GPIO_OE_slice_5 ),
+ // Outputs
+ .Y ( GPIO_IN_4 ),
+ // Inouts
+ .PAD ( P9_26 )
+ );
+
+//--------BIBUF
+BIBUF P9_27_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_6 ),
+ .E ( GPIO_OE_slice_6 ),
+ // Outputs
+ .Y ( GPIO_IN_5 ),
+ // Inouts
+ .PAD ( P9_27 )
+ );
+
+//--------BIBUF
+BIBUF P9_28_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_7 ),
+ .E ( GPIO_OE_slice_7 ),
+ // Outputs
+ .Y ( GPIO_IN_6 ),
+ // Inouts
+ .PAD ( P9_28 )
+ );
+
+//--------BIBUF
+BIBUF P9_29_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_8 ),
+ .E ( GPIO_OE_slice_8 ),
+ // Outputs
+ .Y ( GPIO_IN_7 ),
+ // Inouts
+ .PAD ( P9_29 )
+ );
+
+//--------BIBUF
+BIBUF P9_30_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_9 ),
+ .E ( GPIO_OE_slice_9 ),
+ // Outputs
+ .Y ( GPIO_IN_8 ),
+ // Inouts
+ .PAD ( P9_30 )
+ );
+
+//--------BIBUF
+BIBUF P9_31_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_10 ),
+ .E ( GPIO_OE_slice_10 ),
+ // Outputs
+ .Y ( GPIO_IN_9 ),
+ // Inouts
+ .PAD ( P9_31 )
+ );
+
+
+endmodule
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v
new file mode 100644
index 0000000000000000000000000000000000000000..c8a5bf4f6967d0bdd376709a54fce9b7307c6b4f
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_41_42_IOPADS.v
@@ -0,0 +1,89 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Sat Dec 2 16:38:15 2023
+// Version: 2022.3 2022.3.0.8
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// P9_41_42_IOPADS
+module P9_41_42_IOPADS(
+ // Inputs
+ GPIO_OE,
+ GPIO_OUT,
+ // Outputs
+ GPIO_IN,
+ // Inouts
+ P9_41,
+ P9_42
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input [42:41] GPIO_OE;
+input [42:41] GPIO_OUT;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [42:41] GPIO_IN;
+//--------------------------------------------------------------------
+// Inout
+//--------------------------------------------------------------------
+inout P9_41;
+inout P9_42;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire GPIO_IN_net_0;
+wire GPIO_IN_0;
+wire [41:41] GPIO_OE_slice_0;
+wire [42:42] GPIO_OE_slice_1;
+wire [41:41] GPIO_OUT_slice_0;
+wire [42:42] GPIO_OUT_slice_1;
+wire P9_41;
+wire P9_42;
+wire [41:41] GPIO_IN_net_1;
+wire [42:42] GPIO_IN_0_net_0;
+wire [42:41] GPIO_OUT;
+wire [42:41] GPIO_OE;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign GPIO_IN_net_1[41] = GPIO_IN_net_0;
+assign GPIO_IN[41:41] = GPIO_IN_net_1[41];
+assign GPIO_IN_0_net_0[42] = GPIO_IN_0;
+assign GPIO_IN[42:42] = GPIO_IN_0_net_0[42];
+//--------------------------------------------------------------------
+// Slices assignments
+//--------------------------------------------------------------------
+assign GPIO_OE_slice_0[41] = GPIO_OE[41:41];
+assign GPIO_OE_slice_1[42] = GPIO_OE[42:42];
+assign GPIO_OUT_slice_0[41] = GPIO_OUT[41:41];
+assign GPIO_OUT_slice_1[42] = GPIO_OUT[42:42];
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------BIBUF
+BIBUF P9_41_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_0 ),
+ .E ( GPIO_OE_slice_0 ),
+ // Outputs
+ .Y ( GPIO_IN_net_0 ),
+ // Inouts
+ .PAD ( P9_41 )
+ );
+
+//--------BIBUF
+BIBUF P9_42_BIBUF(
+ // Inputs
+ .D ( GPIO_OUT_slice_1 ),
+ .E ( GPIO_OE_slice_1 ),
+ // Outputs
+ .Y ( GPIO_IN_0 ),
+ // Inouts
+ .PAD ( P9_42 )
+ );
+
+
+endmodule
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v
new file mode 100644
index 0000000000000000000000000000000000000000..f6e0b082dcfb6282a1303198b8c16cb25bd70037
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v
@@ -0,0 +1,73 @@
+`timescale 1ns/100ps
+module apb_ctrl_status(
+ input pclk,
+ input presetn,
+ input penable,
+ input psel,
+ input [7:0] paddr,
+ input pwrite,
+ input [31:0] pwdata,
+ output reg [31:0] prdata,
+ output reg [31:0] control,
+ input [31:0] status
+ );
+
+
+ localparam [7:0] STATUS = 8'h20; // READ-ONLY REGISTER
+ localparam [7:0] CONTROL_1 = 8'h10; // READ/WRITE Register
+ localparam [7:0] CONTROL_0 = 8'h00; // READ_ONLY DEADBEEF REGISTER
+
+ reg [31:0] control_value;
+
+ wire rd_enable;
+ wire wr_enable;
+
+ assign wr_enable = (penable && pwrite && psel);
+ assign rd_enable = (!pwrite && psel);
+
+ always@(posedge pclk or negedge presetn)
+ begin
+ if(~presetn)
+ begin
+ prdata <= 'b0;
+ control_value <= 32'h00000000;
+ control <= 32'h00000000;
+ end
+ else
+ begin
+ case(paddr[7:0])
+ STATUS:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= status;
+ end
+ end
+ CONTROL_0:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= 32'hdeadbeef;
+ control <= 32'hdeadbeef;
+ end
+ end
+ CONTROL_1:
+ begin
+ if (rd_enable)
+ begin
+ prdata <= control_value;
+ control <= control_value;
+ end
+ else if (wr_enable)
+ begin
+ control_value <= pwdata;
+ end
+ end
+ default:
+ begin
+ prdata <= 32'b0;
+ end
+ endcase
+ end
+ end
+endmodule
\ No newline at end of file
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v
new file mode 100644
index 0000000000000000000000000000000000000000..a4022c353ad3d6b1e0186df578e81fe0183e76a4
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v
@@ -0,0 +1,24 @@
+`timescale 1ns/100ps
+module blinky(
+input clk,
+input resetn,
+output blink
+);
+
+
+reg [22:0] counter;
+
+assign blink = counter[22];
+
+always@(posedge clk or negedge resetn)
+begin
+ if(~resetn)
+ begin
+ counter <= 23'h0;
+ end
+ else
+ begin
+ counter <= counter + 23'b1;
+ end
+end
+endmodule
\ No newline at end of file
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/constraints/cape.pdc b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/constraints/cape.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..852c7827cddfa9911e5dda4f9b502cfe209500ea
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/constraints/cape.pdc
@@ -0,0 +1,419 @@
+
+set_io -port_name P9_11 \
+ -pin_name B5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_12 \
+ -pin_name C5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_13 \
+ -pin_name D19 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_14 \
+ -pin_name C6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUT
+
+set_io -port_name P9_15 \
+ -pin_name A5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_16 \
+ -pin_name A6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUT
+
+set_io -port_name P9_17 \
+ -pin_name C9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUT
+
+set_io -port_name P9_18 \
+ -pin_name C10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUT
+
+set_io -port_name P9_21 \
+ -pin_name B8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_22 \
+ -pin_name A8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_23 \
+ -pin_name C12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_24 \
+ -pin_name B12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_25 \
+ -pin_name B7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_26 \
+ -pin_name A7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_27 \
+ -pin_name D11 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+set_io -port_name P9_28 \
+ -pin_name C11 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+set_io -port_name P9_29 \
+ -pin_name F17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+set_io -port_name P9_30 \
+ -pin_name F16 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_31 \
+ -pin_name E18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_41 \
+ -pin_name E15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_42 \
+ -pin_name E14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+#-------------------------------------------------------------------------------
+
+set_io -port_name P8_3 \
+ -pin_name V22 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_4 \
+ -pin_name W22 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_5 \
+ -pin_name V19 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_6 \
+ -pin_name V20 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_7 \
+ -pin_name V15 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_8 \
+ -pin_name V14 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_9 \
+ -pin_name V21 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_10 \
+ -pin_name W21 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_11 \
+ -pin_name Y21 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_12 \
+ -pin_name Y20 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_13 \
+ -pin_name B10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_14 \
+ -pin_name B9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+
+set_io -port_name P8_15 \
+ -pin_name T12 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_16 \
+ -pin_name U12 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_17 \
+ -pin_name W13 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_18 \
+ -pin_name T16 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_19 \
+ -pin_name W18 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_20 \
+ -pin_name R16 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_21 \
+ -pin_name AA21 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_22 \
+ -pin_name AA22 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_23 \
+ -pin_name AB18 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_24 \
+ -pin_name AA18 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_25 \
+ -pin_name V17 \
+ -fixed true \
+ -OUT_DRIVE 12 \
+ -RES_PULL None \
+ -DIRECTION INOUT
+
+set_io -port_name P8_26 \
+ -pin_name A12 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_27 \
+ -pin_name A13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_28 \
+ -pin_name B14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_29 \
+ -pin_name B13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_30 \
+ -pin_name D14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_31 \
+ -pin_name D13 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_32 \
+ -pin_name B15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_33 \
+ -pin_name A15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+set_io -port_name P8_34 \
+ -pin_name C15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_35 \
+ -pin_name C14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INPUT
+
+set_io -port_name P8_36 \
+ -pin_name B4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_37 \
+ -pin_name C4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_38 \
+ -pin_name C17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_39 \
+ -pin_name B17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_40 \
+ -pin_name B18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_41 \
+ -pin_name A18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_42 \
+ -pin_name D6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_43 \
+ -pin_name D7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_44 \
+ -pin_name D8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_45 \
+ -pin_name D9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_46 \
+ -pin_name D18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/leds.dtso b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/leds.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..56551e989ee521f60fc170154dae849bbdadd7fc
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/leds.dtso
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ leds {
+ compatible = "gpio-leds";
+
+ led_P8_03 {
+ status = "okay";
+ gpios = <&gpio2 0 0>;
+ default-state = "on";
+ };
+
+ led_P8_04 {
+ status = "okay";
+ gpios = <&gpio2 1 0>;
+ default-state = "on";
+ };
+
+ led_P8_05 {
+ status = "okay";
+ gpios = <&gpio2 2 0>;
+ default-state = "on";
+ };
+
+ led_P8_06 {
+ status = "okay";
+ gpios = <&gpio2 3 0>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+
+ led_P8_07 {
+ status = "okay";
+ gpios = <&gpio2 4 0>;
+ default-state = "off";
+ };
+
+ led_P8_08 {
+ status = "okay";
+ gpios = <&gpio2 5 0>;
+ default-state = "off";
+ };
+
+ led_P8_09 {
+ status = "okay";
+ gpios = <&gpio2 6 0>;
+ default-state = "off";
+ };
+
+ led_P8_10 {
+ status = "okay";
+ gpios = <&gpio2 7 0>;
+ default-state = "off";
+ };
+
+ led_P8_11 {
+ status = "okay";
+ gpios = <&gpio2 8 0>;
+ default-state = "off";
+ };
+
+ led_P8_12 {
+ status = "okay";
+ gpios = <&gpio2 9 0>;
+ default-state = "off";
+ };
+
+ led_P8_13 {
+ status = "okay";
+ gpios = <&gpio2 10 0>;
+ default-state = "off";
+ };
+
+ led_P8_14 {
+ status = "okay";
+ gpios = <&gpio2 11 0>;
+ default-state = "off";
+ };
+ };
+};
diff --git a/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/verilog-cape.dtso b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/verilog-cape.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..981def927c17e4e8303bc237c12a1cf3aae96ab0
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/device-tree-overlay/verilog-cape.dtso
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2023 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+ overlays {
+ MY-LOVELY-CAPE-GATEWARE = "GATEWARE_GIT_VERSION";
+ };
+};
+
+&{/fabric-bus@40000000} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cape_gpios_p8: gpio@41100000 {
+ compatible = "microchip,core-gpio", "microchip,coregpio-rtl-v3";
+ reg = <0x0 0x41100000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ status = "okay";
+ interrupts = <129>, <130>, <131>, <132>,
+ <133>, <134>, <135>, <136>,
+ <137>, <138>, <139>, <140>,
+ <141>, <142>, <143>, <144>;
+
+ gpio-line-names = "P8_31", "P8_32", "", "P8_34",
+ "", "P8_36", "P8_37", "P8_38",
+ "P8_39", "P8_40", "P8_41", "P8_42",
+ "P8_43", "P8_44", "P8_45", "P8_46";
+ };
+};