diff --git a/accessories/cables.rst b/accessories/cables.rst
index 3b5158f0b2b065a59e7a4b2d028ebe4dc7fccb07..3c6f678ec20edd0ae0df378d54cc193e69500ce8 100644
--- a/accessories/cables.rst
+++ b/accessories/cables.rst
@@ -155,12 +155,49 @@ JTAG debug Cables
TagConnect (JTAG)
==================
-Boards like :ref:`beagleconnect_freedom_home` and :ref:`beagleplay-home` use the TagConnect
-interface which allows you to perform firmware updates and JTAG hardware debugging. To use the
-interface, the the parts below from `tag-connect <https://www.tag-connect.com>`_ are required.
+Boards like :ref:`beagleconnect_freedom_home`, :ref:`beaglev-ahead-home`, :ref:`beaglev-fire-home`, and :ref:`beagleplay-home` use the TagConnect
+interface which allows you to perform firmware updates and JTAG hardware debugging. To use the interface, the the parts below from
+`tag-connect <https://www.tag-connect.com>`_ are required.
-1. `10pin TagConnect (no legs) ribbon cable. <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with-ribbon-connector>`_
-2. `TagConnect retaining clip. <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+.. note::
+ You need both the cable and the retaining clip to properly use/connect the cable with the boards.
+ There is an option to 3D print protective cap and retaining cap which you can try.
+
+TC2050 debug cable
+-------------------
+
+.. image:: images/tc2050-idc-nl-10-pin-debug-cable.jpg
+ :align: center
+ :width: 420
+ :alt: TC2050 10pin debug cable
+
+1. `TC2050 cable (tag-connect.com) <https://www.tag-connect.com/product/tc2050-idc-nl-10-pin-no-legs-cable-with-ribbon-connector>`_
+2. `TC2050 cable (DigiKey) <https://www.digikey.com/en/products/detail/tag-connect-llc/TC2050-IDC-NL/2605367>`_
+
+
+
+TC2050 retaining clip
+----------------------
+
+.. image:: images/TC2050-CLIP.jpg
+ :align: center
+ :width: 420
+ :alt: TC2050 retaining clip
+
+1. `TC2050 retaining clip (tag-connect.com) <https://www.tag-connect.com/product/tc2050-clip-3pack-retaining-clip>`_
+2. `TC2050 retaining clip (DigiKey) <https://www.digikey.com/en/products/detail/tag-connect-llc/TC2050-CLIP-3PACK/12318009>`_
+
+3D printable cap & clip (Optional)
+-----------------------------------
+
+.. image:: images/TC2050-protective-cap.jpg
+ :align: center
+ :width: 420
+ :alt: 3D printable TC2050 protective cap
+
+
+1. `Protective cap (Thingiverse) <https://www.thingiverse.com/thing:3025584>`_
+2. `Retaining clip (Thingiverse) <https://www.thingiverse.com/thing:3035278>`_
HDMI Cables
diff --git a/accessories/images/TC2050-CLIP.jpg b/accessories/images/TC2050-CLIP.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..361b838b853faf3fe0aa91e24d277d32f2d9e8e5
Binary files /dev/null and b/accessories/images/TC2050-CLIP.jpg differ
diff --git a/accessories/images/TC2050-protective-cap.jpg b/accessories/images/TC2050-protective-cap.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..78513c26d9b676965c9cf8d0dc873b7c93f5a08c
Binary files /dev/null and b/accessories/images/TC2050-protective-cap.jpg differ
diff --git a/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg b/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..c9dd86cb951fd0b048c4b56e6f4982b7a1ae6ceb
Binary files /dev/null and b/accessories/images/tc2050-idc-nl-10-pin-debug-cable.jpg differ
diff --git a/boards/beagleplay/demos-and-tutorials/boot/install-emmc.sh b/boards/beagleplay/demos-and-tutorials/boot/install-emmc.sh
new file mode 100644
index 0000000000000000000000000000000000000000..8ac53c3f5b693ea90a727f894e042b1618391c18
--- /dev/null
+++ b/boards/beagleplay/demos-and-tutorials/boot/install-emmc.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+
+if ! id | grep -q root; then
+ echo "must be run as root"
+ exit
+fi
+
+wdir="/opt/u-boot/bb-u-boot-beagleplay"
+
+if [ -b /dev/mmcblk0 ] ; then
+ #mmc extcsd read /dev/mmcblk0
+ mmc bootpart enable 1 2 /dev/mmcblk0
+ mmc bootbus set single_backward x1 x8 /dev/mmcblk0
+ mmc hwreset enable /dev/mmcblk0
+
+ echo "Clearing eMMC boot0"
+
+ echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
+
+ echo "dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k"
+ dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
+
+ echo "dd if=${wdir}/tiboot3.bin of=/dev/mmcblk0boot0 bs=128k"
+ dd if=${wdir}/tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
+fi
diff --git a/boards/beagleplay/demos-and-tutorials/play-kernel-development.rst b/boards/beagleplay/demos-and-tutorials/play-kernel-development.rst
index ec96e970013a96a15b6efe1ad7764f53ab9fc1ab..f74d9b3977971608852b48bfb981e2b34ad4b775 100644
--- a/boards/beagleplay/demos-and-tutorials/play-kernel-development.rst
+++ b/boards/beagleplay/demos-and-tutorials/play-kernel-development.rst
@@ -114,9 +114,12 @@ Installing and Booting the Kernel
See :ref:`beagleplay-serial-console` to setup access over the debug serial port.
+.. _play-dpkg-install-kernel:
+
.. code-block:: bash
+ :caption: Install 6.6.0 kernel and reboot
- sudo dpkg -i linux-image-6.6.0_1xross_arm64.deb linux-libc-dev_1xross_arm64.deb
+ sudo dpkg -i linux-image-6.6.0_1xross_arm64.deb
sudo shutdown -r now
As long as the kernel you built has no significant issues, you'll boot back into a
diff --git a/boards/beagleplay/demos-and-tutorials/understanding-boot.rst b/boards/beagleplay/demos-and-tutorials/understanding-boot.rst
index d141408906a6d5504ee64c1fec0fd926142e169e..04dc6520eb7005ef8a33777d8e32a73d0651bc4b 100644
--- a/boards/beagleplay/demos-and-tutorials/understanding-boot.rst
+++ b/boards/beagleplay/demos-and-tutorials/understanding-boot.rst
@@ -19,3 +19,150 @@ Distro Boot
For some background on distro boot, see `the u-boot documentation on
distro boot <https://docs.u-boot.org/en/latest/develop/distro.html>`_.
+
+In :ref:`play-typical-extlinux-conf`, you can see line 1 provides a label
+and subsequent indented lines provide parameters for that boot option.
+
+.. _play-typical-extlinux-conf:
+
+.. code-block::
+ :caption: Typical /boot/firmware/extlinux/extlinux.conf file
+ :linenos:
+
+ label Linux eMMC
+ kernel /Image
+ append root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait net.ifnames=0 quiet
+ fdtdir /
+ #fdtoverlays /overlays/<file>.dtbo
+ initrd /initrd.img
+
+It is important to note that this file is not on the root file system of BeaglePlay. It
+is sitting on a separate FAT32 partition that is mounted at ``/boot/firmware``. You can
+see the mounted file systems and their formats in :ref:`play-boot-mounted-fs`.
+
+The FAT32 partition in this setup is often referred to as the boot file system.
+
+.. _play-boot-mounted-fs:
+
+.. code-block:: shell-session
+ :caption: List of mounted file systems
+
+ debian@BeaglePlay:~$ df
+ Filesystem 1K-blocks Used Available Use% Mounted on
+ udev 903276 0 903276 0% /dev
+ tmpfs 197324 1524 195800 1% /run
+ /dev/mmcblk0p2 14833640 12144024 1914296 87% /
+ tmpfs 986608 0 986608 0% /dev/shm
+ tmpfs 5120 4 5116 1% /run/lock
+ /dev/mmcblk0p1 130798 53214 77584 41% /boot/firmware
+ tmpfs 197320 32 197288 1% /run/user/1000
+ debian@BeaglePlay:~$ lsblk
+ NAME MAJ:MIN RM SIZE RO TYPE MOUNTPOINT
+ mmcblk0 179:0 0 14.6G 0 disk
+ ├─mmcblk0p1 179:1 0 128M 0 part /boot/firmware
+ └─mmcblk0p2 179:2 0 14.5G 0 part /
+ mmcblk0boot0 179:256 0 4M 1 disk
+ mmcblk0boot1 179:512 0 4M 1 disk
+ debian@BeaglePlay:~$ sudo sfdisk -l /dev/mmcblk0
+ Disk /dev/mmcblk0: 14.6 GiB, 15678308352 bytes, 30621696 sectors
+ Units: sectors of 1 * 512 = 512 bytes
+ Sector size (logical/physical): 512 bytes / 512 bytes
+ I/O size (minimum/optimal): 512 bytes / 512 bytes
+ Disklabel type: dos
+ Disk identifier: 0xba67172a
+
+ Device Boot Start End Sectors Size Id Type
+ /dev/mmcblk0p1 * 2048 264191 262144 128M c W95 FAT32 (LBA)
+ /dev/mmcblk0p2 264192 30621695 30357504 14.5G 83 Linux
+
+
+To better understand BeaglePlay's U-Boot Distro Boot, let's install the kernel image
+we made in :ref:`play-kernel-development`. To do this, we need to have an uncompressed
+version of the kernel in the FAT32 file system and a ramdisk image we plan to use. The
+ramdisk image is utilized to make sure any kernel modules needed are available and to
+provide a bit of a recovery opportunity in case the root file system is corrupted. You
+can learn more about initrd on `the Debian Initrd Wiki page <https://wiki.debian.org/Initrd>`
+and `the Linux kernel documentation admin guide initrd
+entry <https://docs.kernel.org/admin-guide/initrd.html>`.
+
+In :ref:`play-copy-kernel`, we perform a copy of the kernel that was installed via
+:ref:`play-dpkg-install-kernel` and then reverted with ...
+
+.. todo::
+
+ Put the step into play-kernel-development.rst to revert back to the Beagle kernel.
+
+The contents of the initrd can be read using ``lsinitramfs /boot/firmware/initrd.img-6.6.0``.
+
+.. _play-copy-kernel:
+
+.. code-block:: shell-session
+ :caption: Copy kernel to FAT32 filesystem
+
+ debian@BeaglePlay:~$ sudo cp /boot/vmlinuz-6.6.0 /boot/firmware/Image-6.6.gz
+ [sudo] password for debian:
+ debian@BeaglePlay:~$ sudo gunzip /boot/firmware/Image-6.6.gz
+ debian@BeaglePlay:~$ sudo cp /boot/initrd.img-6.6.0 /boot/firmware/
+
+.. _play-modified-extlinux-conf:
+
+.. code-block::
+ :caption: Modified /boot/firmware/extlinux/extlinux.conf file
+ :linenos:
+
+ menu title Select image to boot
+ timeout 30
+ default Linux 6.6
+
+ label Linux default
+ kernel /Image
+ append root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait net.ifnames=0 quiet
+ fdtdir /
+ #fdtoverlays /overlays/<file>.dtbo
+ initrd /initrd.img
+
+ label Linux 6.6
+ kernel /Image-6.6
+ append root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait net.ifnames=0 quiet
+ fdtdir /
+ initrd /initrd.img-6.6.0
+
+.. _play-boot-modified-kernel:
+
+.. code-block:: shell-session
+ :caption: Reboot into modified kernel
+
+ debian@BeaglePlay:~$ sudo shutdown -r now
+ Connection to 192.168.0.117 closed by remote host.
+ Connection to 192.168.0.117 closed.
+ jkridner@slotcar:~$ ssh -Y debian@192.168.0.117
+ Debian GNU/Linux 11
+
+ BeagleBoard.org Debian Bullseye Xfce Image 2023-05-18
+ Support: https://bbb.io/debian
+ default username:password is [debian:temppwd]
+
+ debian@192.168.0.117's password:
+
+ The programs included with the Debian GNU/Linux system are free software;
+ the exact distribution terms for each program are described in the
+ individual files in /usr/share/doc/\*/copyright.
+
+ Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
+ permitted by applicable law.
+ Last login: Tue Dec 12 15:33:21 2023 from 192.168.0.171
+ debian@BeaglePlay:~$ uname -a
+ Linux BeaglePlay 6.6.0 #4 SMP Tue Dec 5 13:50:59 UTC 2023 aarch64 GNU/Linux
+
+
+Booting U-Boot
+**************
+
+.. _play-boot-install-emmc:
+
+.. literalinclude:: boot/install-emmc.sh
+ :caption: Install bootloader to eMMC
+ :language: bash
+
+:download:`install-emmc.sh <boot/install-emmc.sh>`
+
diff --git a/boards/beaglev/ahead/04-expansion.rst b/boards/beaglev/ahead/04-expansion.rst
index 009f0ab064a8717bc4957f9e773c375a7c20ea82..b7c04143e0dd63d042e8b7d8c585eb12a9948ae6 100644
--- a/boards/beaglev/ahead/04-expansion.rst
+++ b/boards/beaglev/ahead/04-expansion.rst
@@ -482,7 +482,7 @@ The **GPIO** row is the expected gpio identifier number in the Linux
kernel.
Each row includes the gpiochipX and pinY in the format of
-`X Y`. You can use these values to direcly control the GPIO pins with the
+`X Y`. You can use these values to directly control the GPIO pins with the
commands shown below.
.. code:: bash
diff --git a/boards/beaglev/fire/05-demos.rst b/boards/beaglev/fire/05-demos.rst
index c318c38ca1cfd58905562383f2583d855daf2092..52a0c62c4094a140b6e5006c816742b27fcf7766 100644
--- a/boards/beaglev/fire/05-demos.rst
+++ b/boards/beaglev/fire/05-demos.rst
@@ -20,3 +20,4 @@ Demos
demos-and-tutorials/gateware/how-to-find-out-whats-on-the-board
demos-and-tutorials/gateware/gateware-full-flow
demos-and-tutorials/gateware/gateware-tcl-scripts-structure
+ demos-and-tutorials/gateware/customize-cape-gateware-verilog
diff --git a/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst b/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst
index a607ff097738e5415f625321f33ee343d9d78670..43554b4c4276f446c1b934f772894e00aa4213e0 100644
--- a/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst
+++ b/boards/beaglev/fire/demos-and-tutorials/gateware/customize-cape-gateware-verilog.rst
@@ -1,4 +1,4 @@
-
+.. _beaglev-fire-customize-cape-gateware-verilog:
Customize BeagleV-Fire Cape Gateware Using Verilog
###################################################
@@ -14,7 +14,6 @@ It will describe:
- How to use the git.beagleboard.org CI infrastruture to generate programming bitstreams for your custom gateware
-
Steps:
1. Fork BeagleV-Fire gateware repository on git.beagleboard.org
@@ -31,24 +30,34 @@ Fork BeagleV-Fire Gateware Repository
Navigate to BeagleV-Fire's `gateware source code repository <https://git.beagleboard.org/beaglev-fire/gateware>`_.
-Click on the **Forks** button on the top-right corner.
+Click on the ``Forks`` button on the top-right corner.
.. figure:: media/gateware-beaglev-fire-fork.png
:align: center
+ :width: 1040
+ :alt: BeagleV-Fire gateware repo fork button
+
+ BeagleV-Fire gateware repo fork button
-On the Fork Project page, select your namespace
-and adjust the project name to help you manage multiple custom gateware (e.g. my-lovely-gateware).
-Click the **Fork project** button.
+On the Fork Project page, select your namespace and adjust the project name to help you manage multiple
+custom gateware (e.g. ``my-lovely-gateware``). Click the ``Fork project`` button.
.. figure:: media/verilog-gateware-fork.png
:align: center
+ :width: 1040
+ :alt: Create gateware fork
-Clone the forked repository::
+ Create gateware fork
- git clone git@git.beagleboard.org:<MY-NAMESPACE>>/my-lovely-gateware.git
+Clone the forked repository
+===========================
-Where <MY-NAMESPACE> is your Gitlab user space/user name.
+.. code-block:: shell
+
+ git clone git@git.beagleboard.org:<MY-NAMESPACE>/my-lovely-gateware.git
+
+Where ``<MY-NAMESPACE>`` is your Gitlab username or namespace.
Create A Custom Gateware Build Option
**************************************
@@ -56,15 +65,15 @@ Create A Custom Gateware Build Option
BeagleV-Fire's gateware build system uses "build configuration" YAML files to describe the combination
of gateware components options that will be used to build the gateware programming bitstream. You need
to create one such file to describe to the gateware build system that you want your own custom gateware
-to be built. You need to have one such file describing your gateware in directory **custom-fpga-design**.
+to be built. You need to have one such file describing your gateware in directory ``custom-fpga-design``.
-Let's modify the **./custom-fpga-design/my_custom_fpga_design.yaml** build configuration file to
+Let's modify the ``./custom-fpga-design/my_custom_fpga_design.yaml`` build configuration file to
specify that your custom cape gateware should be included in the gateware bitstream. In this instance will
-call our custom cape gateware MY_LOVELY_CAPE.
+call our custom cape gateware ``MY_LOVELY_CAPE``.
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: yaml
HSS:
type: git
@@ -80,24 +89,34 @@ call our custom cape gateware MY_LOVELY_CAPE.
<1> On the gateware build-args line, replace VERILOG_TUTORIAL with MY_LOVELY_CAPE.
-Note: The **custom-fpga-design** directory has a special meaning for the Beagleboard Gitlab CI system.
-Any build configuration found in this directory will be built by the CI system. This allows generating
-FPGA programming bitstreams without the requirement for having the Microchip FPGA toolchain installed
-on your computer.
+.. note::
+ The **custom-fpga-design** directory has a special meaning for the Beagleboard Gitlab CI system.
+ Any build configuration found in this directory will be built by the CI system. This allows generating
+ FPGA programming bitstreams without the requirement for having the Microchip FPGA toolchain installed
+ on your computer.
Rename A Copy Of The Cape Gateware Verilog Template
****************************************************
-Move to the cape gateware source code::
+Move to the cape gateware source code
+=====================================
+
+.. code-block:: shell
cd my-lovely-gateware/sources/FPGA-design/script_support/components/CAPE
-Create a directory that will contain your custom cape gateware source code::
+Create a directory that will contain your custom cape gateware source code
+===========================================================================
+
+.. code-block:: shell
mkdir MY_LOVELY_CAPE
-Copy the cape Verilog template::
+Copy the cape Verilog template
+===============================
+
+.. code-block:: shell
cp -r VERILOG_TEMPLATE/* ./MY_LOVELY_CAPE/
@@ -105,20 +124,23 @@ Copy the cape Verilog template::
Customize The Cape's Verilog Source Code
*****************************************
-Move to your custom gateware source directory:
+Move to your custom gateware source directory
+=============================================
+
+.. code-block:: shell
cd MY_LOVELY_CAPE
-You will need to first edit the ADD_CAPE.tcl TCL script to use your source code within your custom
+You will need to first edit the ``ADD_CAPE.tcl`` TCL script to use your source code within your custom
gateware directory and not the Verilog template source code. In this example this means using source
-code within the MY_LOVELY_CAPE directory rather the VERILOG_TEMPLATE directory.
+code within the ``MY_LOVELY_CAPE`` directory rather the VERILOG_TEMPLATE directory.
Edit ADD_CAPE.tcl
==================
-Replace VERILOG_TEMPLATE with MY_LOVELY_CAPE in file ADD_CAPE.tcl.
+Replace ``VERILOG_TEMPLATE`` with ``MY_LOVELY_CAPE`` in file ``ADD_CAPE.tcl``.
-.. code-block::
+.. code-block:: tcl
#-------------------------------------------------------------------------------
# Import HDL source files
@@ -132,14 +154,14 @@ Replace VERILOG_TEMPLATE with MY_LOVELY_CAPE in file ADD_CAPE.tcl.
Add the path to your additional Verilog source code files.
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: tcl
#-------------------------------------------------------------------------------
# Import HDL source files
#-------------------------------------------------------------------------------
- import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v} # <1>
+ import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/blinky.v} // <1>
import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/apb_ctrl_status.v}
import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P8_IOPADS.v}
import_files -hdl_source {script_support/components/CAPE/MY_LOVELY_CAPE/HDL/P9_11_18_IOPADS.v}
@@ -151,16 +173,16 @@ Add the path to your additional Verilog source code files.
<1> In our case we will be adding a new Verilog source file called blinky.v.
-You will only need to revisit the content of ADD_CAPE.tcl if you want to add more Verilog source files
+You will only need to revisit the content of ``ADD_CAPE.tcl`` if you want to add more Verilog source files
or want to modify how the cape interfaces with the rest of the gateware (RISC-V processor subsystem,
clock and reset blocks).
Customize The Cape's Verilog source code
=========================================
-We will add a simple Verilog source file, blinky.v, in the MY_LOVELY_CAPE directory. Code below:
+We will add a simple Verilog source file, ``blinky.v``, in the ``MY_LOVELY_CAPE`` directory. Code below:
-.. code-block::
+.. code-block:: verilog
`timescale 1ns/100ps
module blinky(
@@ -187,13 +209,13 @@ We will add a simple Verilog source file, blinky.v, in the MY_LOVELY_CAPE direct
end
endmodule
-Let's connect the blinky Verilog module within the cape by editing the CAPE.v file.
+Let's connect the blinky Verilog module within the cape by editing the ``CAPE.v`` file.
Add the instantiation of the blinky module:
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: devicetree
//--------P9_41_42_IOPADS
P9_41_42_IOPADS P9_41_42_IOPADS_0(
@@ -208,10 +230,10 @@ Add the instantiation of the blinky module:
);
//--------blinky
- blinky blinky_0( # <1>
- .clk ( PCLK ), # <2>
- .resetn ( PRESETN ), # <3>
- .blink ( BLINK ) # <4>
+ blinky blinky_0( // <1>
+ .clk ( PCLK ), // <2>
+ .resetn ( PRESETN ), // <3>
+ .blink ( BLINK ) // <4>
);
endmodule
@@ -228,13 +250,13 @@ Add the instantiation of the blinky module:
Add the BLINK wire:
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: verilog
wire PCLK;
wire PRESETN;
- wire BLINK; # <1>
+ wire BLINK; // <1>
wire [31:0] APB_SLAVE_PRDATA_net_0;
wire [27:0] GPIO_IN_net_1;
@@ -252,25 +274,25 @@ The original code populates two 43 bits wide wires for controlling the output-en
values of the P8 cape connector I/Os. The bottom 28 bits being controlled by the microprocessor
subsystem's GPIO block.
- .. code-block::
+ .. code-block:: verilog
- //--------------------------------------------------------------------
- // Concatenation assignments
- //--------------------------------------------------------------------
- assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE };
- assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT };
+ //--------------------------------------------------------------------
+ // Concatenation assignments
+ //--------------------------------------------------------------------
+ assign GPIO_OE_net_0 = { 16'h0000 , GPIO_OE };
+ assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT };
We are going to hijack the 6th I/O with our blinky's output:
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: verilog
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
- assign GPIO_OE_net_0 = { 16'h0000, GPIO_OE[27:6], 1'b1, GPIO_OE[4:0] }; # <1>
- assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:6], BLINK, GPIO_OUT[4:0] }; # <2>
+ assign GPIO_OE_net_0 = { 16'h0000, GPIO_OE[27:6], 1'b1, GPIO_OE[4:0] }; // <1>
+ assign GPIO_OUT_net_0 = { 16'h0000 , GPIO_OUT[27:6], BLINK, GPIO_OUT[4:0] }; // <2>
.. annotations::
@@ -286,16 +308,16 @@ You should always have a device tree overlay associated with your gateware even
control from Linux. The device tree overlay is very useful to identify which gateware is currently
programmed on your BeagleV-Fire.
-..callout::
+.. callout::
- .. code-block::
+ .. code-block:: devicetree
/dts-v1/;
/plugin/;
&{/chosen} {
overlays {
- MY-LOVELY-CAPE-GATEWARE = "GATEWARE_GIT_VERSION"; # <1>
+ MY-LOVELY-CAPE-GATEWARE = "GATEWARE_GIT_VERSION"; // <1>
};
};
@@ -303,7 +325,7 @@ programmed on your BeagleV-Fire.
<1> Replace VERILOG-CAPE-GATEWARE with MY-LOVELY-CAPE-GATEWARE.
-This change will result in MY-LOVELY-CAPE-GATEWARE being visible in /proc/device-tree/chosen/overlays
+This change will result in ``MY-LOVELY-CAPE-GATEWARE`` being visible in ``/proc/device-tree/chosen/overlays``
at run-time, allowing to check that my lovely gateware is successfully programmed on BeagleV-Fire.
@@ -312,16 +334,22 @@ Commit And Push Changes To Your Forked Repository
Move back up to the root directory of your gateware project. This is the my-lovely-gateware directory in our current example.
-Add the my-lovely-gateware/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE directory content to your git repository.
+Add the ``my-lovely-gateware/sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE`` directory content to your git repository.
+
+.. code:: shell
git add sources/FPGA-design/script_support/components/CAPE/MY_LOVELY_CAPE/
-Commit changes to my-lovely-gateware/custom-fpga-design/my_custom_fpga_design.yaml
+Commit changes to ``my-lovely-gateware/custom-fpga-design/my_custom_fpga_design.yaml``
+
+.. code:: shell
git commit -m "Add my lovely gateware."
Push changes to your beagleboard Gitlab repository:
+.. code:: shell
+
git push
@@ -329,28 +357,37 @@ Retrieve The Forked Repositories Artifacts
*******************************************
Navigate to your forked repository. Click Pipelines in the left pane then the Download Artifacts
-button on the right handside. Select build-job:archive. This will result in an artifacts.zip file
+button on the right handside. Select ``build-job:archive``. This will result in an ``artifacts.zip`` file
being downloaded.
.. figure:: media/gateware-pipeline.png
:align: center
+ :width: 1040
+ :alt: gateware pipeline
+
+ gateware pipeline
Program BeagleV-Fire With Your Custom Bitstream
************************************************
-Unzip the downloaded artifacts.zip file. Go to the gateware-builds-tester/artifacts/bitstreams directory:
+Unzip the downloaded ``artifacts.zip`` file. Go to the ``gateware-builds-tester/artifacts/bitstreams`` directory:
+
+.. code:: shell
cd gateware-builds-tester/artifacts/bitstreams
On your Linux host development computer, use the scp command to copy the bitstream to BeagleV-Fire
-home directory, replacing <IP_ADDRESS> with the IP address of your BeagleV-Fire.
+home directory, replacing ``<IP_ADDRESS>`` with the IP address of your BeagleV-Fire.
+
+.. code:: shell
scp -r ./my_custom_fpga_design beagle@<IP_ADDRESS>:/home/beagle/
On BeagleV-Fire, initiate the reprogramming of the FPGA with your gateware bitstream:
- sudo su
- /usr/share/beagleboard/gateware/changes-gateware.sh ./my_custom_fpga_design
+.. code:: shell
+
+ sudo /usr/share/beagleboard/gateware/changes-gateware.sh ./my_custom_fpga_design
Wait for a couple of minutes for the BeagleV-Fire to reprogram itself.
@@ -360,8 +397,15 @@ blinking the LED.
On BeagleV-Fire, You can check that your gateware was loaded using the following command to see the
device tree overlays:
+.. code:: shell
+
tree /proc/device-tree/chosen/overlays/
.. figure:: media/gateware-lovely-overlay.png
:align: center
+ :width: 740
+ :alt: gateware lovely overlay
+
+ gateware lovely overlay
+