- Jul 20, 2022
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Robert Nelson authored
v5.10.9-2021_1020 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Reference: v5.10.9 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Reference: v5.15.55 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Reference: v5.10.131 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Reference: v5.13.19 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Reference: v5.13.19 Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
patch-5.10.120-rt70.patch.xz Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Jason Kridner authored
From https://github.com/statropy/wpanusb
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
Signed-off-by:
Robert Nelson <robertcnelson@gmail.com>
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Robert Nelson authored
This reverts commit e68b60ae.
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- Jul 14, 2022
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Texas Instruments Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arm64: dts: ti: k3-am642: Fix the L2 cache sets Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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Nishanth Menon authored
A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae938 ("arm64: dts: ti: Add support for AM642 SoC") Reported-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com
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- Jul 13, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : drm/bridge: ti-sn65dsi86: Detect id panel is connected drm/bridge: ti-sn65dsi86: Return probe deffer in finding dsi host Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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Detect if panel is connected during bridge attach and return the status in connector detect hook. Also add pm runtime calls in the aux transfer function since this should be supported even before pre enable Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Move finding dsi host to a earlier stage in the probe and return EPROBE_DEFFER in case dsi host is not probed yet Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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- Jul 10, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration net: ethernet: ti: am65-cpsw: Fix devlink port register sequence Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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commit e72659b6 upstream. This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf ). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20220303055026.24899-1-sjakhade@cadence.com Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Renaming interfaces using udevd depends on the interface being registered before its netdev is registered. Otherwise, udevd reads an empty phys_port_name value, resulting in the interface not being renamed. Fix this by registering the interface before registering its netdev by invoking am65_cpsw_nuss_register_devlink() before invoking register_netdev() for the interface. Move the function call to devlink_port_type_eth_set(), invoking it after register_netdev() is invoked, to ensure that netlink notification for the port state change is generated after the netdev is completely initialized. Fixes: 4c3e6208 ("net: ti: am65-cpsw-nuss: Add devlink support") Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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- Jul 07, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: Fix build error without PHYLINK ti_config_fragments: connectivity: Enable GPIO bitbang MDIO Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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commit bfa323c6 upstream. If PHYLINK is n, build fails: drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_link_ksettings': am65-cpsw-ethtool.c:(.text+0x118): undefined reference to `phylink_ethtool_ksettings_set' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_get_link_ksettings': am65-cpsw-ethtool.c:(.text+0x138): undefined reference to `phylink_ethtool_ksettings_get' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_eee': am65-cpsw-ethtool.c:(.text+0x158): undefined reference to `phylink_ethtool_set_eee' Select PHYLINK for TI_K3_AM65_CPSW_NUSS to fix this. Fixes: e8609e69 ("net: ethernet: ti: am65-cpsw: Convert to PHYLINK") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20220409105931.9080-1-yuehaibing@huawei.com Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Lets enable GPIO bitbang MDIO support for some of the platforms that can benefit out of it Suggested-by:
Kishon Vijay Abraham I <kishon@ti.com> Suggested-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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- Jun 28, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: Add RMII mode to supported interfaces Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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Support for RMII mode is already present in the am65-cpsw driver. Currently, RMII mode is not set as a supported phy_mode in struct "phylink_config"'s supported_interfaces member. This prevents an interface from being used in RMII mode. Fix it by adding RMII mode as a supported phy-mode if requested by the interface. Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Texas Instruments Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : dmaengine: ti: k3-psil: add additional TX threads for j7200 dmaengine: ti: k3-psil: add additional TX threads for j721e arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator dmaengine: ti: k3-psil-j721s2: Add psil threads for sa2ul arm64: dts: ti: k3-am62-main: Do not exclusively claim SA3UL arm64: dts: ti: k3-am64-main: Do not exclusively claim SA2UL arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID arm64: dts: ti: k3-am62-main: Disable RNG node arm64: dts: ti: k3-am64-main: Disable RNG node arm64: dts: ti: k3-j7200-mcu-wakeup: Disable RNG node arm64: dts: ti: k3-am65-main: Disable RNG node crypto: sa2ul - Check engine status before enabling misc: Kconfig: add DMABUF_HEAPS dependency to SRAM_DMA_HEAP gpio: davinci: Add support for system suspend/resume PM Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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- Jun 27, 2022
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Matt Ranostay authored
Add matching PSI-L threads mapping for transmission DMA channels on the J7200 platform. Signed-off-by:
Matt Ranostay <mranostay@ti.com>
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Matt Ranostay authored
Add matching PSI-L threads mapping for transmission DMA channels on the J721E platform. Signed-off-by:
Matt Ranostay <mranostay@ti.com>
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Jayesh Choudhary authored
Add the node for SA2UL for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com>
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