diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index ca0aee0f05747976d04ae9e0359f0bef8383ade3..0506c6324704eb1976c70132c401c3d120cabf55 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,5 +1,6 @@
stages: # List of stages for jobs, and their order of execution
- build
+ - deploy
build-job: # This job runs in the build stage, which runs first.
stage: build
@@ -38,3 +39,53 @@ build-job: # This job runs in the build stage, which runs first.
- gateware-builds-tester/artifacts/
reports:
junit: gateware-builds-tester/artifacts/tests_report.xml
+
+pages:
+ image: robertcnelson/beagle-devscripts-ubuntu-23.04-riscv64:latest
+ # https://git.beagleboard.org/beagleboard/ci-docker-images
+ stage: deploy
+ tags:
+ - docker-riscv64-ci
+ variables:
+ BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
+ BRANCH_UNDER_TEST: "develop"
+ rules:
+ - if: $CI_PIPELINE_SOURCE == "merge_request_event" && ($CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "main" || $CI_MERGE_REQUEST_TARGET_BRANCH_NAME == "develop")
+ variables:
+ BUILD_OPTIONS_DIRECTORY: "build-options"
+ REPO_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_PROJECT_URL
+ BRANCH_UNDER_TEST: $CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
+ DEBIAN_CHANGELOG_PKG: "bbb.io-gateware"
+ DEBIAN_SRC: "debian"
+ - if: $CI_PIPELINE_SOURCE == "push"
+ variables:
+ BUILD_OPTIONS_DIRECTORY: "custom-fpga-design"
+ REPO_UNDER_TEST: $CI_PROJECT_URL
+ BRANCH_UNDER_TEST: $CI_COMMIT_BRANCH
+ DEBIAN_CHANGELOG_PKG: "bbb.io-gateware-my-custom-fpga-design"
+ DEBIAN_SRC: "debian-custom"
+ script:
+ - rm -rf ./src/ || true
+ - mkdir -p ./src/debian/ || true
+ - rsync -av ./$DEBIAN_SRC/* ./src/debian/
+ - mkdir -p ./src/gateware-builds-tester || true
+ - rsync -av ./gateware-builds-tester/* ./src/gateware-builds-tester/
+ - echo "$DEBIAN_CHANGELOG_PKG (1.$(LANG=C date +%Y%m%d).0-0~lunar) lunar; urgency=low" > ./src/debian/changelog
+ - echo "" >> ./src/debian/changelog
+ - echo " * ci build of $CI_PROJECT_URL" >> ./src/debian/changelog
+ - echo "" >> ./src/debian/changelog
+ - echo " -- $GITLAB_USER_NAME <$GITLAB_USER_EMAIL> $(LANG=C date -R)" >> ./src/debian/changelog
+ - echo "" >> ./src/debian/changelog
+ - cat ./src/debian/changelog
+ - cd ./src/ ; debuild -b -us -uc ; cd ../
+ - mkdir -p ./public/dists/stable/main/binary-riscv64/
+ - mkdir -p ./public/pool
+ - cp -v *.deb ./public/pool/ || true
+ - cp -v *.build ./public/ || true
+ - cp -v *.buildinfo ./public/ || true
+ - cd ./public ; dpkg-scanpackages ./pool/ | gzip > ./dists/stable/main/binary-riscv64/Packages.gz || true ; cd ../
+ - apindex public
+ artifacts:
+ when: on_success
+ paths:
+ - public
diff --git a/build-bitstream.py b/build-bitstream.py
index caed8f98e1fb43f23a33a4cd9e640ba975ffeb3b..be20d126a745512c2808c26895ffccbe3c4fd96d 100644
--- a/build-bitstream.py
+++ b/build-bitstream.py
@@ -42,6 +42,7 @@ import requests
import yaml
import sys
import subprocess
+import datetime
from generate_gateware_overlays import generate_gateware_overlays
@@ -93,7 +94,7 @@ def parse_arguments():
# Checks to see if all of the required tools are installed and present in path, if a needed tool isn't available the script will exit
-def check_tool_status_linux():
+def check_tool_status():
if shutil.which("libero") is None:
print("Error: libero not found in path")
exit()
@@ -116,11 +117,16 @@ def check_tool_status_linux():
path = os.environ["PATH"]
- if "/riscv-unknown-elf-gcc/bin" not in path:
+ if "riscv-unknown-elf-gcc" not in path:
print(
"The path to the RISC-V toolchain needs to be set in PATH to run this script")
exit()
+ if platform.system() == "Linux" or platform.system() == "Linux2":
+ if shutil.which("dtc") is None:
+ print("Error: dtc (device-tree-compiler) not found in path")
+ exit()
+
# Creates required folders and removes artifacts before beginning
def init_workspace():
@@ -274,30 +280,40 @@ def get_libero_script_args(source_list):
return libero_script_args
+#
+# Retrieve/generate the gateware's design version. This version number is stored in the PolarFire SoC device and used
+# as part of programming the PolarFire SoC FPGA using IAP (gateware programming from Linux).
+# Care must be taken to ensure this version number is different between programming attempts. Otherwise, the PolarFire
+# SoC System Controller will not attempt to program the FPGA with the new gateware if it finds the design versions are
+# identical.
+# The approach to managing design version numbers is to use a unique design version number for release gateware. This
+# unique design version number is specified as part of the yaml build option file. The version number is dd.vv.r where
+# dd identifies the design, vv is an incremental features identifier and r is a revision number.
+# For development, the design version number is generated based on the gateware generation date/time. This generated
+# version number loops back every 45 days given the design version number stored in PolarFire SoC is 16 bit long.
+#
def get_design_version(source_list):
- if "custom-fpga-design" in source_list:
- #
- # Ensure every CI gateware build uses a unique version number for gateware programming to
- # be successful (IAP only re-programs the FPGA if the Libero design version is different
- # from the one already programmed in the FPGA).
- # This is required for forked repos.
- #
- git_hash = subprocess.check_output(['git', 'rev-parse', '--short', 'HEAD'])
- git_hash_hex = git_hash.decode('ascii').strip("'")
- git_hash_dec = int(git_hash_hex, 16) % 65535
- design_version = str(git_hash_dec)
- else:
- with open(source_list) as f: # open the yaml file passed as an arg
- data = yaml.load(f, Loader=yaml.FullLoader)
- unique_design_version = data.get("gateware").get("unique-design-version")
- f.close()
- if unique_design_version is None:
- unique_design_version = "65.53.5"
-
- udv_sl = unique_design_version.split(".")
- design_version = (int(udv_sl[0]) * 1000) + (int(udv_sl[1]) * 10) + int(udv_sl[2])
+ with open(source_list) as f: # open the yaml file passed as an arg
+ data = yaml.load(f, Loader=yaml.FullLoader)
+ unique_design_version = data.get("gateware").get("unique-design-version")
+ f.close()
- print("design_version: ", design_version)
+ if unique_design_version is None:
+ now = datetime.datetime.now()
+ day_of_year = now.timetuple().tm_yday
+ design_version = ((day_of_year %45) * 1440) + (now.hour * 60) + now.minute
+ else:
+ try:
+ udv_sl = unique_design_version.split(".")
+ design_version = (int(udv_sl[0]) * 1000) + (int(udv_sl[1]) * 10) + int(udv_sl[2])
+ except (ValueError, AttributeError):
+ print("Error: Invalid value for unique-design-version in ", source_list )
+ print("unique-design-version must be in the form dd.vv.r")
+ exit()
+
+ # FPGA design version number stored in Polarfire SoC devices is 16 bits long.
+ design_version = design_version % 65536
+ print("Design version: ", design_version)
return str(design_version)
@@ -337,14 +353,14 @@ def generate_libero_project(libero, yaml_input_file):
# Execute the Libero TCL script used to create the Libero design
initial_directory = os.getcwd()
os.chdir("./sources/FPGA-design")
- project_location = os.path.join(initial_directory, "work/libero")
- script = os.path.join(initial_directory , "sources/FPGA-design/BUILD_BVF_GATEWARE.tcl")
+ project_location = os.path.join("..", "..", "work", "libero")
+ script = os.path.join("..", "..", "sources", "FPGA-design", "BUILD_BVF_GATEWARE.tcl")
script_args = get_libero_script_args(yaml_input_file)
design_version = get_design_version(yaml_input_file)
- hss_image_location = os.path.join(initial_directory, "work/HSS/hss-envm-wrapper-bm1-p0.hex")
- prog_export_path = initial_directory
+ hss_image_location = os.path.join("..", "..", "work", "HSS", "hss-envm-wrapper-bm1-p0.hex")
+ prog_export_path = os.path.join("..", "..")
top_level_name = get_top_level_name()
print("top level name: ", top_level_name)
@@ -362,7 +378,7 @@ def main():
parse_arguments()
# This function will check if all of the required tools are present and quit if they aren't
- check_tool_status_linux()
+ check_tool_status()
sources = {}
@@ -374,7 +390,9 @@ def main():
build_options_list = get_libero_script_args(yaml_input_file)
generate_gateware_overlays(os.path.join(os.getcwd(), "bitstream", "LinuxProgramming"), build_options_list)
- make_mss_config(mss_configurator, "./sources/MSS_Configuration/MSS_Configuration.cfg", os.path.join(os.getcwd(), "work/MSS"))
+ mss_config_file_path = os.path.join(".", "sources", "MSS_Configuration", "MSS_Configuration.cfg")
+ work_mss_dir = os.path.join("work", "MSS")
+ make_mss_config(mss_configurator, mss_config_file_path, os.path.join(os.getcwd(), work_mss_dir))
make_hss(sources["HSS"], yaml_input_file)
diff --git a/custom-fpga-design/my_custom_fpga_design.yaml b/custom-fpga-design/my_custom_fpga_design.yaml
index 4d8eaee4792735a701b3662663b62678508c0e17..cde4a26a4ed761cd2625e82c1f64205be16fac6a 100644
--- a/custom-fpga-design/my_custom_fpga_design.yaml
+++ b/custom-fpga-design/my_custom_fpga_design.yaml
@@ -7,5 +7,4 @@ HSS:
gateware:
type: sources
build-args: "M2_OPTION:NONE CAPE_OPTION:VERILOG_TUTORIAL"
- unique-design-version: 9.0.2
diff --git a/debian-custom/bbb.io-gateware-my-custom-fpga-design.install b/debian-custom/bbb.io-gateware-my-custom-fpga-design.install
new file mode 100644
index 0000000000000000000000000000000000000000..443448bcb27c672d62d556b4de8dced82056e00b
--- /dev/null
+++ b/debian-custom/bbb.io-gateware-my-custom-fpga-design.install
@@ -0,0 +1,3 @@
+gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/DirectC/* /usr/share/beagleboard/gateware/my_custom_fpga_design/DirectC
+gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/FlashProExpress/* /usr/share/beagleboard/gateware/my_custom_fpga_design/FlashProExpress
+gateware-builds-tester/artifacts/bitstreams/my_custom_fpga_design/LinuxProgramming/* /usr/share/beagleboard/gateware/my_custom_fpga_design/LinuxProgramming
\ No newline at end of file
diff --git a/debian-custom/changelog b/debian-custom/changelog
new file mode 100644
index 0000000000000000000000000000000000000000..4b97b11a65c5e21629173ceb4a3eabc8c8bae7cf
--- /dev/null
+++ b/debian-custom/changelog
@@ -0,0 +1,5 @@
+bbb.io-gateware-my-custom-fpga-design (1.20231226.0-0~lunar) lunar; urgency=low
+
+ * ci build of https://git.beagleboard.org/beaglev-fire/gateware
+
+ -- Robert Nelson <robertcnelson@beagleboard.org> Tue, 26 Dec 2023 17:41:26 +0000
diff --git a/debian-custom/compat b/debian-custom/compat
new file mode 100644
index 0000000000000000000000000000000000000000..f599e28b8ab0d8c9c57a486c89c4a5132dcbd3b2
--- /dev/null
+++ b/debian-custom/compat
@@ -0,0 +1 @@
+10
diff --git a/debian-custom/control b/debian-custom/control
new file mode 100644
index 0000000000000000000000000000000000000000..92153949e4b25ebd1415f16d00b5a8aa983e13cc
--- /dev/null
+++ b/debian-custom/control
@@ -0,0 +1,17 @@
+Source: bbb.io-gateware-my-custom-fpga-design
+Section: misc
+Priority: extra
+Maintainer: Robert Nelson <robertcnelson@gmail.com>
+Build-Depends:
+ debhelper (>= 10)
+Standards-Version: 4.5.1
+
+Package: bbb.io-gateware-my-custom-fpga-design
+Architecture: all
+Depends:
+ ${shlibs:Depends}
+ , ${misc:Depends}
+ , bbb.io-gateware
+ , mtd-utils
+Description: bbb.io-gateware-my-custom-fpga-design
+ bbb.io-gateware-my-custom-fpga-design
diff --git a/debian-custom/rules b/debian-custom/rules
new file mode 100755
index 0000000000000000000000000000000000000000..9752fa6124aa6ff51036c011da99d999ec720ad5
--- /dev/null
+++ b/debian-custom/rules
@@ -0,0 +1,10 @@
+#!/usr/bin/make -f
+# See debhelper(7) (uncomment to enable)
+# output every command that modifies files on the build system.
+DH_VERBOSE = 1
+
+%:
+ dh $@
+
+override_dh_builddeb:
+ dh_builddeb -- -Zxz
diff --git a/debian/bbb.io-gateware.install b/debian/bbb.io-gateware.install
new file mode 100644
index 0000000000000000000000000000000000000000..659223595bc35e1f2448394e0eff508d59749334
--- /dev/null
+++ b/debian/bbb.io-gateware.install
@@ -0,0 +1,15 @@
+debian/change-gateware.sh /usr/share/beagleboard/gateware
+debian/update-gateware.sh /usr/share/microchip/gateware
+debian/mcp356x_read.py /usr/share/microchip/gateware
+gateware-builds-tester/artifacts/bitstreams/board-tests/DirectC/* /usr/share/beagleboard/gateware/board-tests/DirectC
+gateware-builds-tester/artifacts/bitstreams/board-tests/FlashProExpress/* /usr/share/beagleboard/gateware/board-tests/FlashProExpress
+gateware-builds-tester/artifacts/bitstreams/board-tests/LinuxProgramming/* /usr/share/beagleboard/gateware/board-tests/LinuxProgramming
+gateware-builds-tester/artifacts/bitstreams/default/DirectC/* /usr/share/beagleboard/gateware/default/DirectC
+gateware-builds-tester/artifacts/bitstreams/default/FlashProExpress/* /usr/share/beagleboard/gateware/default/FlashProExpress
+gateware-builds-tester/artifacts/bitstreams/default/LinuxProgramming/* /usr/share/beagleboard/gateware/default/LinuxProgramming
+gateware-builds-tester/artifacts/bitstreams/minimal/DirectC/* /usr/share/beagleboard/gateware/minimal/DirectC
+gateware-builds-tester/artifacts/bitstreams/minimal/FlashProExpress/* /usr/share/beagleboard/gateware/minimal/FlashProExpress
+gateware-builds-tester/artifacts/bitstreams/minimal/LinuxProgramming/* /usr/share/beagleboard/gateware/minimal/LinuxProgramming
+gateware-builds-tester/artifacts/bitstreams/robotics/DirectC/* /usr/share/beagleboard/gateware/robotics/DirectC
+gateware-builds-tester/artifacts/bitstreams/robotics/FlashProExpress/* /usr/share/beagleboard/gateware/robotics/FlashProExpress
+gateware-builds-tester/artifacts/bitstreams/robotics/LinuxProgramming/* /usr/share/beagleboard/gateware/robotics/LinuxProgramming
diff --git a/debian/change-gateware.sh b/debian/change-gateware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..fab1167293f40296258241d6f1b6e324cc717bb2
--- /dev/null
+++ b/debian/change-gateware.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+if ! id | grep -q root; then
+ echo "must be run as root"
+ exit
+fi
+
+if [ -d $1 ]
+then
+ echo "Changing gateware."
+ if [ -e $1/LinuxProgramming/mpfs_bitstream.spi ]
+ then
+ if [ -e $1/LinuxProgramming/mpfs_dtbo.spi ]
+ then
+ cp -v $1/LinuxProgramming/mpfs_dtbo.spi /lib/firmware/mpfs_dtbo.spi
+ cp -v $1/LinuxProgramming/mpfs_bitstream.spi /lib/firmware/mpfs_bitstream.spi
+ sync
+ . /usr/share/microchip/gateware/update-gateware.sh
+ else
+ echo "No device tree overlay file found."
+ fi
+ else
+ echo "No gateware file found."
+ fi
+else
+ echo "No directory found for this requested gateware."
+fi
diff --git a/debian/changelog b/debian/changelog
new file mode 100644
index 0000000000000000000000000000000000000000..5e6715d53b694d953e09357ebb477f90e1570421
--- /dev/null
+++ b/debian/changelog
@@ -0,0 +1,5 @@
+bbb.io-gateware (1.20231226.0-0~lunar) lunar; urgency=low
+
+ * ci build of https://git.beagleboard.org/beaglev-fire/gateware
+
+ -- Robert Nelson <robertcnelson@beagleboard.org> Tue, 26 Dec 2023 17:41:26 +0000
diff --git a/debian/compat b/debian/compat
new file mode 100644
index 0000000000000000000000000000000000000000..f599e28b8ab0d8c9c57a486c89c4a5132dcbd3b2
--- /dev/null
+++ b/debian/compat
@@ -0,0 +1 @@
+10
diff --git a/debian/control b/debian/control
new file mode 100644
index 0000000000000000000000000000000000000000..281f9a2104ebfa992f362c525bab3b7117543bc4
--- /dev/null
+++ b/debian/control
@@ -0,0 +1,16 @@
+Source: bbb.io-gateware
+Section: misc
+Priority: extra
+Maintainer: Robert Nelson <robertcnelson@gmail.com>
+Build-Depends:
+ debhelper (>= 10)
+Standards-Version: 4.5.1
+
+Package: bbb.io-gateware
+Architecture: all
+Depends:
+ ${shlibs:Depends}
+ , ${misc:Depends}
+ , mtd-utils
+Description: bbb.io-gateware
+ bbb.io-gateware
diff --git a/debian/mcp356x_read.py b/debian/mcp356x_read.py
new file mode 100644
index 0000000000000000000000000000000000000000..d73787d481ecbbb7108558f6942ef2d0bb5cdf73
--- /dev/null
+++ b/debian/mcp356x_read.py
@@ -0,0 +1,322 @@
+#!/bin/env python3
+
+#
+# This script is intended to be run with python 3
+#
+
+import time
+import os
+import re
+import subprocess
+import functools
+
+voltage_raws = []
+
+voltage_differential_raws = []
+
+voltage_scales = [ "in_voltage-voltage_scale" ]
+
+hw_gain = [ "hardwaregain" ]
+
+hw_gain_available = [ hw_gain[0] + "_available" ]
+
+calib_bias = [ "calibbias" ]
+
+calib_bias_available = [ calib_bias[0] + "_available" ]
+
+calib_scale = [ "calibscale" ]
+
+calib_scale_available = [ calib_scale[0] + "_available" ]
+
+oversampling_ratio = [ "oversampling_ratio" ]
+
+oversampling_ratio_available = [ oversampling_ratio[0] + "_available" ]
+temperature_raws = [ "in_temp_raw" ]
+
+temperature_scale = [ "in_temp_scale" ]
+
+DIR_PATH="/sys/bus/iio/devices/"
+device = []
+mcp_devices = []
+
+device2channels ={}
+
+
+new_line = '\n'
+
+def mult(file1_name, file2_name):
+ global ABS_PATH
+ file1 = open(ABS_PATH+file1_name,'r')
+ val1 = int(file1.read())
+ file1.close()
+ file2 = open(ABS_PATH+file2_name,'r')
+ val2 = float(file2.read())
+ file2.close()
+ return (val1 * val2)
+
+
+def print_attribute(file_name):
+ global ABS_PATH
+ attr_file = open(ABS_PATH + file_name,'r')
+ string = attr_file.read()
+ attr_file.close()
+ # clean the string for printing
+ string = string.replace("0000000", "")
+ return string
+
+def calculate_temperature(file1_name):
+ global ABS_PATH
+
+ name_file = open(ABS_PATH + "name",'r')
+ device_name_string = name_file.read()
+ name_file.close()
+
+ temperature = open(ABS_PATH+file1_name,'r')
+ temperature_val = int(temperature.read())
+ temperature.close()
+
+ if ( 'mcp3564\n' == device_name_string ):
+ return temperature_val * 4.0096 * 0.0001 * 2.4 - 269.13
+ else:
+ return 0
+
+def write_attribute(file_name, value):
+ global ABS_PATH
+ attr_file = open(ABS_PATH + file_name,'w')
+ attr_file.write(value)
+ attr_file.close()
+ return 0
+
+def get_name(file_name):
+ global ABS_PATH
+ attr_file = open(file_name,'r')
+ string = attr_file.read()
+ attr_file.close()
+ return string
+
+
+
+
+if not os.path.isdir(DIR_PATH):
+ print('IIO is not enabled')
+ exit()
+
+proc = subprocess.Popen("ls -1 " + DIR_PATH + "| grep device", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+stdout, stderr = proc.communicate()
+
+lines = stdout.decode('utf-8').split('\n')
+
+print('Search for devices:')
+for line in lines:
+ path=DIR_PATH + line
+ if os.path.exists(path):
+ if os.path.exists(path + "/name"):
+ device_name= get_name(path + "/name")
+
+ print('------------->', device_name)
+
+ if re.search(r"mcp3[45]6[124][rR]", device_name):
+ device_index = re.findall(r'\d+', line)
+ if device_index:
+ mcp_devices.append(device_index[0])
+
+ # get voltage_raws*
+ proc_channels = subprocess.Popen("ls -1 " + path + "/ | grep in_voltage* | grep -v scale | grep -v \"-\"", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+ stdout_channels, stderr_channels = proc_channels.communicate()
+ voltage_raws = stdout_channels.decode('utf-8').split('\n')
+ voltage_raws = voltage_raws[:-1]
+
+ # get voltage_differential_raws
+ proc_channels = subprocess.Popen("ls -1 " + path + "/ | grep in_voltage* | grep -v scale | grep \"-\"", shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+ stdout_channels, stderr_channels = proc_channels.communicate()
+ voltage_differential_raws = stdout_channels.decode('utf-8').split('\n')
+ voltage_differential_raws = voltage_differential_raws[:-1]
+
+
+for mcp_device in mcp_devices:
+ ABS_PATH = f'{DIR_PATH}iio:device{mcp_device}/'
+
+ print('--------------------------------')
+ print('--------------------------------')
+ print('--------------------------------')
+ print(f'Device: {print_attribute("name")}')
+ print('--------------------------------')
+
+ print(f'Available Voltage Oversampling Ratio:')
+ oversampling_ratio_string = print_attribute(oversampling_ratio_available[0])
+ oversampling_ratio_list = oversampling_ratio_string.split()
+ print(f' {oversampling_ratio_string}')
+
+ print('--------------------------------')
+ print(f'Current Voltage Oversampling Ratio: %s' % (print_attribute(oversampling_ratio[0])))
+ print('--------------------------------')
+
+ print(f'Available Voltage Hardware Gain:')
+ hw_gain_string = print_attribute(hw_gain_available[0])
+ hw_gain_list = hw_gain_string.split()
+ print(f' {hw_gain_string}')
+
+ print('--------------------------------')
+ print(f'Current Voltage Hardware Gain: %s' % (print_attribute(hw_gain[0])))
+ print('--------------------------------')
+
+ print(f'Available Voltage Calibration Bias {new_line} [ Low, Step, High ] {new_line} %s' % (print_attribute(calib_bias_available[0]).replace(" ", " ")))
+
+ print('--------------------------------')
+ print(f'Current Voltage Calibration Bias: %s' % (print_attribute(calib_bias[0])))
+ print('--------------------------------')
+
+ print(f'Available Voltage Calibration Scale {new_line} [ Low, Step, High ] {new_line} %s' % (print_attribute(calib_scale_available[0]).replace(" ", " ")))
+
+ print('--------------------------------')
+ print(f'Current Voltage Calibration Scale: %s' % (print_attribute(calib_scale[0])))
+ print('--------------------------------')
+
+ print('--------------------------------')
+ # Measured voltage in millivolts
+ # U = in2_raw * in_scale
+
+ print('\n Voltage')
+ print('=========')
+
+ print(f' Channel V mV')
+ for raw in voltage_raws:
+ # Voltage Scale is in mV
+ voltage_mv = mult(raw,voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ print(f' {raw}: %2.4f | %5.6f' % (voltage, voltage_mv))
+
+ print('\n\n--------------------------------')
+
+
+ print('\n Differential Voltage')
+ print('======================')
+
+ print(f' Channel V mV')
+ for raw in voltage_differential_raws:
+ # Voltage Scale is in mV
+ voltage_mv = mult(raw,voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ print(f' {raw}: %8.4f | %15.6f' % (voltage, voltage_mv))
+
+ print('\n\n--------------------------------')
+ print('\n\n Temperature(',u'\xb0\x43','): %8.4f' % calculate_temperature(temperature_raws[0]))
+ print('\n\n--------------------------------')
+
+ if os.geteuid()==0:
+ print('\n\n================================')
+ print ('Running as root.')
+ print('================================\n\n')
+
+ # Testing Hardware Gain
+ current_hw_gain = print_attribute(hw_gain[0])
+ print(f' Current Voltage Hardware Gain: x{current_hw_gain}')
+
+
+ print('\n================================')
+ print(f' Testing Hardware gain settings: {hw_gain_string}')
+ print('================================\n')
+ print('--------------------------------')
+
+ for hw_gain_value in hw_gain_list:
+ print(f' {new_line} Set Voltage Hardware Gain: x{hw_gain_value}')
+
+ write_attribute(hw_gain[0], hw_gain_value)
+
+ print(f' Channel V mV')
+ voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ print(f' {voltage_differential_raws[0]}: %2.4f | %5.6f -> Hw Gain: x%s' % (voltage, voltage_mv, print_attribute(hw_gain[0])))
+ print('---------------------------------------------------------------------------------------------------------------------')
+
+ # set back the Hardware Gain
+ write_attribute(hw_gain[0], current_hw_gain)
+ print('--------------------------------')
+
+ # Testing Oversampling Ratio
+ current_oversampling_ratio = print_attribute(oversampling_ratio[0])
+ print(f' Current Oversampling Ratio: x{current_oversampling_ratio}')
+
+ print(f' {new_line}')
+ print('\n================================')
+ print(f' Testing Oversampling Ratio settings: {oversampling_ratio_string}')
+ print('================================\n')
+ print('--------------------------------')
+
+ for oversampling_ratio_value in oversampling_ratio_list:
+ print(f' {new_line} Set Oversampling Ratio: x{oversampling_ratio_value}')
+
+ write_attribute(oversampling_ratio[0], oversampling_ratio_value)
+
+ print(f' Channel V mV')
+ voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ print(f' {voltage_differential_raws[0]}: %2.4f | %5.6f -> Oversampling Ratio: x%s' % (voltage, voltage_mv, print_attribute(oversampling_ratio[0])))
+ print('---------------------------------------------------------------------------------------------------------------------')
+
+ # set back the Oversampling Ratio
+ write_attribute(oversampling_ratio[0], current_oversampling_ratio)
+ print('\n--------------------------------')
+
+ # Testing Calibration BIAS
+ current_calib_bias = print_attribute(calib_bias[0])
+ print(f'{new_line} Current Calibration BIAS: {current_calib_bias}')
+
+ print('\n\n================================')
+ print(f' Testing Calibration Bias settings')
+ print('================================\n')
+ print('--------------------------------\n')
+
+ calib_bias_value = "50000"
+ print(f' {new_line} Set Calibration BIAS: {calib_bias_value}')
+
+ write_attribute(calib_bias[0], calib_bias_value)
+
+ print(f' Channel V mV')
+ voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ print(f' {voltage_differential_raws[0]}: %2.4f | %5.6f -> Calibration BIAS: %s' % (voltage, voltage_mv, print_attribute(calib_bias[0])))
+ print('---------------------------------------------------------------------------------------------------------------------')
+
+ # set back the Calibration Bias
+ write_attribute(calib_bias[0], "0")
+ print('\n--------------------------------')
+
+ # Testing Calibration Scale
+ calib_scale_x1_gain = 8388608
+
+ current_calib_scale = print_attribute(calib_scale[0])
+ print(f'{new_line} Current Calibration Scale: {int(current_calib_scale)/calib_scale_x1_gain}')
+
+ print('\n\n================================')
+ print(f' Testing Calibration Scale settings')
+ print('================================\n')
+ print('--------------------------------')
+
+ calib_scale_value = 4194304;
+ print(f' {new_line} Set Calibration Scale: {calib_scale_value/calib_scale_x1_gain}')
+
+ write_attribute(calib_scale[0], str(calib_scale_value))
+
+ print(f' Channel V mV')
+ voltage_mv = mult(voltage_differential_raws[0], voltage_scales[0])
+ voltage = voltage_mv/1000
+ print('---------------------------------------------------------------------')
+ calib_scale_string = print_attribute(calib_scale[0])
+ calib_scale_int = int(calib_scale_string)
+ print(f' {voltage_differential_raws[0]}: %2.4f | %5.6f -> Calibration Scale: x%2.6f' % (voltage, voltage_mv, calib_scale_int/calib_scale_x1_gain))
+ print('*********************************************************************************************************************')
+ print('*********************************************************************************************************************')
+ print('*********************************************************************************************************************')
+
+ # set back the Calibration Scale
+ write_attribute(calib_scale[0], str(calib_scale_x1_gain))
+
+ else:
+ print ('User is not root.\n')
+ print ('Changing the user configurable settings must by done by root user.\n')
\ No newline at end of file
diff --git a/debian/rules b/debian/rules
new file mode 100755
index 0000000000000000000000000000000000000000..9752fa6124aa6ff51036c011da99d999ec720ad5
--- /dev/null
+++ b/debian/rules
@@ -0,0 +1,10 @@
+#!/usr/bin/make -f
+# See debhelper(7) (uncomment to enable)
+# output every command that modifies files on the build system.
+DH_VERBOSE = 1
+
+%:
+ dh $@
+
+override_dh_builddeb:
+ dh_builddeb -- -Zxz
diff --git a/debian/update-gateware.sh b/debian/update-gateware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..2b1deb28a9f9d63e7e6d56fcc58404c1708ef994
--- /dev/null
+++ b/debian/update-gateware.sh
@@ -0,0 +1,45 @@
+#!/bin/bash
+echo "================================================================================"
+echo "| FPGA Gateware Update |"
+echo "| |"
+echo "| Please ensure that the mpfs_bitstream.spi file containing the gateware |"
+echo "| update has been copied to directory /lib/firmware. |"
+echo "| |"
+echo "| !!! This will take a couple of minutes. !!! |"
+echo "| |"
+echo "| Give the system a few minutes to reboot itself |"
+echo "| after Linux has shutdown. |"
+echo "| |"
+echo "================================================================================"
+
+if [ ! -f /lib/firmware/mpfs_bitstream.spi ] ; then
+ echo "Missing: /lib/firmware/mpfs_bitstream.spi"
+ exit 2
+fi
+
+#read -rsp $'Press any key to continue...\n' -n1 key
+
+if [ ! -f /sys/kernel/debug/fpga/microchip_exec_update ] ; then
+ /usr/bin/mount -t debugfs none /sys/kernel/debug
+fi
+
+# Trash exisitng device tree overlay in case the rest of the process fails:
+/usr/sbin/mtd_debug erase /dev/mtd0 0x0 0x10000
+
+# Write device tree overlay
+dtbo_ls=$(ls -l /lib/firmware/mpfs_dtbo.spi)
+dtbo_size=$(echo $dtbo_ls | cut -d " " -f 5)
+
+echo "Writing mpfs_dtbo.spi to /dev/mtd0"
+/usr/sbin/mtd_debug write /dev/mtd0 0x400 $dtbo_size /lib/firmware/mpfs_dtbo.spi > /dev/zero
+
+# Fake the presence of a golden image for now.
+/usr/sbin/mtd_debug write /dev/mtd0 0 4 /dev/zero > /dev/zero
+
+# Initiate FPGA update.
+echo "Triggering FPGA Gateware Update (/sys/kernel/debug/fpga/microchip_exec_update)"
+echo 1 > /sys/kernel/debug/fpga/microchip_exec_update
+
+# Reboot Linux for the gateware update to take effect.
+# FPGA reprogramming takes places between Linux shut-down and HSS restarting the board.
+/usr/sbin/reboot
diff --git a/generate_gateware_overlays.py b/generate_gateware_overlays.py
index 47dd3ec19c4365f2a0e7decfb8b575ed5a6dd7ad..7cd0f6afe4304ba8f21a874e55622a8f641470c2 100644
--- a/generate_gateware_overlays.py
+++ b/generate_gateware_overlays.py
@@ -107,7 +107,7 @@ def get_gateware_git_version(work_dir):
try:
git_hash = subprocess.check_output(['git', 'describe', '--tags'])
except subprocess.CalledProcessError as e:
- git_hash = 0
+ git_hash = b"\n"
return git_hash.decode('ascii').strip("'").strip("\n")
diff --git a/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl b/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
index 536458652753dbf21cad45619d48bede73c9e210..1bb716567cb7d38f147c0403b5ff2bf090656008 100644
--- a/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
+++ b/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
@@ -285,7 +285,14 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_SS
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_SS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_CLK}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_56_58} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_3_7} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_F} -value {GND}
#-------------------------------------------------------------------------------
diff --git a/sources/FPGA-design/script_support/components/BVF_RISCV_SUBSYSTEM.tcl b/sources/FPGA-design/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
index 163e46d9275a62ff680595731699a2b63efdbfea..d6ef3aa0f699b38524b8a6826964b1d123da8b8a 100644
--- a/sources/FPGA-design/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
+++ b/sources/FPGA-design/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
@@ -102,6 +102,21 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDC} -port_direction {
sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction {INOUT}
+#-------------------------------------------------------------------------------
+# Fabric interrupts
+#-------------------------------------------------------------------------------
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_3_7} -port_direction {IN} -port_range {[7:3]}
+
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_A} -port_direction {IN} -port_range {[15:8]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_B} -port_direction {IN} -port_range {[23:16]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_C} -port_direction {IN} -port_range {[31:24]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_D} -port_direction {IN} -port_range {[39:32]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_E} -port_direction {IN} -port_range {[47:40]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_F} -port_direction {IN} -port_range {[55:48]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {MSS_INT_F2M_56_58} -port_direction {IN} -port_range {[58:56]}
+
#-------------------------------------------------------------------------------
# User LEDs
#-------------------------------------------------------------------------------
@@ -141,15 +156,28 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SOC_MSS} -insta
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[2]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[58:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[7:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[15:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[23:16]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[31:24]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[39:32]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[47:40]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[55:48]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {"[58:56]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[59]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[60]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[61]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[62]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M} -pin_slices {[63]}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:MSS_INT_F2M[58:3]} -port_name {}
-
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_3_7" "PF_SOC_MSS:MSS_INT_F2M[7:3]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_A" "PF_SOC_MSS:MSS_INT_F2M[15:8]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_B" "PF_SOC_MSS:MSS_INT_F2M[23:16]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_C" "PF_SOC_MSS:MSS_INT_F2M[31:24]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_D" "PF_SOC_MSS:MSS_INT_F2M[39:32]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_E" "PF_SOC_MSS:MSS_INT_F2M[47:40]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_F" "PF_SOC_MSS:MSS_INT_F2M[55:48]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS_INT_F2M_56_58" "PF_SOC_MSS:MSS_INT_F2M[58:56]"}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:MSS_INT_M2F}
#sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SOC_MSS:FIC_2_AXI4_TARGET}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
index 91a29bbd42cb2ff0c87404949929f3ee5e70b6de..a21173fd32a2c7f708f634f811dfb44f93bfa005 100644
--- a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
@@ -5,9 +5,9 @@ puts "======== Add cape option: DEFAULT ========"
#-------------------------------------------------------------------------------
source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
source script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
-#source script_support/components/CAPE/DEFAULT/CAPE_CoreAPB.tcl
source script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
-source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+#source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/DEFAULT/P8_GPIO_UPPER.tcl
source script_support/components/CAPE/DEFAULT/CoreGPIO_P9.tcl
source script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
@@ -62,6 +62,17 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN42" "P9_PIN42"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D" "CAPE:INT_D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E" "CAPE:INT_E"}
+
sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} -port_name {}
sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_2_TXD} -new_port_name {P9_24}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/CAPE.tcl
index f655bd5943bcd681317bb286108bfa0b169f1b99..af929b91bf2863d848e309715bd5b6aca866a517 100644
--- a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -1,4 +1,4 @@
-# Creating SmartDesign CAPE
+# Creating SmartDesign "CAPE"
set sd_name {CAPE}
create_smartdesign -sd_name ${sd_name}
@@ -78,6 +78,11 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_A} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_B} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_C} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_D} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_E} -port_direction {OUT} -port_range {[7:0]}
# Create top level Bus interface Ports
@@ -91,6 +96,9 @@ sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AM
"PREADY:APB_SLAVE_SLAVE_PREADY" \
"PSLVERR:APB_SLAVE_SLAVE_PSLVERR" }
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[4:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[7:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {INT_E[7:5]} -value {GND}
# Add APB_BUS_CONVERTER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
@@ -108,11 +116,16 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -in
# Add P8_GPIO_UPPER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[7:0]}
# Add P9_GPIO_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[20:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[7:0]}
@@ -194,6 +207,11 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "PWM_0:PWM_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_A" "P8_GPIO_UPPER_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_B" "P8_GPIO_UPPER_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_C" "P9_GPIO_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_D" "P9_GPIO_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_E[4:0]" "P9_GPIO_0:INT[20:16]" }
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
@@ -206,7 +224,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave5" "PW
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
+# Generate SmartDesign "CAPE"
generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
deleted file mode 100644
index 9b16ecca90b1b7a06df3ac6c26decb3369cc796e..0000000000000000000000000000000000000000
--- a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+++ /dev/null
@@ -1,174 +0,0 @@
-# Creating SmartDesign P8_GPIO_UPPER
-set sd_name {P8_GPIO_UPPER}
-create_smartdesign -sd_name ${sd_name}
-
-auto_promote_pad_pins -promote_all 1
-
-# Add GPIO BIBUFs
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
-
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[0:0]"}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
-
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:APB_bif} -port_name {}
-
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:INT}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P8_GPIO_UPPER
-generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_UPPER.tcl b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_UPPER.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c162d804156e0190274d77127a0241de7f353bfb
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P8_GPIO_UPPER.tcl
@@ -0,0 +1,266 @@
+# Creating SmartDesign "P8_GPIO_UPPER"
+set sd_name {P8_GPIO_UPPER}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_0_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_11_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_13_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_15_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_2_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_3_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_5_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_6_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_7_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_8_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_9_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[15:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" }
+
+# Add CoreGPIO_P8_UPPER_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {CoreGPIO_P8_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[9:9]}
+
+
+
+# Add GPIO_0_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+
+
+
+# Add GPIO_1_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_2_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+
+
+
+# Add GPIO_3_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_5_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+
+
+
+# Add GPIO_6_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+
+
+
+# Add GPIO_7_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+
+
+
+# Add GPIO_8_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+
+
+
+# Add GPIO_9_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_11_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_13_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_15_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_0_BIBUF:PAD" "GPIO_0_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_11_BIBUF:PAD" "GPIO_11_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_13_BIBUF:PAD" "GPIO_13_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_15_BIBUF:PAD" "GPIO_15_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_BIBUF:PAD" "GPIO_2_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_3_BIBUF:PAD" "GPIO_3_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_5_BIBUF:PAD" "GPIO_5_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_6_BIBUF:PAD" "GPIO_6_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_7_BIBUF:PAD" "GPIO_7_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_8_BIBUF:PAD" "GPIO_8_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_9_BIBUF:PAD" "GPIO_9_PAD" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:INT" "INT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P8_UPPER_0:APB_bif" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the SmartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign "P8_GPIO_UPPER"
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
index bb4d1618e707974a5a94a2e458410bf0d23200fe..9afedc1e3d4b599d8a4efeb9ca66ff4ffe819b79 100644
--- a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/P9_GPIO.tcl
@@ -1,4 +1,4 @@
-# Creating SmartDesign P9_GPIO
+# Creating SmartDesign "P9_GPIO"
set sd_name {P9_GPIO}
create_smartdesign -sd_name ${sd_name}
@@ -28,6 +28,7 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_directio
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[20:0]}
# Create top level Bus interface Ports
@@ -148,7 +149,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[8:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[9:9]}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:INT}
@@ -219,13 +219,15 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_19_BIBUF:PAD" "GPIO_19_PAD
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:INT" "INT" }
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P9_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P9_GPIO
+# Generate SmartDesign "P9_GPIO"
generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md
index 2349d4f77db2e1c368a47f5b4b5527140a73a9ed..d02c040d1136b826f451c37825297f3ad0a30c19 100644
--- a/sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md
+++ b/sources/FPGA-design/script_support/components/CAPE/DEFAULT/Readme.md
@@ -2,102 +2,102 @@
## P8 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P8_1 | n/a | GND |
-| P8_2 | n/a | GND |
-| P8_3 | MSS GPIO_2[0] | User LED 0 |
-| P8_4 | MSS GPIO_2[1] | User LED 1 |
-| P8_5 | MSS GPIO_2[2] | User LED 2 |
-| P8_6 | MSS GPIO_2[3] | User LED 3 |
-| P8_7 | MSS GPIO_2[4] | User LED 4 |
-| P8_8 | MSS GPIO_2[5] | User LED 5 |
-| P8_9 | MSS GPIO_2[6] | User LED 6 |
-| P8_10 | MSS GPIO_2[7] | User LED 7 |
-| P8_11 | MSS GPIO_2[8] | User LED 8 |
-| P8_12 | MSS GPIO_2[9] | User LED 9 |
-| P8_13 | core_pwm[1] @ 0x41500000 | PWM_2:1 |
-| P8_14 | MSS GPIO_2[11] | User LED 11 |
-| P8_15 | MSS GPIO_2[12] | GPIO |
-| P8_16 | MSS GPIO_2[13] | GPIO |
-| P8_17 | MSS GPIO_2[14] | GPIO |
-| P8_18 | MSS GPIO_2[15] | GPIO |
-| P8_19 | core_pwm[0] @ 0x41500000 | PWM_2:0 |
-| P8_20 | MSS GPIO_2[17] | GPIO |
-| P8_21 | MSS GPIO_2[18] | GPIO |
-| P8_22 | MSS GPIO_2[19] | GPIO |
-| P8_23 | MSS GPIO_2[20] | GPIO |
-| P8_24 | MSS GPIO_2[21] | GPIO |
-| P8_25 | MSS GPIO_2[22] | GPIO |
-| P8_26 | MSS GPIO_2[23] | GPIO |
-| P8_27 | MSS GPIO_2[24] | GPIO |
-| P8_28 | MSS GPIO_2[25] | GPIO |
-| P8_29 | MSS GPIO_2[26] | GPIO |
-| P8_30 | MSS GPIO_2[27] | GPIO |
-| P8_31 | core_gpio[0] @ 0x41100000 | GPIO |
-| P8_32 | core_gpio[1] @ 0x41100000 | GPIO |
-| P8_33 | core_gpio[2] @ 0x41100000 | GPIO |
-| P8_34 | core_gpio[3] @ 0x41100000 | GPIO |
-| P8_35 | core_gpio[4] @ 0x41100000 | GPIO |
-| P8_36 | core_gpio[5] @ 0x41100000 | GPIO |
-| P8_37 | core_gpio[6] @ 0x41100000 | GPIO |
-| P8_38 | core_gpio[7] @ 0x41100000 | GPIO |
-| P8_39 | core_gpio[8] @ 0x41100000 | GPIO |
-| P8_40 | core_gpio[9] @ 0x41100000 | GPIO |
-| P8_41 | core_gpio[10] @ 0x41100000 | GPIO |
-| P8_42 | core_gpio[11] @ 0x41100000 | GPIO |
-| P8_43 | core_gpio[12] @ 0x41100000 | GPIO |
-| P8_44 | core_gpio[13] @ 0x41100000 | GPIO |
-| P8_45 | core_gpio[14] @ 0x41100000 | GPIO |
-| P8_46 | core_gpio[15] @ 0x41100000 | GPIO |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1 | n/a | n/a | GND |
+| P8_2 | n/a | n/a | GND |
+| P8_3 | MSS GPIO_2[0] | 53 | User LED 0 |
+| P8_4 | MSS GPIO_2[1] | 53 | User LED 1 |
+| P8_5 | MSS GPIO_2[2] | 53 | User LED 2 |
+| P8_6 | MSS GPIO_2[3] | 53 | User LED 3 |
+| P8_7 | MSS GPIO_2[4] | 53 | User LED 4 |
+| P8_8 | MSS GPIO_2[5] | 53 | User LED 5 |
+| P8_9 | MSS GPIO_2[6] | 53 | User LED 6 |
+| P8_10 | MSS GPIO_2[7] | 53 | User LED 7 |
+| P8_11 | MSS GPIO_2[8] | 53 | User LED 8 |
+| P8_12 | MSS GPIO_2[9] | 53 | User LED 9 |
+| P8_13 | core_pwm[1] @ 0x41500000 | n/a | PWM_2:1 |
+| P8_14 | MSS GPIO_2[11] | 53 | User LED 11 |
+| P8_15 | MSS GPIO_2[12] | 53 | GPIO |
+| P8_16 | MSS GPIO_2[13] | 53 | GPIO |
+| P8_17 | MSS GPIO_2[14] | 53 | GPIO |
+| P8_18 | MSS GPIO_2[15] | 53 | GPIO |
+| P8_19 | core_pwm[0] @ 0x41500000 | n/a | PWM_2:0 |
+| P8_20 | MSS GPIO_2[17] | 53 | GPIO |
+| P8_21 | MSS GPIO_2[18] | 53 | GPIO |
+| P8_22 | MSS GPIO_2[19] | 53 | GPIO |
+| P8_23 | MSS GPIO_2[20] | 53 | GPIO |
+| P8_24 | MSS GPIO_2[21] | 53 | GPIO |
+| P8_25 | MSS GPIO_2[22] | 53 | GPIO |
+| P8_26 | MSS GPIO_2[23] | 53 | GPIO |
+| P8_27 | MSS GPIO_2[24] | 53 | GPIO |
+| P8_28 | MSS GPIO_2[25] | 53 | GPIO |
+| P8_29 | MSS GPIO_2[26] | 53 | GPIO |
+| P8_30 | MSS GPIO_2[27] | 53 | GPIO |
+| P8_31 | core_gpio[0] @ 0x41100000 | 126 | GPIO |
+| P8_32 | core_gpio[1] @ 0x41100000 | 127 | GPIO |
+| P8_33 | core_gpio[2] @ 0x41100000 | 128 | GPIO |
+| P8_34 | core_gpio[3] @ 0x41100000 | 129 | GPIO |
+| P8_35 | core_gpio[4] @ 0x41100000 | 130 | GPIO |
+| P8_36 | core_gpio[5] @ 0x41100000 | 131 | GPIO |
+| P8_37 | core_gpio[6] @ 0x41100000 | 132 | GPIO |
+| P8_38 | core_gpio[7] @ 0x41100000 | 133 | GPIO |
+| P8_39 | core_gpio[8] @ 0x41100000 | 134 | GPIO |
+| P8_40 | core_gpio[9] @ 0x41100000 | 135 | GPIO |
+| P8_41 | core_gpio[10] @ 0x41100000 | 136 | GPIO |
+| P8_42 | core_gpio[11] @ 0x41100000 | 137 | GPIO |
+| P8_43 | core_gpio[12] @ 0x41100000 | 138 | GPIO |
+| P8_44 | core_gpio[13] @ 0x41100000 | 139 | GPIO |
+| P8_45 | core_gpio[14] @ 0x41100000 | 140 | GPIO |
+| P8_46 | core_gpio[15] @ 0x41100000 | 141 | GPIO |
## P9 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P9_1 | n/a | GND |
-| P9_2 | n/a | GND |
-| P9_3 | n/a | VCC 3.3V |
-| P9_4 | n/a | VCC 3.3V |
-| P9_5 | n/a | VDD 5V |
-| P9_6 | n/a | VDD 5V |
-| P9_7 | n/a | SYS 5V |
-| P9_8 | n/a | SYS 5V |
-| P9_9 | n/a | NC |
-| P9_10 | n/a | SYS_RSTN |
-| P9_11 | MMUART4 | UART4 RX |
-| P9_12 | core_gpio[1] @ 0x41200000 | GPIO |
-| P9_13 | MMUART4 | UART4 TX |
-| P9_14 | core_pwm[0] @ 0x41400000 | PWM_1:0 |
-| P9_15 | core_gpio[4] @ 0x41200000 | GPIO |
-| P9_16 | core_pwm[1] @ 0x41400000 | PWM_1:1 |
-| P9_17 | MSS SPI0 | SPI0 CS |
-| P9_18 | MSS SPI0 | SPI0 DI |
-| P9_19 | MSS I2C0 | I2C0 SCL |
-| P9_20 | MSS I2C0 | I2C0 SDA |
-| P9_21 | MSS SPI0 | SPI0 DO |
-| P9_22 | MSS SPI0 | SPI0 SCLK |
-| P9_23 | core_gpio[10] @ 0x41200000 | GPIO |
-| P9_24 | MMUART2 | UART1 TX |
-| P9_25 | core_gpio[12] @ 0x41200000 | GPIO |
-| P9_26 | MMUART2 | UART2 RX |
-| P9_27 | core_gpio[14] @ 0x41200000 | GPIO |
-| P9_28 | MSS SPI | SPI1 CS |
-| P9_29 | MSS SPI | SPI1 DO |
-| P9_30 | core_gpio[17] @ 0x41200000 | GPIO |
-| P9_31 | MSS SPI | SPI1 SCLK |
-| P9_32 | n/a | VDD ADC |
-| P9_33 | n/a | ADC input 4 |
-| P9_34 | n/a | AGND |
-| P9_35 | n/a | ADC input 6 |
-| P9_36 | n/a | ADC input 5 |
-| P9_37 | n/a | ADC input 2 |
-| P9_38 | n/a | ADC input 3 |
-| P9_39 | n/a | ADC input 0 |
-| P9_40 | n/a | ADC input 1 |
-| P9_41 | core_gpio[19] @ 0x41200000 | GPIO |
-| P9_42 | core_pwm[0] @ 0x41000000 | PWM_0:0 |
-| P9_43 | n/a | GND |
-| P9_44 | n/a | GND |
-| P9_45 | n/a | GND |
-| P9_46 | n/a | GND |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1 | n/a | n/a | GND |
+| P9_2 | n/a | n/a | GND |
+| P9_3 | n/a | n/a | VCC 3.3V |
+| P9_4 | n/a | n/a | VCC 3.3V |
+| P9_5 | n/a | n/a | VDD 5V |
+| P9_6 | n/a | n/a | VDD 5V |
+| P9_7 | n/a | n/a | SYS 5V |
+| P9_8 | n/a | n/a | SYS 5V |
+| P9_9 | n/a | n/a | NC |
+| P9_10 | n/a | n/a | SYS_RSTN |
+| P9_11 | MMUART4 | 94 | UART4 RX |
+| P9_12 | core_gpio[1] @ 0x41200000 | 143 | GPIO |
+| P9_13 | MMUART4 | 94 | UART4 TX |
+| P9_14 | core_pwm[0] @ 0x41400000 | n/a | PWM_1:0 |
+| P9_15 | core_gpio[4] @ 0x41200000 | 146 | GPIO |
+| P9_16 | core_pwm[1] @ 0x41400000 | n/a | PWM_1:1 |
+| P9_17 | MSS SPI0 | 54 | SPI0 CS |
+| P9_18 | MSS SPI0 | 54 | SPI0 DI |
+| P9_19 | MSS I2C0 | 58 | I2C0 SCL |
+| P9_20 | MSS I2C0 | 58 | I2C0 SDA |
+| P9_21 | MSS SPI0 | 54 | SPI0 DO |
+| P9_22 | MSS SPI0 | 54 | SPI0 SCLK |
+| P9_23 | core_gpio[10] @ 0x41200000 | 152 | GPIO |
+| P9_24 | MMUART2 | 92 | UART1 TX |
+| P9_25 | core_gpio[12] @ 0x41200000 | 154 | GPIO |
+| P9_26 | MMUART2 | 92 | UART2 RX |
+| P9_27 | core_gpio[14] @ 0x41200000 | 156 | GPIO |
+| P9_28 | MSS SPI1 | 55 | SPI1 CS |
+| P9_29 | MSS SPI1 | 55 | SPI1 DO |
+| P9_30 | core_gpio[17] @ 0x41200000 | 159 | GPIO |
+| P9_31 | MSS SPI1 | 55 | SPI1 SCLK |
+| P9_32 | n/a | n/a | VDD ADC |
+| P9_33 | n/a | n/a | ADC input 4 |
+| P9_34 | n/a | n/a | AGND |
+| P9_35 | n/a | n/a | ADC input 6 |
+| P9_36 | n/a | n/a | ADC input 5 |
+| P9_37 | n/a | n/a | ADC input 2 |
+| P9_38 | n/a | n/a | ADC input 3 |
+| P9_39 | n/a | n/a | ADC input 0 |
+| P9_40 | n/a | n/a | ADC input 1 |
+| P9_41 | core_gpio[19] @ 0x41200000 | 161 | GPIO |
+| P9_42 | core_pwm[0] @ 0x41000000 | n/a | PWM_0:0 |
+| P9_43 | n/a | n/a | GND |
+| P9_44 | n/a | n/a | GND |
+| P9_45 | n/a | n/a | GND |
+| P9_46 | n/a | n/a | GND |
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
index 331f13f79ed0c6d11b655030cbf6e6c5ec64e0ca..62de4820177dd1c2c612c554c2016e33a984bdcf 100644
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
@@ -4,12 +4,12 @@ puts "======== Add cape option: GPIOS ========"
# Build cape's submodules
#-------------------------------------------------------------------------------
source script_support/components/CAPE/GPIOS/APB_BUS_CONVERTER.tcl
+source script_support/components/CAPE/DEFAULT/CoreAPB3_CAPE.tcl
source script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
-source script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/GPIOS/P8_GPIO_UPPER.tcl
source script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl
source script_support/components/CAPE/GPIOS/P9_GPIO.tcl
source script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
-#source script_support/components/CAPE/GPIOS/CAPE_PWM.tcl
source script_support/components/CAPE/GPIOS/CAPE.tcl
#-------------------------------------------------------------------------------
@@ -20,11 +20,10 @@ set sd_name ${top_level_name}
#-------------------------------------------------------------------------------
# Cape pins
#-------------------------------------------------------------------------------
-#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_19} -port_direction {OUT}
-
sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
+
#-------------------------------------------------------------------------------
# Instantiate.
#-------------------------------------------------------------------------------
@@ -46,9 +45,21 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M"
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"}
-
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D" "CAPE:INT_D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E" "CAPE:INT_E"}
+
+
+
sd_delete_ports -sd_name ${sd_name} -port_names {P9_11}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
sd_delete_ports -sd_name ${sd_name} -port_names {P9_13}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE.tcl
index 8e1424285f5dfcb04fee020d7882f56d17c651ce..82405d610c58df2eaa0ddd092ac3eb200591aacd 100644
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE.tcl
@@ -1,138 +1,233 @@
-# Creating SmartDesign CAPE
+# Creating SmartDesign "CAPE"
set sd_name {CAPE}
create_smartdesign -sd_name ${sd_name}
-#-------------------------------------------------------------------------------
-# Create APB Bus
-#-------------------------------------------------------------------------------
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:false" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:true" "APBSLOT3ENABLE:false" \
-"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
-"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
-"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
-"APB_DWIDTH:32" \
-"IADDR_OPTION:0" \
-"MADDR_BITS:24" \
-"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
-"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
-"SC_12:false" "SC_13:false" "SC_14:false" \
-"SC_15:false" \
-"UPR_NIBBLE_POSN:5"}
-
-sd_instantiate_component -sd_name {CAPE} -component_name {CoreAPB3_CAPE} -instance_name {}
-
-#-------------------------------------------------------------------------------
-# Create APB Bus Converter
-#-------------------------------------------------------------------------------
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN10_USER_LED_7} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN11_USER_LED_8} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN12_USER_LED_9} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN14_USER_LED_11} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN16} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN17} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN18} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN19} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN20} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN21} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN22} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN24} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN26} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN28} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN29} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN31} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN3_USER_LED_0} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN4_USER_LED_1} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN5_USER_LED_2} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN6_USER_LED_3} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN7_USER_LED_4} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN8_USER_LED_5} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN9_USER_LED_6} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN11} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN12} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN13} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN17} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN18} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN21} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN22} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN24} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN26} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN28} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN29} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN31} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN41} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PADDR} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWDATA} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_A} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_B} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_C} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_D} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_E} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_SLAVE_SLAVE_PADDR" \
+"PSELx:APB_SLAVE_SLAVE_PSEL" \
+"PENABLE:APB_SLAVE_SLAVE_PENABLE" \
+"PWRITE:APB_SLAVE_SLAVE_PWRITE" \
+"PRDATA:APB_SLAVE_SLAVE_PRDATA" \
+"PWDATA:APB_SLAVE_SLAVE_PWDATA" \
+"PREADY:APB_SLAVE_SLAVE_PREADY" \
+"PSLVERR:APB_SLAVE_SLAVE_PSLVERR" }
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[4:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[7:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {INT_E[7:5]} -value {GND}
+# Add APB_BUS_CONVERTER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
-#-------------------------------------------------------------------------------
-# Add Default Cape GPIOs
-#-------------------------------------------------------------------------------
+
+
+# Add CAPE_DEFAULT_GPIOS instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OUT} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN3_USER_LED_0}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN4_USER_LED_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN5_USER_LED_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN6_USER_LED_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN7_USER_LED_4}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN8_USER_LED_5}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN9_USER_LED_6}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN10_USER_LED_7}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN11_USER_LED_8}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN12_USER_LED_9}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN13_USER_LED_10}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN14_USER_LED_11}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P8_PIN19}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P8_PIN20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P8_PIN21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P8_PIN22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P8_PIN23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P8_PIN24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P8_PIN25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P8_PIN26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P8_PIN27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P8_PIN28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P8_PIN29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_PIN30}
-
-
-#-------------------------------------------------------------------------------
-# P8
-#-------------------------------------------------------------------------------
+
+
+# Add CoreAPB3_CAPE_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -instance_name {CoreAPB3_CAPE_0}
+
+
+
+# Add P8_GPIO_UPPER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[7:0]}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PCLK} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN46}
-
-#-------------------------------------------------------------------------------
-# P9
-#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P9_PIN11}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P9_PIN12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P9_PIN13}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P9_PIN14}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P9_PIN15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P9_PIN16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P9_PIN17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P9_PIN18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P9_PIN21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P9_PIN22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P9_PIN23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_PIN24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_PIN25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_PIN26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_PIN27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_PIN28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_PIN29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_PIN30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_PIN31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_PIN41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_PIN42}
-
-#-------------------------------------------------------------------------------
-# Connections
-#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "P9_GPIO_0:PRESETN"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "P9_GPIO_0:PCLK"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave2"}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"}
+# Add P9_GPIO_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[20:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[7:0]}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_0_PAD" "P8_PIN3_USER_LED_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_10_PAD" "P8_PIN13_USER_LED_10" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_11_PAD" "P8_PIN14_USER_LED_11" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_12_PAD" "P8_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_13_PAD" "P8_PIN16" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_14_PAD" "P8_PIN17" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_15_PAD" "P8_PIN18" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_16_PAD" "P8_PIN19" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_17_PAD" "P8_PIN20" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_18_PAD" "P8_PIN21" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_19_PAD" "P8_PIN22" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_1_PAD" "P8_PIN4_USER_LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_20_PAD" "P8_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_21_PAD" "P8_PIN24" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_22_PAD" "P8_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_23_PAD" "P8_PIN26" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_24_PAD" "P8_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_25_PAD" "P8_PIN28" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_26_PAD" "P8_PIN29" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_27_PAD" "P8_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_2_PAD" "P8_PIN5_USER_LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_3_PAD" "P8_PIN6_USER_LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_4_PAD" "P8_PIN7_USER_LED_4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_5_PAD" "P8_PIN8_USER_LED_5" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_6_PAD" "P8_PIN9_USER_LED_6" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_7_PAD" "P8_PIN10_USER_LED_7" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_8_PAD" "P8_PIN11_USER_LED_8" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_9_PAD" "P8_PIN12_USER_LED_9" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_0_PAD" "P8_PIN31" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_10_PAD" "P8_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_11_PAD" "P8_PIN42" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_12_PAD" "P8_PIN43" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_13_PAD" "P8_PIN44" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_14_PAD" "P8_PIN45" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_15_PAD" "P8_PIN46" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_1_PAD" "P8_PIN32" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_2_PAD" "P8_PIN33" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_3_PAD" "P8_PIN34" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_4_PAD" "P8_PIN35" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_5_PAD" "P8_PIN36" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_6_PAD" "P8_PIN37" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_7_PAD" "P8_PIN38" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_8_PAD" "P8_PIN39" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_9_PAD" "P8_PIN40" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PCLK" "P9_GPIO_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PRESETN" "P9_GPIO_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_0_PAD" "P9_PIN11" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_10_PAD" "P9_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_11_PAD" "P9_PIN24" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_12_PAD" "P9_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_13_PAD" "P9_PIN26" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_14_PAD" "P9_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_15_PAD" "P9_PIN28" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_16_PAD" "P9_PIN29" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_17_PAD" "P9_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_18_PAD" "P9_PIN31" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_19_PAD" "P9_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_1_PAD" "P9_PIN12" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_20_PAD" "P9_PIN42" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_2_PAD" "P9_PIN13" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_3_PAD" "P9_PIN14" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_4_PAD" "P9_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_5_PAD" "P9_PIN16" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_6_PAD" "P9_PIN17" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_7_PAD" "P9_PIN18" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_8_PAD" "P9_PIN21" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_9_PAD" "P9_PIN22" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_A" "P8_GPIO_UPPER_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_B" "P8_GPIO_UPPER_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_C" "P9_GPIO_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_D" "P9_GPIO_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_E[4:0]" "P9_GPIO_0:INT[20:16]" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_SLAVE" "APB_SLAVE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave1" "P8_GPIO_UPPER_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave2" "P9_GPIO_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
+# Generate SmartDesign "CAPE"
generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE_PWM.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE_PWM.tcl
deleted file mode 100644
index aaffab1d8a949287fc27347eadefabe99eccd13d..0000000000000000000000000000000000000000
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/CAPE_PWM.tcl
+++ /dev/null
@@ -1,72 +0,0 @@
-# Creating SmartDesign CAPE_PWM
-set sd_name {CAPE_PWM}
-create_smartdesign -sd_name ${sd_name}
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
-"APB_DWIDTH:32" "CONFIG_MODE:0" \
-"DAC_MODE1:false" "DAC_MODE2:false" "DAC_MODE3:false" "DAC_MODE4:false" "DAC_MODE5:false" \
-"DAC_MODE6:false" "DAC_MODE7:false" "DAC_MODE8:false" "DAC_MODE9:false" "DAC_MODE10:false" \
-"DAC_MODE11:false" "DAC_MODE12:false" "DAC_MODE13:false" "DAC_MODE14:false" "DAC_MODE15:false" \
-"DAC_MODE16:false" \
-"FIXED_PERIOD:1" "FIXED_PERIOD_EN:false" "FIXED_PRESCALE:0" "FIXED_PRESCALE_EN:false" \
-"FIXED_PWM_NEGEDGE1:0" "FIXED_PWM_NEGEDGE2:0" "FIXED_PWM_NEGEDGE3:0" "FIXED_PWM_NEGEDGE4:0" "FIXED_PWM_NEGEDGE5:0" \
-"FIXED_PWM_NEGEDGE6:0" "FIXED_PWM_NEGEDGE7:0" "FIXED_PWM_NEGEDGE8:0" "FIXED_PWM_NEGEDGE9:0" "FIXED_PWM_NEGEDGE10:0" \
-"FIXED_PWM_NEGEDGE11:0" "FIXED_PWM_NEGEDGE12:0" "FIXED_PWM_NEGEDGE13:0" "FIXED_PWM_NEGEDGE14:0" "FIXED_PWM_NEGEDGE15:0" \
-"FIXED_PWM_NEGEDGE16:0" \
-"FIXED_PWM_NEG_EN1:false" "FIXED_PWM_NEG_EN2:false" "FIXED_PWM_NEG_EN3:false" "FIXED_PWM_NEG_EN4:false" "FIXED_PWM_NEG_EN5:false" \
-"FIXED_PWM_NEG_EN6:false" "FIXED_PWM_NEG_EN7:false" "FIXED_PWM_NEG_EN8:false" "FIXED_PWM_NEG_EN9:false" "FIXED_PWM_NEG_EN10:false" \
-"FIXED_PWM_NEG_EN11:false" "FIXED_PWM_NEG_EN12:false" "FIXED_PWM_NEG_EN13:false" "FIXED_PWM_NEG_EN14:false" "FIXED_PWM_NEG_EN15:false" \
-"FIXED_PWM_NEG_EN16:false" \
-"FIXED_PWM_POSEDGE1:0" "FIXED_PWM_POSEDGE2:0" "FIXED_PWM_POSEDGE3:0" "FIXED_PWM_POSEDGE4:0" "FIXED_PWM_POSEDGE5:0" \
-"FIXED_PWM_POSEDGE6:0" "FIXED_PWM_POSEDGE7:0" "FIXED_PWM_POSEDGE8:0" "FIXED_PWM_POSEDGE9:0" "FIXED_PWM_POSEDGE10:0" \
-"FIXED_PWM_POSEDGE11:0" "FIXED_PWM_POSEDGE12:0" "FIXED_PWM_POSEDGE13:0" "FIXED_PWM_POSEDGE14:0" "FIXED_PWM_POSEDGE15:0" \
-"FIXED_PWM_POSEDGE16:0" \
-"FIXED_PWM_POS_EN1:false" "FIXED_PWM_POS_EN2:false" "FIXED_PWM_POS_EN3:false" "FIXED_PWM_POS_EN4:false" "FIXED_PWM_POS_EN5:false" \
-"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
-"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
-"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:4" \
-"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
-"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
-"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
-"PWM_STRETCH_VALUE16:false" \
-"SEPARATE_PWM_CLK:false" \
-"SHADOW_REG_EN1:false" "SHADOW_REG_EN2:false" "SHADOW_REG_EN3:false" "SHADOW_REG_EN4:false" "SHADOW_REG_EN5:false" \
-"SHADOW_REG_EN6:false" "SHADOW_REG_EN7:false" "SHADOW_REG_EN8:false" "SHADOW_REG_EN9:false" \
-"SHADOW_REG_EN10:false" "SHADOW_REG_EN11:false" "SHADOW_REG_EN12:false" "SHADOW_REG_EN13:false" \
-"SHADOW_REG_EN14:false" "SHADOW_REG_EN15:false" "SHADOW_REG_EN16:false" \
-"TACHINT_ACT_LEVEL:false" \
-"TACH_EDGE1:false" "TACH_EDGE2:false" "TACH_EDGE3:false" "TACH_EDGE4:false" "TACH_EDGE5:false" \
-"TACH_EDGE6:false" "TACH_EDGE7:false" "TACH_EDGE8:false" "TACH_EDGE9:false" "TACH_EDGE10:false" \
-"TACH_EDGE11:false" "TACH_EDGE12:false" "TACH_EDGE13:false" "TACH_EDGE14:false" "TACH_EDGE15:false" \
-"TACH_EDGE16:false" \
-"TACH_NUM:1"}
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[0:0]"}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PWM} -new_port_name {PWM_0}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE_PWM
-generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/CoreAPB3_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/CoreAPB3_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ab9b81e998527110100572f6008a0373b7ecbfe8
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/CoreAPB3_CAPE.tcl
@@ -0,0 +1,42 @@
+# Exporting Component Description of CoreAPB3_CAPE to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreAPB3_CAPE
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APB_DWIDTH:32" \
+"APBSLOT0ENABLE:true" \
+"APBSLOT1ENABLE:true" \
+"APBSLOT2ENABLE:true" \
+"APBSLOT3ENABLE:false" \
+"APBSLOT4ENABLE:true" \
+"APBSLOT5ENABLE:true" \
+"APBSLOT6ENABLE:false" \
+"APBSLOT7ENABLE:false" \
+"APBSLOT8ENABLE:false" \
+"APBSLOT9ENABLE:false" \
+"APBSLOT10ENABLE:false" \
+"APBSLOT11ENABLE:false" \
+"APBSLOT12ENABLE:false" \
+"APBSLOT13ENABLE:false" \
+"APBSLOT14ENABLE:false" \
+"APBSLOT15ENABLE:false" \
+"IADDR_OPTION:0" \
+"MADDR_BITS:24" \
+"SC_0:false" \
+"SC_1:false" \
+"SC_2:false" \
+"SC_3:false" \
+"SC_4:false" \
+"SC_5:false" \
+"SC_6:false" \
+"SC_7:false" \
+"SC_8:false" \
+"SC_9:false" \
+"SC_10:false" \
+"SC_11:false" \
+"SC_12:false" \
+"SC_13:false" \
+"SC_14:false" \
+"SC_15:false" \
+"UPR_NIBBLE_POSN:5" }
+# Exporting Component Description of CoreAPB3_CAPE to TCL done
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
deleted file mode 100644
index d14a5aeac101fc0be8e7a50715be09ee78dcf8e8..0000000000000000000000000000000000000000
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
+++ /dev/null
@@ -1,174 +0,0 @@
-# Creating SmartDesign P8_GPIO_UPPER
-set sd_name {P8_GPIO_UPPER}
-create_smartdesign -sd_name ${sd_name}
-
-auto_promote_pad_pins -promote_all 1
-
-# Add GPIO BIBUFs
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
-
-
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[0:0]"}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
-
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:APB_bif} -port_name {}
-
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:INT}
-
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P8_GPIO_UPPER
-generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_UPPER.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_UPPER.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c162d804156e0190274d77127a0241de7f353bfb
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/P8_GPIO_UPPER.tcl
@@ -0,0 +1,266 @@
+# Creating SmartDesign "P8_GPIO_UPPER"
+set sd_name {P8_GPIO_UPPER}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_0_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_11_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_13_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_15_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_2_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_3_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_5_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_6_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_7_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_8_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_9_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[15:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" }
+
+# Add CoreGPIO_P8_UPPER_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {CoreGPIO_P8_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[9:9]}
+
+
+
+# Add GPIO_0_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+
+
+
+# Add GPIO_1_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_2_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+
+
+
+# Add GPIO_3_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_5_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+
+
+
+# Add GPIO_6_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+
+
+
+# Add GPIO_7_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+
+
+
+# Add GPIO_8_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+
+
+
+# Add GPIO_9_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_11_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_13_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_15_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_0_BIBUF:PAD" "GPIO_0_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_11_BIBUF:PAD" "GPIO_11_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_13_BIBUF:PAD" "GPIO_13_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_15_BIBUF:PAD" "GPIO_15_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_BIBUF:PAD" "GPIO_2_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_3_BIBUF:PAD" "GPIO_3_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_5_BIBUF:PAD" "GPIO_5_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_6_BIBUF:PAD" "GPIO_6_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_7_BIBUF:PAD" "GPIO_7_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_8_BIBUF:PAD" "GPIO_8_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_9_BIBUF:PAD" "GPIO_9_PAD" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:INT" "INT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P8_UPPER_0:APB_bif" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the SmartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign "P8_GPIO_UPPER"
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/P9_GPIO.tcl b/sources/FPGA-design/script_support/components/CAPE/GPIOS/P9_GPIO.tcl
index 0230e58ff248d468856b2b9158335373746cc6f1..80a11faa766fbe046c04006a5a8e38be079855dd 100644
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/P9_GPIO.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/P9_GPIO.tcl
@@ -1,220 +1,331 @@
-# Creating SmartDesign P9_GPIO
+# Creating SmartDesign "P9_GPIO"
set sd_name {P9_GPIO}
create_smartdesign -sd_name ${sd_name}
-auto_promote_pad_pins -promote_all 1
-
-# Add GPIO BIBUFs
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_0_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_11_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_13_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_15_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_16_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_17_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_18_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_19_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_20_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_2_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_3_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_5_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_6_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_7_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_8_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_9_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[20:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" }
+
+# Add CoreGPIO_P9_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P9} -instance_name {CoreGPIO_P9_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[9:9]}
+
+
+
+# Add GPIO_0_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+
+
+
+# Add GPIO_1_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_2_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+
+
+
+# Add GPIO_3_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_5_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+
+
+
+# Add GPIO_6_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+
+
+
+# Add GPIO_7_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+
+
+
+# Add GPIO_8_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+
+
+
+# Add GPIO_9_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_11_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_13_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_15_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+
+# Add GPIO_16_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_16_BIBUF}
+
+
+
+# Add GPIO_17_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
+
+
+
+# Add GPIO_18_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_18_BIBUF}
+
+
+
+# Add GPIO_19_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
+
+
+
+# Add GPIO_20_BIBUF instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_20_BIBUF}
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P9} -instance_name {}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[20:20]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[20:20]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[20:20]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[0:0]"}
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[16:16]" "GPIO_16_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[16:16]" "GPIO_16_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[16:16]" "GPIO_16_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[17:17]" "GPIO_17_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[17:17]" "GPIO_17_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[17:17]" "GPIO_17_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[18:18]" "GPIO_18_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[18:18]" "GPIO_18_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[18:18]" "GPIO_18_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[19:19]" "GPIO_19_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[19:19]" "GPIO_19_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[19:19]" "GPIO_19_BIBUF:E"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[20:20]" "GPIO_20_BIBUF:D"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[20:20]" "GPIO_20_BIBUF:Y"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[20:20]" "GPIO_20_BIBUF:E"}
-
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_15} -new_port_name {GPIO_16_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_16} -new_port_name {GPIO_17_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_17} -new_port_name {GPIO_18_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_18} -new_port_name {GPIO_19_PAD}
-sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_19} -new_port_name {GPIO_20_PAD}
-
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:APB_bif} -port_name {}
-
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:INT}
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[16:16]" "GPIO_16_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[17:17]" "GPIO_17_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[18:18]" "GPIO_18_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[19:19]" "GPIO_19_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[20:20]" "GPIO_20_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[16:16]" "GPIO_16_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[17:17]" "GPIO_17_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[18:18]" "GPIO_18_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[19:19]" "GPIO_19_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[20:20]" "GPIO_20_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[16:16]" "GPIO_16_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[17:17]" "GPIO_17_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[18:18]" "GPIO_18_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[19:19]" "GPIO_19_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[20:20]" "GPIO_20_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_0_BIBUF:PAD" "GPIO_0_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_11_BIBUF:PAD" "GPIO_11_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_13_BIBUF:PAD" "GPIO_13_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_15_BIBUF:PAD" "GPIO_15_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_16_BIBUF:PAD" "GPIO_16_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_17_BIBUF:PAD" "GPIO_17_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_18_BIBUF:PAD" "GPIO_18_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_19_BIBUF:PAD" "GPIO_19_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_20_BIBUF:PAD" "GPIO_20_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_BIBUF:PAD" "GPIO_2_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_3_BIBUF:PAD" "GPIO_3_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_5_BIBUF:PAD" "GPIO_5_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_6_BIBUF:PAD" "GPIO_6_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_7_BIBUF:PAD" "GPIO_7_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_8_BIBUF:PAD" "GPIO_8_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_9_BIBUF:PAD" "GPIO_9_PAD" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:INT" "INT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P9_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P9_GPIO
+# Generate SmartDesign "P9_GPIO"
generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/GPIOS/Readme.md b/sources/FPGA-design/script_support/components/CAPE/GPIOS/Readme.md
index 2d43b13058bd61b8989bdf4b5fffd4890f0942c2..1241367ee125d732a3cf4de59242d23446080f9b 100644
--- a/sources/FPGA-design/script_support/components/CAPE/GPIOS/Readme.md
+++ b/sources/FPGA-design/script_support/components/CAPE/GPIOS/Readme.md
@@ -2,102 +2,102 @@
## P8 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P8_1 | n/a | GND |
-| P8_2 | n/a | GND |
-| P8_3 | MSS GPIO_2[0] | User LED 0 |
-| P8_4 | MSS GPIO_2[1] | User LED 1 |
-| P8_5 | MSS GPIO_2[2] | User LED 2 |
-| P8_6 | MSS GPIO_2[3] | User LED 3 |
-| P8_7 | MSS GPIO_2[4] | User LED 4 |
-| P8_8 | MSS GPIO_2[5] | User LED 5 |
-| P8_9 | MSS GPIO_2[6] | User LED 6 |
-| P8_10 | MSS GPIO_2[7] | User LED 7 |
-| P8_11 | MSS GPIO_2[8] | User LED 8 |
-| P8_12 | MSS GPIO_2[9] | User LED 9 |
-| P8_13 | MSS GPIO_2[10] | User LED 10 |
-| P8_14 | MSS GPIO_2[11] | User LED 11 |
-| P8_15 | MSS GPIO_2[12] | GPIO |
-| P8_16 | MSS GPIO_2[13] | GPIO |
-| P8_17 | MSS GPIO_2[14] | GPIO |
-| P8_18 | MSS GPIO_2[15] | GPIO |
-| P8_19 | MSS GPIO_2[16] | GPIO |
-| P8_20 | MSS GPIO_2[17] | GPIO |
-| P8_21 | MSS GPIO_2[18] | GPIO |
-| P8_22 | MSS GPIO_2[19] | GPIO |
-| P8_23 | MSS GPIO_2[20] | GPIO |
-| P8_24 | MSS GPIO_2[21] | GPIO |
-| P8_25 | MSS GPIO_2[22] | GPIO |
-| P8_26 | MSS GPIO_2[23] | GPIO |
-| P8_27 | MSS GPIO_2[24] | GPIO |
-| P8_28 | MSS GPIO_2[25] | GPIO |
-| P8_29 | MSS GPIO_2[26] | GPIO |
-| P8_30 | MSS GPIO_2[27] | GPIO |
-| P8_31 | core_gpio[0] @ 0x41100000 | GPIO |
-| P8_32 | core_gpio[1] @ 0x41100000 | GPIO |
-| P8_33 | core_gpio[2] @ 0x41100000 | GPIO |
-| P8_34 | core_gpio[3] @ 0x41100000 | GPIO |
-| P8_35 | core_gpio[4] @ 0x41100000 | GPIO |
-| P8_36 | core_gpio[5] @ 0x41100000 | GPIO |
-| P8_37 | core_gpio[6] @ 0x41100000 | GPIO |
-| P8_38 | core_gpio[7] @ 0x41100000 | GPIO |
-| P8_39 | core_gpio[8] @ 0x41100000 | GPIO |
-| P8_40 | core_gpio[9] @ 0x41100000 | GPIO |
-| P8_41 | core_gpio[10] @ 0x41100000 | GPIO |
-| P8_42 | core_gpio[11] @ 0x41100000 | GPIO |
-| P8_43 | core_gpio[12] @ 0x41100000 | GPIO |
-| P8_44 | core_gpio[13] @ 0x41100000 | GPIO |
-| P8_45 | core_gpio[14] @ 0x41100000 | GPIO |
-| P8_46 | core_gpio[15] @ 0x41100000 | GPIO |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1 | n/a | n/a | GND |
+| P8_2 | n/a | n/a | GND |
+| P8_3 | MSS GPIO_2[0] | 53 | User LED 0 |
+| P8_4 | MSS GPIO_2[1] | 53 | User LED 1 |
+| P8_5 | MSS GPIO_2[2] | 53 | User LED 2 |
+| P8_6 | MSS GPIO_2[3] | 53 | User LED 3 |
+| P8_7 | MSS GPIO_2[4] | 53 | User LED 4 |
+| P8_8 | MSS GPIO_2[5] | 53 | User LED 5 |
+| P8_9 | MSS GPIO_2[6] | 53 | User LED 6 |
+| P8_10 | MSS GPIO_2[7] | 53 | User LED 7 |
+| P8_11 | MSS GPIO_2[8] | 53 | User LED 8 |
+| P8_12 | MSS GPIO_2[9] | 53 | User LED 9 |
+| P8_13 | MSS GPIO_2[10] | 53 | User LED 10 |
+| P8_14 | MSS GPIO_2[11] | 53 | User LED 11 |
+| P8_15 | MSS GPIO_2[12] | 53 | GPIO |
+| P8_16 | MSS GPIO_2[13] | 53 | GPIO |
+| P8_17 | MSS GPIO_2[14] | 53 | GPIO |
+| P8_18 | MSS GPIO_2[15] | 53 | GPIO |
+| P8_19 | MSS GPIO_2[16] | 53 | GPIO |
+| P8_20 | MSS GPIO_2[17] | 53 | GPIO |
+| P8_21 | MSS GPIO_2[18] | 53 | GPIO |
+| P8_22 | MSS GPIO_2[19] | 53 | GPIO |
+| P8_23 | MSS GPIO_2[20] | 53 | GPIO |
+| P8_24 | MSS GPIO_2[21] | 53 | GPIO |
+| P8_25 | MSS GPIO_2[22] | 53 | GPIO |
+| P8_26 | MSS GPIO_2[23] | 53 | GPIO |
+| P8_27 | MSS GPIO_2[24] | 53 | GPIO |
+| P8_28 | MSS GPIO_2[25] | 53 | GPIO |
+| P8_29 | MSS GPIO_2[26] | 53 | GPIO |
+| P8_30 | MSS GPIO_2[27] | 53 | GPIO |
+| P8_31 | core_gpio[0] @ 0x41100000 | 126 | GPIO |
+| P8_32 | core_gpio[1] @ 0x41100000 | 127 | GPIO |
+| P8_33 | core_gpio[2] @ 0x41100000 | 128 | GPIO |
+| P8_34 | core_gpio[3] @ 0x41100000 | 129 | GPIO |
+| P8_35 | core_gpio[4] @ 0x41100000 | 130 | GPIO |
+| P8_36 | core_gpio[5] @ 0x41100000 | 131 | GPIO |
+| P8_37 | core_gpio[6] @ 0x41100000 | 132 | GPIO |
+| P8_38 | core_gpio[7] @ 0x41100000 | 133 | GPIO |
+| P8_39 | core_gpio[8] @ 0x41100000 | 134 | GPIO |
+| P8_40 | core_gpio[9] @ 0x41100000 | 135 | GPIO |
+| P8_41 | core_gpio[10] @ 0x41100000 | 136 | GPIO |
+| P8_42 | core_gpio[11] @ 0x41100000 | 137 | GPIO |
+| P8_43 | core_gpio[12] @ 0x41100000 | 138 | GPIO |
+| P8_44 | core_gpio[13] @ 0x41100000 | 139 | GPIO |
+| P8_45 | core_gpio[14] @ 0x41100000 | 140 | GPIO |
+| P8_46 | core_gpio[15] @ 0x41100000 | 141 | GPIO |
## P9 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P9_1 | n/a | GND |
-| P9_2 | n/a | GND |
-| P9_3 | n/a | VCC 3.3V |
-| P9_4 | n/a | VCC 3.3V |
-| P9_5 | n/a | VDD 5V |
-| P9_6 | n/a | VDD 5V |
-| P9_7 | n/a | SYS 5V |
-| P9_8 | n/a | SYS 5V |
-| P9_9 | n/a | NC |
-| P9_10 | n/a | SYS_RSTN |
-| P9_11 | core_gpio[0] @ 0x41200000 | GPIO |
-| P9_12 | core_gpio[1] @ 0x41200000 | GPIO |
-| P9_13 | core_gpio[2] @ 0x41200000 | GPIO |
-| P9_14 | core_gpio[3] @ 0x41200000 | GPIO |
-| P9_15 | core_gpio[4] @ 0x41200000 | GPIO |
-| P9_16 | core_gpio[5] @ 0x41200000 | GPIO |
-| P9_17 | core_gpio[6] @ 0x41200000 | GPIO |
-| P9_18 | core_gpio[7] @ 0x41200000 | GPIO |
-| P9_19 | MSS I2C0 | I2C0 SCL |
-| P9_20 | MSS I2C0 | I2C0 SDA |
-| P9_21 | core_gpio[8] @ 0x41200000 | GPIO |
-| P9_22 | core_gpio[9] @ 0x41200000 | GPIO |
-| P9_23 | core_gpio[10] @ 0x41200000 | GPIO |
-| P9_24 | core_gpio[11] @ 0x41200000 | GPIO |
-| P9_25 | core_gpio[12] @ 0x41200000 | GPIO |
-| P9_26 | core_gpio[13] @ 0x41200000 | GPIO |
-| P9_27 | core_gpio[14] @ 0x41200000 | GPIO |
-| P9_28 | core_gpio[15] @ 0x41200000 | GPIO |
-| P9_29 | core_gpio[16] @ 0x41200000 | GPIO |
-| P9_30 | core_gpio[17] @ 0x41200000 | GPIO |
-| P9_31 | core_gpio[18] @ 0x41200000 | GPIO |
-| P9_32 | n/a | VDD ADC |
-| P9_33 | n/a | ADC input 4 |
-| P9_34 | n/a | AGND |
-| P9_35 | n/a | ADC input 6 |
-| P9_36 | n/a | ADC input 5 |
-| P9_37 | n/a | ADC input 2 |
-| P9_38 | n/a | ADC input 3 |
-| P9_39 | n/a | ADC input 0 |
-| P9_40 | n/a | ADC input 1 |
-| P9_41 | core_gpio[19] @ 0x41200000 | GPIO |
-| P9_42 | core_gpio[20] @ 0x41200000 | GPIO |
-| P9_43 | n/a | GND |
-| P9_44 | n/a | GND |
-| P9_45 | n/a | GND |
-| P9_46 | n/a | GND |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1 | n/a | n/a | GND |
+| P9_2 | n/a | n/a | GND |
+| P9_3 | n/a | n/a | VCC 3.3V |
+| P9_4 | n/a | n/a | VCC 3.3V |
+| P9_5 | n/a | n/a | VDD 5V |
+| P9_6 | n/a | n/a | VDD 5V |
+| P9_7 | n/a | n/a | SYS 5V |
+| P9_8 | n/a | n/a | SYS 5V |
+| P9_9 | n/a | n/a | NC |
+| P9_10 | n/a | n/a | SYS_RSTN |
+| P9_11 | core_gpio[0] @ 0x41200000 | 142 | GPIO |
+| P9_12 | core_gpio[1] @ 0x41200000 | 143 | GPIO |
+| P9_13 | core_gpio[2] @ 0x41200000 | 144 | GPIO |
+| P9_14 | core_gpio[3] @ 0x41200000 | 145 | GPIO |
+| P9_15 | core_gpio[4] @ 0x41200000 | 146 | GPIO |
+| P9_16 | core_gpio[5] @ 0x41200000 | 147 | GPIO |
+| P9_17 | core_gpio[6] @ 0x41200000 | 148 | GPIO |
+| P9_18 | core_gpio[7] @ 0x41200000 | 149 | GPIO |
+| P9_19 | MSS I2C0 | 58 | I2C0 SCL |
+| P9_20 | MSS I2C0 | 58 | I2C0 SDA |
+| P9_21 | core_gpio[8] @ 0x41200000 | 150 | GPIO |
+| P9_22 | core_gpio[9] @ 0x41200000 | 151 | GPIO |
+| P9_23 | core_gpio[10] @ 0x41200000 | 152 | GPIO |
+| P9_24 | core_gpio[11] @ 0x41200000 | 153 | GPIO |
+| P9_25 | core_gpio[12] @ 0x41200000 | 154 | GPIO |
+| P9_26 | core_gpio[13] @ 0x41200000 | 155 | GPIO |
+| P9_27 | core_gpio[14] @ 0x41200000 | 156 | GPIO |
+| P9_28 | core_gpio[15] @ 0x41200000 | 157 | GPIO |
+| P9_29 | core_gpio[16] @ 0x41200000 | 158 | GPIO |
+| P9_30 | core_gpio[17] @ 0x41200000 | 159 | GPIO |
+| P9_31 | core_gpio[18] @ 0x41200000 | 160 | GPIO |
+| P9_32 | n/a | n/a | VDD ADC |
+| P9_33 | n/a | n/a | ADC input 4 |
+| P9_34 | n/a | n/a | AGND |
+| P9_35 | n/a | n/a | ADC input 6 |
+| P9_36 | n/a | n/a | ADC input 5 |
+| P9_37 | n/a | n/a | ADC input 2 |
+| P9_38 | n/a | n/a | ADC input 3 |
+| P9_39 | n/a | n/a | ADC input 0 |
+| P9_40 | n/a | n/a | ADC input 1 |
+| P9_41 | core_gpio[19] @ 0x41200000 | 161 | GPIO |
+| P9_42 | core_gpio[20] @ 0x41200000 | 162 | GPIO |
+| P9_43 | n/a | n/a | GND |
+| P9_44 | n/a | n/a | GND |
+| P9_45 | n/a | n/a | GND |
+| P9_46 | n/a | n/a | GND |
diff --git a/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/ADD_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4e63d8f89276ba979324434931018b89a37ddf6d
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/ADD_CAPE.tcl
@@ -0,0 +1,33 @@
+puts "======== Add cape option: NONE ========"
+
+set sd_name ${top_level_name}
+
+#-------------------------------------------------------------------------------
+# Cape pins
+#-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
+
+
+#-------------------------------------------------------------------------------
+# Instantiate.
+#-------------------------------------------------------------------------------
+
+#-------------------------------------------------------------------------------
+# Connections.
+#-------------------------------------------------------------------------------
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_TXD" "P9_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_RXD" "P9_11"}
+
+#-------------------------------------------------------------------------------
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET}
+
+#-------------------------------------------------------------------------------
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:GPIO_2_F2M} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_INITIATOR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_TARGET}
+
diff --git a/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/Readme.md b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/Readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..d1c9427346271a49b6dd50d9793c5ef432e686b0
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/Readme.md
@@ -0,0 +1,105 @@
+# Minimal Cape, No USer LEDs
+
+This cape configuration is intended for use where some other part of the gateware will use the LEDs.
+
+## P8 Header
+
+| Signal | Control | Description |
+|--------|----------------------------|-------------|
+| P8_1 | n/a | GND |
+| P8_2 | n/a | GND |
+| P8_3 | n/a | NC |
+| P8_4 | n/a | NC |
+| P8_5 | n/a | NC |
+| P8_6 | n/a | NC |
+| P8_7 | n/a | NC |
+| P8_8 | n/a | NC |
+| P8_9 | n/a | NC |
+| P8_10 | n/a | NC |
+| P8_11 | n/a | NC |
+| P8_12 | n/a | NC |
+| P8_13 | n/a | NC |
+| P8_14 | n/a | NC |
+| P8_15 | n/a | NC |
+| P8_16 | n/a | NC |
+| P8_17 | n/a | NC |
+| P8_18 | n/a | NC |
+| P8_19 | n/a | NC |
+| P8_20 | n/a | NC |
+| P8_21 | n/a | NC |
+| P8_22 | n/a | NC |
+| P8_23 | n/a | NC |
+| P8_24 | n/a | NC |
+| P8_25 | n/a | NC |
+| P8_26 | n/a | NC |
+| P8_27 | n/a | NC |
+| P8_28 | n/a | NC |
+| P8_29 | n/a | NC |
+| P8_30 | n/a | NC |
+| P8_31 | n/a | NC |
+| P8_32 | n/a | NC |
+| P8_33 | n/a | NC |
+| P8_34 | n/a | NC |
+| P8_35 | n/a | NC |
+| P8_36 | n/a | NC |
+| P8_37 | n/a | NC |
+| P8_38 | n/a | NC |
+| P8_39 | n/a | NC |
+| P8_40 | n/a | NC |
+| P8_41 | n/a | NC |
+| P8_42 | n/a | NC |
+| P8_43 | n/a | NC |
+| P8_44 | n/a | NC |
+| P8_45 | n/a | NC |
+| P8_46 | n/a | NC |
+
+## P9 Header
+
+| Signal | Control | Description |
+|--------|----------------------------|-------------|
+| P9_1 | n/a | GND |
+| P9_2 | n/a | GND |
+| P9_3 | n/a | VCC 3.3V |
+| P9_4 | n/a | VCC 3.3V |
+| P9_5 | n/a | VDD 5V |
+| P9_6 | n/a | VDD 5V |
+| P9_7 | n/a | SYS 5V |
+| P9_8 | n/a | SYS 5V |
+| P9_9 | n/a | NC |
+| P9_10 | n/a | SYS_RSTN |
+| P9_11 | n/a | NC |
+| P9_12 | n/a | NC |
+| P9_13 | n/a | NC |
+| P9_14 | n/a | NC |
+| P9_15 | n/a | NC |
+| P9_16 | n/a | NC |
+| P9_17 | n/a | NC |
+| P9_18 | n/a | NC |
+| P9_19 | MSS I2C0 | I2C0 SCL |
+| P9_20 | MSS I2C0 | I2C0 SDA |
+| P9_21 | n/a | NC |
+| P9_22 | n/a | NC |
+| P9_23 | n/a | NC |
+| P9_24 | n/a | NC |
+| P9_25 | n/a | NC |
+| P9_26 | n/a | NC |
+| P9_27 | n/a | NC |
+| P9_28 | n/a | NC |
+| P9_29 | n/a | NC |
+| P9_30 | n/a | NC |
+| P9_31 | n/a | NC |
+| P9_32 | n/a | VDD ADC |
+| P9_33 | n/a | ADC input 4 |
+| P9_34 | n/a | AGND |
+| P9_35 | n/a | ADC input 6 |
+| P9_36 | n/a | ADC input 5 |
+| P9_37 | n/a | ADC input 2 |
+| P9_38 | n/a | ADC input 3 |
+| P9_39 | n/a | ADC input 0 |
+| P9_40 | n/a | ADC input 1 |
+| P9_41 | n/a | NC |
+| P9_42 | n/a | NC |
+| P9_43 | n/a | GND |
+| P9_44 | n/a | GND |
+| P9_45 | n/a | GND |
+| P9_46 | n/a | GND |
diff --git a/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/constraints/cape.pdc b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/constraints/cape.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..c18d848afd8f4ff03d72ac39975062cc00c322b7
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/constraints/cape.pdc
@@ -0,0 +1,98 @@
+set_io -port_name P9_11 \
+ -pin_name B5 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION INPUT
+
+set_io -port_name P9_13 \
+ -pin_name D19 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+#set_io -port_name P8_3_USER_LED_0 \
+# -pin_name V22 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_4_USER_LED_1 \
+# -pin_name W22 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_5_USER_LED_2 \
+# -pin_name V19 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_6_USER_LED_3 \
+# -pin_name V20 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_7_USER_LED_4 \
+# -pin_name V15 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_8_USER_LED_5 \
+# -pin_name V14 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_9_USER_LED_6 \
+# -pin_name V21 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_10_USER_LED_7 \
+# -pin_name W21 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_11_USER_LED_8 \
+# -pin_name Y21 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_12_USER_LED_9 \
+# -pin_name Y20 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_13_USER_LED_10 \
+# -pin_name B10 \
+# -fixed true \
+# -io_std LVCMOS33 \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+#
+#set_io -port_name P8_14_USER_LED_11 \
+# -pin_name B9 \
+# -io_std LVCMOS33 \
+# -fixed true \
+# -OUT_DRIVE 12 \
+# -RES_PULL None \
+# -DIRECTION OUTPUT
+
diff --git a/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/device-tree-overlay/cape-gpios.dtso b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/device-tree-overlay/cape-gpios.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..fa044b50dc8d08211cf5e069786c2382d11df0d1
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/NONE_NO_USER_LEDS/device-tree-overlay/cape-gpios.dtso
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+ overlays {
+ MINIMAL-NO-LEDS-CAPE-GATEWARE = "GATEWARE_GIT_VERSION";
+ };
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ gpio-line-names = "", "", "",
+ "", "", "",
+ "", "", "",
+ "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "",
+ "M2_W_DISABLE1", "M2_W_DISABLE2",
+ "VIO_ENABLE", "SD_DET";
+ status = "okay";
+
+ vio_enable {
+ gpio-hog;
+ gpios = <30 30>;
+ output_high;
+ line-name = "VIO_ENABLE";
+ };
+
+ sd_det {
+ gpio-hog;
+ gpios = <31 31>;
+ input;
+ line-name = "SD_DET";
+ };
+};
+
+&mmuart4 {
+ status = "okay";
+ symlink = "bone/uart/4";
+};
diff --git a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/ADD_CAPE.tcl
index 26349e7b52eccc52b79b66d3280a4429b388f952..3b79b78a958bf8c4ffb088346f733330fce43acc 100644
--- a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/ADD_CAPE.tcl
@@ -89,9 +89,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBS
sd_delete_ports -sd_name ${sd_name} -port_names {P9_13}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
-sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[26:3]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[26:3]" "CAPE:INT"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[58:27]"}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[58:27]} -value {GND}
-
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
diff --git a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/CAPE.tcl
index 003f7f36b5a97b0f555ec348b375634e5b27a6d0..4fca43420e2f097a841d54237ce61c2c835d15eb 100644
--- a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/CAPE.tcl
@@ -1,4 +1,4 @@
-# Creating SmartDesign CAPE
+# Creating SmartDesign "CAPE"
set sd_name {CAPE}
create_smartdesign -sd_name ${sd_name}
@@ -79,7 +79,9 @@ sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[23:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_A} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_B} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_C} -port_direction {OUT} -port_range {[7:0]}
# Create top level Bus interface Ports
@@ -93,8 +95,6 @@ sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AM
"PREADY:APB_SLAVE_SLAVE_PREADY" \
"PSLVERR:APB_SLAVE_SLAVE_PSLVERR" }
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT} -pin_slices {[23:8]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT} -pin_slices {[7:0]}
# Add APB_BUS_CONVERTER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
@@ -117,6 +117,8 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -in
# Add P8_GPIO_UPPER_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[7:0]}
@@ -201,8 +203,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "apb_rotary_enc_0:enc
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"INT[23:8]" "P8_GPIO_UPPER_0:INT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"INT[7:0]" "P9_GPIO_0:INT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_A" "P8_GPIO_UPPER_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_B" "P8_GPIO_UPPER_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_C" "P9_GPIO_0:INT" }
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
@@ -215,7 +218,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave5" "PW
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
+# Save the SmartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign CAPE
+# Generate SmartDesign "CAPE"
generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/Readme.md b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/Readme.md
index bb65558986774ade2099b9c1e4fd1278ab4a7f1a..fcd3c1d84936cc05448871d296d21e51f47f5ce6 100644
--- a/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/Readme.md
+++ b/sources/FPGA-design/script_support/components/CAPE/ROBOTICS/Readme.md
@@ -2,102 +2,102 @@
## P8 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P8_1 | n/a | GND |
-| P8_2 | n/a | GND |
-| P8_3 | MSS GPIO_2[0] | User LED 0 |
-| P8_4 | MSS GPIO_2[1] | User LED 1 |
-| P8_5 | MSS GPIO_2[2] | User LED 2 |
-| P8_6 | MSS GPIO_2[3] | User LED 3 |
-| P8_7 | MSS GPIO_2[4] | User LED 4 |
-| P8_8 | MSS GPIO_2[5] | User LED 5 |
-| P8_9 | MSS GPIO_2[6] | User LED 6 |
-| P8_10 | MSS GPIO_2[7] | User LED 7 |
-| P8_11 | MSS GPIO_2[8] | User LED 8 |
-| P8_12 | MSS GPIO_2[9] | User LED 9 |
-| P8_13 | core_pwm[1] @ 0x41500000 | PWM_2:1 |
-| P8_14 | MSS GPIO_2[11] | User LED 11 |
-| P8_15 | MSS GPIO_2[12] | GPIO |
-| P8_16 | MSS GPIO_2[13] | GPIO |
-| P8_17 | MSS GPIO_2[14] | GPIO |
-| P8_18 | MSS GPIO_2[15] | GPIO |
-| P8_19 | core_pwm[0] @ 0x41500000 | PWM_2:0 |
-| P8_20 | MSS GPIO_2[17] | GPIO |
-| P8_21 | MSS GPIO_2[18] | GPIO |
-| P8_22 | MSS GPIO_2[19] | GPIO |
-| P8_23 | MSS GPIO_2[20] | GPIO |
-| P8_24 | MSS GPIO_2[21] | GPIO |
-| P8_25 | MSS GPIO_2[22] | GPIO |
-| P8_26 | MSS GPIO_2[23] | GPIO |
-| P8_27 | MSS GPIO_2[24] | GPIO |
-| P8_28 | MSS GPIO_2[25] | GPIO |
-| P8_29 | MSS GPIO_2[26] | GPIO |
-| P8_30 | MSS GPIO_2[27] | GPIO |
-| P8_31 | core_gpio[0] @ 0x41100000 | GPIO |
-| P8_32 | core_gpio[1] @ 0x41100000 | GPIO |
-| P8_33 | core_gpio[2] @ 0x41100000 | GPIO |
-| P8_34 | core_gpio[3] @ 0x41100000 | GPIO |
-| P8_35 | core_gpio[4] @ 0x41100000 | GPIO |
-| P8_36 | core_gpio[5] @ 0x41100000 | GPIO |
-| P8_37 | core_gpio[6] @ 0x41100000 | GPIO |
-| P8_38 | core_gpio[7] @ 0x41100000 | GPIO |
-| P8_39 | core_gpio[8] @ 0x41100000 | GPIO |
-| P8_40 | core_gpio[9] @ 0x41100000 | GPIO |
-| P8_41 | core_gpio[10] @ 0x41100000 | GPIO |
-| P8_42 | core_gpio[11] @ 0x41100000 | GPIO |
-| P8_43 | core_gpio[12] @ 0x41100000 | GPIO |
-| P8_44 | core_gpio[13] @ 0x41100000 | GPIO |
-| P8_45 | core_gpio[14] @ 0x41100000 | GPIO |
-| P8_46 | core_gpio[15] @ 0x41100000 | GPIO |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1 | n/a | n/a | GND |
+| P8_2 | n/a | n/a | GND |
+| P8_3 | MSS GPIO_2[0] | 53 | User LED 0 |
+| P8_4 | MSS GPIO_2[1] | 53 | User LED 1 |
+| P8_5 | MSS GPIO_2[2] | 53 | User LED 2 |
+| P8_6 | MSS GPIO_2[3] | 53 | User LED 3 |
+| P8_7 | MSS GPIO_2[4] | 53 | User LED 4 |
+| P8_8 | MSS GPIO_2[5] | 53 | User LED 5 |
+| P8_9 | MSS GPIO_2[6] | 53 | User LED 6 |
+| P8_10 | MSS GPIO_2[7] | 53 | User LED 7 |
+| P8_11 | MSS GPIO_2[8] | 53 | User LED 8 |
+| P8_12 | MSS GPIO_2[9] | 53 | User LED 9 |
+| P8_13 | core_pwm[1] @ 0x41500000 | n/a | PWM_2:1 |
+| P8_14 | MSS GPIO_2[11] | 53 | User LED 11 |
+| P8_15 | MSS GPIO_2[12] | 53 | GPIO |
+| P8_16 | MSS GPIO_2[13] | 53 | GPIO |
+| P8_17 | MSS GPIO_2[14] | 53 | GPIO |
+| P8_18 | MSS GPIO_2[15] | 53 | GPIO |
+| P8_19 | core_pwm[0] @ 0x41500000 | n/a | PWM_2:0 |
+| P8_20 | MSS GPIO_2[17] | 53 | GPIO |
+| P8_21 | MSS GPIO_2[18] | 53 | GPIO |
+| P8_22 | MSS GPIO_2[19] | 53 | GPIO |
+| P8_23 | MSS GPIO_2[20] | 53 | GPIO |
+| P8_24 | MSS GPIO_2[21] | 53 | GPIO |
+| P8_25 | MSS GPIO_2[22] | 53 | GPIO |
+| P8_26 | MSS GPIO_2[23] | 53 | GPIO |
+| P8_27 | MSS GPIO_2[24] | 53 | GPIO |
+| P8_28 | MSS GPIO_2[25] | 53 | GPIO |
+| P8_29 | MSS GPIO_2[26] | 53 | GPIO |
+| P8_30 | MSS GPIO_2[27] | 53 | GPIO |
+| P8_31 | core_gpio[0] @ 0x41100000 | 126 | GPIO |
+| P8_32 | core_gpio[1] @ 0x41100000 | 127 | GPIO |
+| P8_33 | core_gpio[2] @ 0x41100000 | 128 | GPIO |
+| P8_34 | core_gpio[3] @ 0x41100000 | 129 | GPIO |
+| P8_35 | core_gpio[4] @ 0x41100000 | 130 | GPIO |
+| P8_36 | core_gpio[5] @ 0x41100000 | 131 | GPIO |
+| P8_37 | core_gpio[6] @ 0x41100000 | 132 | GPIO |
+| P8_38 | core_gpio[7] @ 0x41100000 | 133 | GPIO |
+| P8_39 | core_gpio[8] @ 0x41100000 | 134 | GPIO |
+| P8_40 | core_gpio[9] @ 0x41100000 | 135 | GPIO |
+| P8_41 | core_gpio[10] @ 0x41100000 | 136 | GPIO |
+| P8_42 | core_gpio[11] @ 0x41100000 | 137 | GPIO |
+| P8_43 | core_gpio[12] @ 0x41100000 | 138 | GPIO |
+| P8_44 | core_gpio[13] @ 0x41100000 | 139 | GPIO |
+| P8_45 | core_gpio[14] @ 0x41100000 | 140 | GPIO |
+| P8_46 | core_gpio[15] @ 0x41100000 | 141 | GPIO |
## P9 Header
-| Signal | Control | Description |
-|--------|----------------------------|-------------|
-| P9_1 | n/a | GND |
-| P9_2 | n/a | GND |
-| P9_3 | n/a | VCC 3.3V |
-| P9_4 | n/a | VCC 3.3V |
-| P9_5 | n/a | VDD 5V |
-| P9_6 | n/a | VDD 5V |
-| P9_7 | n/a | SYS 5V |
-| P9_8 | n/a | SYS 5V |
-| P9_9 | n/a | NC |
-| P9_10 | n/a | SYS_RSTN |
-| P9_11 | | |
-| P9_12 | core_gpio[0] @ 0x41200000 | GPIO |
-| P9_13 | core_gpio[7] @ 0x41200000 | GPIO |
-| P9_14 | core_pwm[0] @ 0x41400000 | PWM_1:0 |
-| P9_15 | core_gpio[1] @ 0x41200000 | GPIO |
-| P9_16 | core_pwm[1] @ 0x41400000 | PWM_1:1 |
-| P9_17 | | |
-| P9_18 | | |
-| P9_19 | MSS I2C0 | I2C0 SCL |
-| P9_20 | MSS I2C0 | I2C0 SDA |
-| P9_21 | | |
-| P9_22 | | |
-| P9_23 | core_gpio[2] @ 0x41200000 | GPIO |
-| P9_24 | | |
-| P9_25 | core_gpio[3] @ 0x41200000 | GPIO |
-| P9_26 | | |
-| P9_27 | | |
-| P9_28 | | |
-| P9_29 | | |
-| P9_30 | core_gpio[5] @ 0x41200000 | GPIO |
-| P9_31 | | |
-| P9_32 | n/a | VDD ADC |
-| P9_33 | n/a | ADC input 4 |
-| P9_34 | n/a | AGND |
-| P9_35 | n/a | ADC input 6 |
-| P9_36 | n/a | ADC input 5 |
-| P9_37 | n/a | ADC input 2 |
-| P9_38 | n/a | ADC input 3 |
-| P9_39 | n/a | ADC input 0 |
-| P9_40 | n/a | ADC input 1 |
-| P9_41 | core_gpio[19] @ 0x41200000 | GPIO |
-| P9_42 | | |
-| P9_43 | n/a | GND |
-| P9_44 | n/a | GND |
-| P9_45 | n/a | GND |
-| P9_46 | n/a | GND |
+| Signal | Control | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1 | n/a | n/a | GND |
+| P9_2 | n/a | n/a | GND |
+| P9_3 | n/a | n/a | VCC 3.3V |
+| P9_4 | n/a | n/a | VCC 3.3V |
+| P9_5 | n/a | n/a | VDD 5V |
+| P9_6 | n/a | n/a | VDD 5V |
+| P9_7 | n/a | n/a | SYS 5V |
+| P9_8 | n/a | n/a | SYS 5V |
+| P9_9 | n/a | n/a | NC |
+| P9_10 | n/a | n/a | SYS_RSTN |
+| P9_11 | | | |
+| P9_12 | core_gpio[0] @ 0x41200000 | 142 | GPIO |
+| P9_13 | core_gpio[7] @ 0x41200000 | 149 | GPIO |
+| P9_14 | core_pwm[0] @ 0x41400000 | n/a | PWM_1:0 |
+| P9_15 | core_gpio[1] @ 0x41200000 | 143 | GPIO |
+| P9_16 | core_pwm[1] @ 0x41400000 | n/a | PWM_1:1 |
+| P9_17 | | | |
+| P9_18 | | | |
+| P9_19 | MSS I2C0 | 58 | I2C0 SCL |
+| P9_20 | MSS I2C0 | 58 | I2C0 SDA |
+| P9_21 | | | |
+| P9_22 | | | |
+| P9_23 | core_gpio[2] @ 0x41200000 | 144 | GPIO |
+| P9_24 | | | |
+| P9_25 | core_gpio[3] @ 0x41200000 | 145 | GPIO |
+| P9_26 | | | |
+| P9_27 | | | |
+| P9_28 | | | |
+| P9_29 | | | |
+| P9_30 | core_gpio[5] @ 0x41200000 | 147 | GPIO |
+| P9_31 | | | |
+| P9_32 | n/a | n/a | VDD ADC |
+| P9_33 | n/a | n/a | ADC input 4 |
+| P9_34 | n/a | n/a | AGND |
+| P9_35 | n/a | n/a | ADC input 6 |
+| P9_36 | n/a | n/a | ADC input 5 |
+| P9_37 | n/a | n/a | ADC input 2 |
+| P9_38 | n/a | n/a | ADC input 3 |
+| P9_39 | n/a | n/a | ADC input 0 |
+| P9_40 | n/a | n/a | ADC input 1 |
+| P9_41 | core_gpio[6] @ 0x41200000 | 148 | GPIO |
+| P9_42 | | | |
+| P9_43 | n/a | n/a | GND |
+| P9_44 | n/a | n/a | GND |
+| P9_45 | n/a | n/a | GND |
+| P9_46 | n/a | n/a | GND |
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
index c47747dda858bc2bb01d14a9d972e769f65ec660..d6ca7b5ac44794ec25f464c99125ba335e9d83fe 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/ADD_CAPE.tcl
@@ -122,8 +122,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_TARGET" "BVF_RISCV_SUB
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
-sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[26:3]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[26:3]" "CAPE:INT"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[58:27]"}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[58:27]} -value {GND}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
index ebf07ca15103e72e12e9e50035f0ae49cf52b1ca..eeffe7560a8db259abf365ce418fe80afe81b637 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TEMPLATE/HDL/CAPE.v
@@ -20,7 +20,9 @@ module CAPE(
// Outputs
APB_SLAVE_SLAVE_PRDATA,
GPIO_IN,
- INT,
+ INT_A,
+ INT_B,
+ INT_C,
// Inouts
P8_3,
P8_4,
@@ -106,7 +108,9 @@ input PRESETN;
//--------------------------------------------------------------------
output [31:0] APB_SLAVE_SLAVE_PRDATA;
output [27:0] GPIO_IN;
-output [23:0] INT;
+output [7:0] INT_A;
+output [7:0] INT_B;
+output [7:0] INT_C;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
@@ -263,7 +267,6 @@ wire [46:3] GPIO_IN_net_2;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
-wire [23:0] INT_const_net_0;
wire [46:31] GPIO_OE_const_net_0;
wire [46:31] GPIO_OUT_const_net_0;
wire [18:11] GPIO_OE_const_net_1;
@@ -281,7 +284,6 @@ wire [7:0] APB_SLAVE_SLAVE_PADDR_0_7to0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
-assign INT_const_net_0 = 24'h000000;
assign GPIO_OE_const_net_0 = 16'h0000;
assign GPIO_OUT_const_net_0 = 16'h0000;
assign GPIO_OE_const_net_1 = 8'h00;
@@ -293,7 +295,9 @@ assign GPIO_OUT_const_net_3 = 2'h0;
//--------------------------------------------------------------------
// TieOff assignments
//--------------------------------------------------------------------
-assign INT[23:0] = 24'h000000;
+assign INT_A[7:0] = 8'h00;
+assign INT_B[7:0] = 8'h00;
+assign INT_C[7:0] = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/ADD_CAPE.tcl
index 4a3fdecae12c14f29c6a34517383ffce9eb69d95..dcafa338953ca18d8b2a1e0ff1dd23c754efe940 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/ADD_CAPE.tcl
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/ADD_CAPE.tcl
@@ -123,8 +123,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_TARGET" "BVF_RISCV_SUB
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
-sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[26:3]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[26:3]" "CAPE:INT"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M} -pin_slices {"[58:27]"}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M[58:27]} -value {GND}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"}
diff --git a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/HDL/CAPE.v b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/HDL/CAPE.v
index 33ffb165063c55e960aa1c6c43cb9fe47b53a319..3e0f99205c2b45a0b28c09b64275898f23b9b6a6 100644
--- a/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/HDL/CAPE.v
+++ b/sources/FPGA-design/script_support/components/CAPE/VERILOG_TUTORIAL/HDL/CAPE.v
@@ -20,7 +20,9 @@ module CAPE(
// Outputs
APB_SLAVE_SLAVE_PRDATA,
GPIO_IN,
- INT,
+ INT_A,
+ INT_B,
+ INT_C,
// Inouts
P8_3,
P8_4,
@@ -106,7 +108,9 @@ input PRESETN;
//--------------------------------------------------------------------
output [31:0] APB_SLAVE_SLAVE_PRDATA;
output [27:0] GPIO_IN;
-output [23:0] INT;
+output [7:0] INT_A;
+output [7:0] INT_B;
+output [7:0] INT_C;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
@@ -264,7 +268,6 @@ wire [46:3] GPIO_IN_net_2;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
-wire [23:0] INT_const_net_0;
wire [46:31] GPIO_OE_const_net_0;
wire [46:31] GPIO_OUT_const_net_0;
wire [18:11] GPIO_OE_const_net_1;
@@ -282,7 +285,6 @@ wire [7:0] APB_SLAVE_SLAVE_PADDR_0_7to0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
-assign INT_const_net_0 = 24'h000000;
assign GPIO_OE_const_net_0 = 16'h0000;
assign GPIO_OUT_const_net_0 = 16'h0000;
assign GPIO_OE_const_net_1 = 8'h00;
@@ -294,7 +296,9 @@ assign GPIO_OUT_const_net_3 = 2'h0;
//--------------------------------------------------------------------
// TieOff assignments
//--------------------------------------------------------------------
-assign INT[23:0] = 24'h000000;
+assign INT_A[7:0] = 8'h00;
+assign INT_B[7:0] = 8'h00;
+assign INT_C[7:0] = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/ADD_HIGH_SPEED_CONNECTOR.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/ADD_HIGH_SPEED_CONNECTOR.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8aaede0d795e00bd0c9404900d9a153d2af204eb
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/ADD_HIGH_SPEED_CONNECTOR.tcl
@@ -0,0 +1,119 @@
+
+puts "======== Add High Speed Connector option: LOOPBACK_3_LANES_OPAL_KELLY ========"
+
+#BOARD_VALIDATION_OPAL_KELLY_3_LANES
+
+# Import source files
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_chk.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_gen.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/startup.v}
+
+build_design_hierarchy
+create_hdl_core -file $project_dir/hdl/startup.v -module {STARTUP} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_chk.v -module {PATTERN_CHK} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_gen.v -module {PATTERN_GEN} -library {work} -package {}
+
+
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_C0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_rx.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_tx.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_Block.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
+
+
+
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_CCC_C1.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_TX_PLL_XCVR1.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HSIO_CoreGPIO_C0.tcl
+source script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HIGH_SPEED_INTERFACE.tcl
+
+
+
+
+set sd_name ${top_level_name}
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {HIGH_SPEED_INTERFACE} -instance_name {HIGH_SPEED_INTERFACE_0}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_RESET_N_M2F" "HIGH_SPEED_INTERFACE_0:EXT_RST_N"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "HIGH_SPEED_INTERFACE_0:DEVICE_INIT_DONE"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:XCVR_INIT_DONE" "HIGH_SPEED_INTERFACE_0:XCVR_INIT_DONE"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RCOSC_160MHZ_GL" "HIGH_SPEED_INTERFACE_0:RCOSC_160MHZ_GL"}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_3_USER_LED_0} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_4_USER_LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_5_USER_LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_6_USER_LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_7_USER_LED_4} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_8_USER_LED_5} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_9_USER_LED_6} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_10_USER_LED_7} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_11_USER_LED_8} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_12_USER_LED_9} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_14_USER_LED_11} -port_direction {OUT}
+
+
+
+
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_RX_VALID" "P8_3_USER_LED_0"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_LOCK" "P8_4_USER_LED_1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_ERROR" "P8_5_USER_LED_2"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID" "P8_6_USER_LED_3"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_LOCK" "P8_7_USER_LED_4"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_ERROR" "P8_8_USER_LED_5"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID" "P8_9_USER_LED_6"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "P8_10_USER_LED_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "P8_11_USER_LED_8"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0B_REF_CLK_PLL_LOCK" "P8_12_USER_LED_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REF_CLK_PLL_LOCK" "P8_13_USER_LED_10"}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_14_USER_LED_11} -value {GND}
+
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_3_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_1_LED}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO82P} -port_name {}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M" "HIGH_SPEED_INTERFACE_0:MAC_1_MDI_F2M"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDC_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_OE_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_M2F"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "HIGH_SPEED_INTERFACE_0:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:PRESETN"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET" "HIGH_SPEED_INTERFACE_0:APB_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:SYS_RESET_N"}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73P_C2P_CLKP} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73N_C2P_CLKN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81P} -port_name {}
+
+# Override software control of VIO.
+sd_delete_nets -sd_name ${sd_name} -net_names {VIO_ENABLE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:VIO_ENABLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VIO_ENABLE} -value {GND}
+
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HIGH_SPEED_INTERFACE.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HIGH_SPEED_INTERFACE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1e4c53ea9ef180c2695bed7e44d7313c1a1a4835
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HIGH_SPEED_INTERFACE.tcl
@@ -0,0 +1,292 @@
+# Creating SmartDesign HIGH_SPEED_INTERFACE
+set sd_name {HIGH_SPEED_INTERFACE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73P_C2P_CLKP} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDC_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_OE_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_RESET_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX1_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX1_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_P} -port_direction {IN} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73N_C2P_CLKN} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDI_F2M} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REF_CLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REF_CLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_P} -port_direction {OUT} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82N} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_TARGET_PADDR" \
+"PSELx:APB_TARGET_PSEL" \
+"PENABLE:APB_TARGET_PENABLE" \
+"PWRITE:APB_TARGET_PWRITE" \
+"PRDATA:APB_TARGET_PRDATA" \
+"PWDATA:APB_TARGET_PWDATA" \
+"PREADY:APB_TARGET_PREADY" \
+"PSLVERR:APB_TARGET_PSLVERR" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add BIBUF_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
+
+
+
+# Add HSIO_CoreGPIO_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {HSIO_CoreGPIO_C0} -instance_name {HSIO_CoreGPIO_C0_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[0:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[1:1]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[1:1]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[2:2]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[3:3]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:INT}
+
+
+
+# Add PF_CCC_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0}
+
+
+
+# Add PF_CCC_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_CCC_C1_0:PLL_POWERDOWN_N_0} -value {VCC}
+
+
+
+# Add PF_CLK_DIV_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}
+
+
+
+# Add PF_TX_PLL_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_0} -instance_name {PF_TX_PLL_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:CLK_125}
+
+
+
+# Add PF_XCVR_REF_CLK_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}
+
+
+
+# Add PF_XCVR_REF_CLK_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_C0_0:REF_CLK}
+
+
+
+# Add XCVR_LOOPBACK_3 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_3}
+
+
+
+# Add XCVR_LOOPBACK_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_1}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_0_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_1_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_3_LED}
+
+
+
+# Add XCVR_LOOPBACK_2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_0_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_1_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_3_LED}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "HSIO_CoreGPIO_C0_0:GPIO_IN[17:17]" "PF_CCC_C0_0:PLL_LOCK_0" "XCVR_0B_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_TX_PLL_0_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_3:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_1:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[18:18]" "PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[4:4]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71P" "HSIO_CoreGPIO_C0_0:GPIO_IN[5:5]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73N_C2P_CLKN" "HSIO_CoreGPIO_C0_0:GPIO_OUT[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73P_C2P_CLKP" "HSIO_CoreGPIO_C0_0:GPIO_IN[7:7]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81N" "HSIO_CoreGPIO_C0_0:GPIO_IN[19:19]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81P" "SYS_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82N" "BIBUF_0:PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82P" "MAC_1_MDC_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83P" "HSIO_CoreGPIO_C0_0:GPIO_IN[6:6]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "MAC_1_MDO_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "MAC_1_MDO_OE_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "MAC_1_MDI_F2M" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "XCVR_LOOPBACK_3:DEVICE_INIT_DONE" "XCVR_LOOPBACK_1:DEVICE_INIT_DONE" "XCVR_LOOPBACK_2:DEVICE_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "XCVR_LOOPBACK_3:EXT_RST_N" "XCVR_LOOPBACK_1:EXT_RST_N" "XCVR_LOOPBACK_2:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[10:10]" "XCVR1_ERROR" "XCVR_LOOPBACK_1:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[11:11]" "XCVR2_RX_VALID" "XCVR_LOOPBACK_2:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[12:12]" "XCVR2_LOCK" "XCVR_LOOPBACK_2:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[13:13]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[14:14]" "XCVR3_RX_VALID" "XCVR_LOOPBACK_3:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[15:15]" "XCVR3_LOCK" "XCVR_LOOPBACK_3:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[16:16]" "XCVR3_ERROR" "XCVR_LOOPBACK_3:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]" "XCVR1_RX_VALID" "XCVR_LOOPBACK_1:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR1_LOCK" "XCVR_LOOPBACK_1:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_3:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" "XCVR_LOOPBACK_1:XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "XCVR_LOOPBACK_3:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_1:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_2:RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_N" "XCVR_0B_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_P" "XCVR_0B_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "XCVR_0C_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "XCVR_0C_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "XCVR_LOOPBACK_3:TEST_MODE_0_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "XCVR_LOOPBACK_3:TEST_MODE_1_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "XCVR_LOOPBACK_3:TEST_MODE_2_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_3_LED" "XCVR_LOOPBACK_3:TEST_MODE_3_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_INIT_DONE" "XCVR_LOOPBACK_3:XCVR_INIT_DONE" "XCVR_LOOPBACK_1:XCVR_INIT_DONE" "XCVR_LOOPBACK_2:XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_3:LANE0_RXD_N" "XCVR_RX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_3:LANE0_RXD_P" "XCVR_RX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_3:LANE0_TXD_N" "XCVR_TX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_3:LANE0_TXD_P" "XCVR_TX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_RXD_N" "XCVR_RX1_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_RXD_P" "XCVR_RX1_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_TXD_N" "XCVR_TX1_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_TXD_P" "XCVR_TX1_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_N" "XCVR_RX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_P" "XCVR_RX2_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_N" "XCVR_TX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_P" "XCVR_TX2_P" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "HSIO_CoreGPIO_C0_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_3:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_2:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_1:CLKS_FROM_TXPLL_0"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_XCVR1_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_1:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign HIGH_SPEED_INTERFACE
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HSIO_CoreGPIO_C0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HSIO_CoreGPIO_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8b5fec733627d0faec5d0d43cde1e421c570d031
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/HSIO_CoreGPIO_C0.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component HSIO_CoreGPIO_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {HSIO_CoreGPIO_C0} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:true" \
+"FIXED_CONFIG_17:true" \
+"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_20:false" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:20" \
+"IO_TYPE_0:1" \
+"IO_TYPE_1:1" \
+"IO_TYPE_2:1" \
+"IO_TYPE_3:1" \
+"IO_TYPE_4:0" \
+"IO_TYPE_5:0" \
+"IO_TYPE_6:0" \
+"IO_TYPE_7:0" \
+"IO_TYPE_8:0" \
+"IO_TYPE_9:0" \
+"IO_TYPE_10:0" \
+"IO_TYPE_11:0" \
+"IO_TYPE_12:0" \
+"IO_TYPE_13:0" \
+"IO_TYPE_14:0" \
+"IO_TYPE_15:0" \
+"IO_TYPE_16:0" \
+"IO_TYPE_17:0" \
+"IO_TYPE_18:0" \
+"IO_TYPE_19:0" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_CCC_C1.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_CCC_C1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2e1d947307a619e6cbecb43b2afbc50f7aaa2abb
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_CCC_C1.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_CCC_C1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:*} -component_name {PF_CCC_C1} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:12" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:true" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:125" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C1 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_TX_PLL_XCVR1.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_TX_PLL_XCVR1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d8d115d770ff5dce3b9ccf55751b06c2614cee87
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_TX_PLL_XCVR1.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_TX_PLL_XCVR1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_XCVR1} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..55f816c6b1239c3e90a999a4c2dd90033ae9c06e
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/PF_XCVR_REF_CLK_C0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_XCVR_REF_CLK_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+"ENABLE_FAB_CLK_0:true" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/Readme.md b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/Readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..668bb41938e6ecb046949c8b1f61a8dc920d3148
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/Readme.md
@@ -0,0 +1,9 @@
+# SYZYGY Loopback - 3 Lanes
+
+Loopback the 3 SYZYGY tranceivers lanes at 5Gbps
+
+This is intended to be used with the Opal Kelly SZG-TST-TXR4 loopback board to sanity check the connections between the SYZYGY connector and PolarFire SoC.
+
+This can only be built using the following gateware build options combination:
+
+"M2_OPTION:NONE CAPE_OPTION:NONE_NO_USER_LEDS SYZYGY_OPTION:LOOPBACK_3_LANES_OPAL_KELLY"
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_01.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_01.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c6ba95cb116fd7a439d5b988c52a6916bb459928
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_01.tcl
@@ -0,0 +1,248 @@
+# Exporting Component Description of PF_CCC_01 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CCC_01
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CCC:* -component_name {PF_CCC_01} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:1" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:10" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:125" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:0" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:160" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:0" \
+"PLL_LOCK_COUNT_1:0" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:4" \
+"PLL_REFDIV_1:1" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_01 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_C0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3abd00e9794cfde9097737931e4296ace3c0242e
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CCC_C0.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_CCC_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:*} -component_name {PF_CCC_C0} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:8" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:156.25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:100" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c6a23b9f703efb211edfa25d6940f2b99ac7e395
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -0,0 +1,9 @@
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CLK_DIV_C0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
+"DIVIDER:4" \
+"ENABLE_BIT_SLIP:false" \
+"ENABLE_SRESET:false" }
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_OSC_0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_OSC_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..88eb2d4072a45ccdda19a665e4fcebd20be9ef48
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_OSC_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_OSC_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_OSC_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_OSC:1.0.102 -component_name {PF_OSC_0} -params {\
+"RCOSC_2MHZ_CLK_DIV_EN:false" \
+"RCOSC_2MHZ_GL_EN:false" \
+"RCOSC_2MHZ_NGMUX_EN:false" \
+"RCOSC_160MHZ_CLK_DIV_EN:false" \
+"RCOSC_160MHZ_GL_EN:true" \
+"RCOSC_160MHZ_NGMUX_EN:false" }
+# Exporting Component Description of PF_OSC_0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..71025d8d90ecd943216aafe39490b91ce194c088
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_TX_PLL_0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1d1081ec160cd8363161ebfe5f701fbe0100bdb1
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -0,0 +1,55 @@
+# Exporting Component Description of PF_XCVR_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_XCVR_0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
+"EXPOSE_ALL_DEBUG_PORTS:false" \
+"EXPOSE_FWF_EN_PORTS:false" \
+"SHOW_UNIVERSAL_SOLN_PORTS:true" \
+"UI_CDR_LOCK_MODE:Lock to data" \
+"UI_CDR_REFERENCE_CLK_FREQ:156.25" \
+"UI_CDR_REFERENCE_CLK_SOURCE:Fabric" \
+"UI_CDR_REFERENCE_CLK_TOLERANCE:1" \
+"UI_ENABLE_32BIT_DATA_WIDTH:false" \
+"UI_ENABLE_64B66B:true" \
+"UI_ENABLE_64B67B:false" \
+"UI_ENABLE_64B6XB_MODE:false" \
+"UI_ENABLE_8B10B_MODE:true" \
+"UI_ENABLE_BER:false" \
+"UI_ENABLE_DISPARITY:false" \
+"UI_ENABLE_FIBRE_CHANNEL_DISPARITY:false" \
+"UI_ENABLE_PHASE_COMP_MODE:false" \
+"UI_ENABLE_PIPE_MODE:false" \
+"UI_ENABLE_PMA_MODE:false" \
+"UI_ENABLE_SCRAMBLING:false" \
+"UI_ENABLE_SWITCH_BETWEEN_CDR_REFCLKS:false" \
+"UI_ENABLE_SWITCH_BETWEEN_TXPLLS:false" \
+"UI_EXPOSE_APBLINK_PORTS:false" \
+"UI_EXPOSE_CDR_BITSLIP_PORT:false" \
+"UI_EXPOSE_DYNAMIC_RECONFIGURATION_PORTS:false" \
+"UI_EXPOSE_JA_CLOCK_PORT:false" \
+"UI_EXPOSE_RX_READY_VAL_CDR_PORT:false" \
+"UI_EXPOSE_TX_BYPASS_DATA:false" \
+"UI_EXPOSE_TX_ELEC_IDLE:false" \
+"UI_INTERFACE_RXCLOCK:Regional" \
+"UI_INTERFACE_TXCLOCK:Regional" \
+"UI_IS_CONFIGURED:true" \
+"UI_NUMBER_OF_LANES:1" \
+"UI_PCS_ARST_N:RX Only" \
+"UI_PIPE_PROTOCOL_USED:PCIe" \
+"UI_PMA_ARST_N:TX and RX PMA" \
+"UI_PROTOCOL_PRESET_USED:None" \
+"UI_RX_DATA_RATE:5000" \
+"UI_RX_PCS_FAB_IF_WIDTH:32" \
+"UI_SATA_IDLE_BURST_TIMING:MAC" \
+"UI_TX_CLK_DIV_FACTOR:1" \
+"UI_TX_DATA_RATE:5000" \
+"UI_TX_PCS_FAB_IF_WIDTH:32" \
+"UI_TX_RX_MODE:Duplex" \
+"UI_USE_INTERFACE_CLK_AS_PLL_REFCLK:false" \
+"UI_XCVR_RX_CALIBRATION:None (CDR)" \
+"UI_XCVR_RX_DATA_EYE_CALIBRATION:false" \
+"UI_XCVR_RX_DFE_COEFF_CALIBRATION:false" \
+"UI_XCVR_RX_ENHANCED_MANAGEMENT:true" \
+"XT_ES_DEVICE:false" }
+# Exporting Component Description of PF_XCVR_0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..94d64dcd93d485c9bbf6390c658c51370dde6bad
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_XCVR_REF_CLK_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
+"ENABLE_FAB_CLK_0:false" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_Block.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_Block.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..56de848720c5d43c065759644c92e70c6782d462
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_Block.tcl
@@ -0,0 +1,66 @@
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvv Create Transceivers Reset Block vvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+
+# Creating SmartDesign Reset_Block
+set sd_name {Reset_Block}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_x_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_y_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_clk} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_ready} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk_stable} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_chk_rst_n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_gen_rst_n} -port_direction {OUT}
+
+
+
+# Add Reset_sync_rx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_rx} -instance_name {Reset_sync_rx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:PLL_POWERDOWN_B}
+
+
+
+# Add Reset_sync_tx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_tx} -instance_name {Reset_sync_tx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:PLL_POWERDOWN_B}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_x_VDDI_STATUS" "Reset_sync_rx_0:BANK_x_VDDI_STATUS" "Reset_sync_tx_0:BANK_x_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_y_VDDI_STATUS" "Reset_sync_rx_0:BANK_y_VDDI_STATUS" "Reset_sync_tx_0:BANK_y_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_sync_rx_0:EXT_RST_N" "Reset_sync_tx_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "Reset_sync_rx_0:INIT_DONE" "Reset_sync_tx_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_chk_rst_n" "Reset_sync_rx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_gen_rst_n" "Reset_sync_tx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_clk" "Reset_sync_rx_0:CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_ready" "Reset_sync_rx_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:CLK" "TX_clk" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:PLL_LOCK" "TX_clk_stable" }
+
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign Reset_Block
+generate_component -component_name ${sd_name}
+
+puts "^^^^^^^^^^^^^^^^^ Create Transceivers Reset Block Complete ^^^^^^^^^^^^^^^^^^^"
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_rx.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_rx.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b2fad00b4abf0284cf96a6d818a9063461164458
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_rx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_rx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_rx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_rx} -params { }
+# Exporting Component Description of Reset_sync_rx to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_tx.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_tx.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..18005a52b4bca08c839151364cbee8fd0e5992c0
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/Reset_sync_tx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_tx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_tx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_tx} -params { }
+# Exporting Component Description of Reset_sync_tx to TCL done
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..31bb785f784c55164af87ad1e9e07f4bae8a1e01
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
@@ -0,0 +1,151 @@
+# Creating SmartDesign XCVR_LOOPBACK
+set sd_name {XCVR_LOOPBACK}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_BIT_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {error_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {lock_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val_o} -port_direction {OUT}
+
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {slave} -port_bif_mapping {\
+"LOCK:CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0" \
+"BIT_CLK:CLKS_FROM_TXPLL_0_TX_BIT_CLK_0" \
+"REF_CLK_TO_LANE:CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add pattern_chk_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_CHK} -instance_name {pattern_chk_0}
+# Exporting Parameters of instance pattern_chk_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_chk_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:RESET_EN} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:generate_err} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:LANE_ARST_N}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:start_i} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:clear_i} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_count_o}
+
+
+
+# Add pattern_gen_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_GEN} -instance_name {pattern_gen_0}
+# Exporting Parameters of instance pattern_gen_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_gen_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_gen_0:generate_err_i} -value {GND}
+
+
+
+# Add PF_XCVR_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_IDLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_TX_DISPFNC} -value {GND}
+
+
+
+# Add Reset_Block_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_Block} -instance_name {Reset_Block_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_y_VDDI_STATUS} -value {VCC}
+
+
+
+# Add startup_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {STARTUP} -instance_name {startup_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_XCVR_0_0:LANE0_TX_CLK_STABLE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "Reset_Block_0:TX_clk_stable" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "Reset_Block_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_Block_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_0_0:LANE0_RXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_0_0:LANE0_RXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_0_0:LANE0_TXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_0_0:LANE0_TXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_ARST_N" "PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE0_PMA_ARST_N" "XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_CLK" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_CDR_REF_CLK_FAB" "XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CLK_R" "Reset_Block_0:RX_clk" "pattern_chk_0:clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_READY" "Reset_Block_0:RX_ready" "pattern_chk_0:RX_READY" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_VAL" "pattern_chk_0:rx_val_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_R" "Reset_Block_0:TX_clk" "pattern_gen_0:clk_i" "startup_0:tx_clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_chk_rst_n" "TEST_MODE_3_LED" "pattern_chk_0:ARST_N" "pattern_chk_0:reset_n_i" "startup_0:pattern_chk_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_gen_rst_n" "startup_0:pattern_gen_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "pattern_chk_0:s_count[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "pattern_chk_0:s_count[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "pattern_chk_0:s_count[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"error_o" "pattern_chk_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"lock_o" "pattern_chk_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_chk_0:rx_val_o" "rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_0:reset_n_i" "startup_0:start_gen_o" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_RX_K" "pattern_chk_0:Rx_K_Char_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_TX_K" "pattern_gen_0:Tx_K_Char_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CODE_VIOLATION" "pattern_chk_0:LCV_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "pattern_chk_0:data_in_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DISPARITY_ERROR" "pattern_chk_0:DISP_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_DATA" "pattern_gen_0:data_out_o" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_FROM_TXPLL_0" "PF_XCVR_0_0:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign XCVR_LOOPBACK
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/SYZYGY.pdc b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/SYZYGY.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..a7fedb76b3acff473a6b83e689dca098468d5c2d
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/SYZYGY.pdc
@@ -0,0 +1,211 @@
+set_io -port_name P8_3_USER_LED_0 \
+ -pin_name V22 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_4_USER_LED_1 \
+ -pin_name W22 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_5_USER_LED_2 \
+ -pin_name V19 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_6_USER_LED_3 \
+ -pin_name V20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_7_USER_LED_4 \
+ -pin_name V15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_8_USER_LED_5 \
+ -pin_name V14 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_9_USER_LED_6 \
+ -pin_name V21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_10_USER_LED_7 \
+ -pin_name W21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_11_USER_LED_8 \
+ -pin_name Y21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_12_USER_LED_9 \
+ -pin_name Y20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_13_USER_LED_10 \
+ -pin_name B10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_14_USER_LED_11 \
+ -pin_name B9 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name XCVR_TX1_N \
+ -pin_name H21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX1_P \
+ -pin_name H22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX2_N \
+ -pin_name P21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX2_P \
+ -pin_name P22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_N \
+ -pin_name T21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_P \
+ -pin_name T22 \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name XCVR_RX1_N \
+ -pin_name K21 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX1_P \
+ -pin_name K22 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_N \
+ -pin_name M21 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_P \
+ -pin_name M22 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_N \
+ -pin_name R19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_P \
+ -pin_name R20 \
+ -DIRECTION INPUT
+
+
+#set_io -port_name XCVR_0A_REFCLK_P \
+# -pin_name L19 \
+# -DIRECTION INPUT
+#
+#set_io -port_name XCVR_0A_REFCLK_N \
+# -pin_name L20 \
+# -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0B_REFCLK_P \
+ -pin_name N19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0B_REFCLK_N \
+ -pin_name N20 \
+ -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0C_REFCLK_P \
+ -pin_name J19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0C_REFCLK_N \
+ -pin_name J20 \
+ -DIRECTION INPUT
+
+
+
+set_io -port_name B0_HSIO70N \
+ -pin_name AB20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO70P \
+ -pin_name AB19 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO71N \
+ -pin_name AA20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO71P \
+ -pin_name AB21 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO73N_C2P_CLKN \
+ -pin_name U17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO73P_C2P_CLKP \
+ -pin_name T17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO81N \
+ -pin_name AA17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO81P \
+ -pin_name AB17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO82N \
+ -pin_name Y16 \
+ -fixed true \
+ -DIRECTION INOUT
+
+
+set_io -port_name B0_HSIO82P \
+ -pin_name AA16 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO83N \
+ -pin_name W17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO83P \
+ -pin_name W16 \
+ -fixed true \
+ -DIRECTION INPUT
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/fp/SYZYGY.pdc b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/fp/SYZYGY.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..806a692d2117e9595dfbacc7e6d4770a0afd0f76
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/constraints/fp/SYZYGY.pdc
@@ -0,0 +1,7 @@
+
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_0/I_IO -fixed true -x 1014 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_3/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1009 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_TX_PLL_0_0/PF_TX_PLL_0_0/txpll_isnt_0 -fixed true -x 1014 -y 77
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_2/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_0_0/PF_XCVR_REF_CLK_0_0/I_IO -fixed true -x 1015 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_1/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 47
diff --git a/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/device-tree-overlay/syzygy-test-gpios.dtso b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/device-tree-overlay/syzygy-test-gpios.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..1a57dfe71f03f93557880c7ad32b5d5657ec1342
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/SYZYGY/LOOPBACK_3_LANES_OPAL_KELLY/device-tree-overlay/syzygy-test-gpios.dtso
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+ overlays {
+ SYZYGY-3-LANES-LOOPBACK-GATEWARE = "GATEWARE_GIT_VERSION";
+ };
+};
+
+&{/} {
+ fabric-bus@40000000 {
+ hsi_gpios: gpio@44000000 {
+ compatible = "microchip,core-gpio";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios=<20>;
+ status = "okay";
+ gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", "B0_HSIO73N_C2P_CLKN",
+ "B0_HSIO70P", "B0_HSIO71P", "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP",
+ "XCVR1_RX_VALID", "XCVR1_LOCK", "XCVR1_ERROR",
+ "XCVR2_RX_VALID", "XCVR2_LOCK", "XCVR2_ERROR",
+ "XCVR3_RX_VALID", "XCVR3_LOCK", "XCVR3_ERROR",
+ "XCVR_0B_REF_CLK_PLL_LOCK", "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
+ };
+ };
+};
diff --git a/sources/MSS_Configuration/MSS_Configuration.cfg b/sources/MSS_Configuration/MSS_Configuration.cfg
index 5440c34e35a1d005e891923bf25db5185696b5bb..f2d7c78152af09ba20d9733d46b19a726335691c 100644
--- a/sources/MSS_Configuration/MSS_Configuration.cfg
+++ b/sources/MSS_Configuration/MSS_Configuration.cfg
@@ -644,12 +644,12 @@ LPDDR4_BANK_ADDR_WIDTH 3
LPDDR4_CA_ODT RZQ4
LPDDR4_CLOCK_DDR 800.0
LPDDR4_COL_ADDR_WIDTH 10
-LPDDR4_CONTROLLER_ADD_CMD_DRIVE 48
-LPDDR4_CONTROLLER_CLK_DRIVE 48
-LPDDR4_CONTROLLER_DQS_DRIVE 48
-LPDDR4_CONTROLLER_DQS_ODT 80
-LPDDR4_CONTROLLER_DQ_DRIVE 48
-LPDDR4_CONTROLLER_DQ_ODT 80
+LPDDR4_CONTROLLER_ADD_CMD_DRIVE 40
+LPDDR4_CONTROLLER_CLK_DRIVE 40
+LPDDR4_CONTROLLER_DQS_DRIVE 40
+LPDDR4_CONTROLLER_DQS_ODT 120
+LPDDR4_CONTROLLER_DQ_DRIVE 40
+LPDDR4_CONTROLLER_DQ_ODT 120
LPDDR4_DM_MODE DM
LPDDR4_DQDQS_TRAINING_OFFSET 1
LPDDR4_DQ_ODT RZQ2
@@ -680,7 +680,7 @@ LPDDR4_TIMING_RRD 10
LPDDR4_TIMING_RTP 7.5
LPDDR4_TIMING_WR 18
LPDDR4_TIMING_WTR 10
-LPDDR4_VREF_CA 50
+LPDDR4_VREF_CA 35
LPDDR4_VREF_CALIB_ENABLE 1
LPDDR4_VREF_CALIB_RANGE 1
LPDDR4_VREF_CALIB_VALUE 31.2