From 9b4044df5c268af3a624037e1a9cb15f15ce7a22 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Wed, 31 May 2023 21:22:07 +0100
Subject: [PATCH 01/19] MIPI-CSI: Add MIPI-CSI PHY for camera.
Camera PHY bringing camera data to cape pins for board validation
and debug.
---
.../ADD_MIPI_CSI_INTERFACE.tcl | 63 +++++
.../CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl | 223 ++++++++++++++++
.../CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl | 6 +
.../CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl | 10 +
.../CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl | 43 +++
.../IMX219_PHY_TEST/CORERESET_PF_C2.tcl | 6 +
.../IMX219_PHY_TEST/IMX219_IF_TOP.tcl | 126 +++++++++
.../MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl | 248 ++++++++++++++++++
.../constraints/MIPI_CSI_INTERFACE.pdc | 157 +++++++++++
.../mipicsi2rxdecoderPF_C0.tcl | 12 +
10 files changed, 894 insertions(+)
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
new file mode 100644
index 0000000..2fbb9b9
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
@@ -0,0 +1,63 @@
+puts "======== Add MIPI CSI option: IMX219_PHY_TEST ========"
+
+auto_promote_pad_pins -promote_all 1
+
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl
+
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
+
+
+set sd_name {BVF_GATEWARE}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {IMX219_IF_TOP} -instance_name {IMX219_IF_TOP_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[0:0]"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "IMX219_IF_TOP_0:INIT_DONE"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMCLK_RESET_N" "P8_PIN46"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMERA_CLK" "P8_PIN45"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_START" "P8_PIN44"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_VALID" "P8_PIN43"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:LINE_VALID" "P8_PIN42"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:PARALLEL_CLOCK" "P8_PIN41"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[0:0]" "P8_PIN40"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[1:1]" "P8_PIN39"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[2:2]" "P8_PIN38"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[3:3]" "P8_PIN37"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[4:4]" "P8_PIN36"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[5:5]" "P8_PIN35"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[6:6]" "P8_PIN34"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[7:7]" "P8_PIN33"}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN32} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:TRNG_RST_N} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
+
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl
new file mode 100644
index 0000000..8b56313
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.tcl
@@ -0,0 +1,223 @@
+# Creating SmartDesign CAM_IOD_TIP_TOP
+set sd_name {CAM_IOD_TIP_TOP}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_IO_CLK_PAUSE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {HS_SEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PLL_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RESTART_TRNG} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SKIP_TRNG} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRAINING_RESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_DONE} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_TRAIN_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L0_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L1_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L2_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {L3_LP_DATA} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {training_done_o} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {L0_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L1_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L2_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {L3_RXD_DATA} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add AND4_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}
+
+
+
+# Add CORERESET_PF_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_LOCK} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:INIT_DONE} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}
+
+
+
+# Add CORERXIODBITALIGN_C1_L0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L0:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L1}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L1:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L2:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add CORERXIODBITALIGN_C1_L3 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERXIODBITALIGN_C1} -instance_name {CORERXIODBITALIGN_C1_L3}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_OOR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_HOLD} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_ERR}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:BIT_ALGN_EYE_IN} -value {011}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:DEM_BIT_ALGN_TAPDLY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_LEFT_WIN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERXIODBITALIGN_C1_L3:RX_BIT_ALIGN_RGHT_WIN}
+
+
+
+# Add PF_IOD_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_GENERIC_RX_C0} -instance_name {PF_IOD_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_EARLY} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:EYE_MONITOR_LATE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_MOVE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_DIRECTION} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_LOAD} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_IOD_0:DELAY_LINE_OUT_OF_RANGE} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_0:EYE_MONITOR_WIDTH} -value {011}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CLK_TRAIN_DONE" "PF_IOD_0:CLK_TRAIN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERXIODBITALIGN_C1_L0:RESETN" "CORERXIODBITALIGN_C1_L1:RESETN" "CORERXIODBITALIGN_C1_L2:RESETN" "CORERXIODBITALIGN_C1_L3:RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:A" "CORERXIODBITALIGN_C1_L0:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "training_done_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_0:ARST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_TRAIN_ERROR" "PF_IOD_0:CLK_TRAIN_ERROR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CORERXIODBITALIGN_C1_L0:SCLK" "CORERXIODBITALIGN_C1_L1:SCLK" "CORERXIODBITALIGN_C1_L2:SCLK" "CORERXIODBITALIGN_C1_L3:SCLK" "PF_IOD_0:RX_CLK_G" "RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "TRAINING_RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_RSTRT" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_RSTRT" "RESTART_TRNG" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L1:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L2:BIT_ALGN_SKIP" "CORERXIODBITALIGN_C1_L3:BIT_ALGN_SKIP" "SKIP_TRNG" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:LP_IN" "L0_LP_DATA_N" "PF_IOD_0:L0_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L0:PLL_LOCK" "CORERXIODBITALIGN_C1_L1:PLL_LOCK" "CORERXIODBITALIGN_C1_L2:PLL_LOCK" "CORERXIODBITALIGN_C1_L3:PLL_LOCK" "PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L1:LP_IN" "L1_LP_DATA_N" "PF_IOD_0:L1_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L2:LP_IN" "L2_LP_DATA_N" "PF_IOD_0:L2_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_CLR_FLGS" "PF_IOD_0:EYE_MONITOR_CLEAR_FLAGS[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_DIR" "PF_IOD_0:DELAY_LINE_DIRECTION[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_LOAD" "PF_IOD_0:DELAY_LINE_LOAD[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:BIT_ALGN_MOVE" "PF_IOD_0:DELAY_LINE_MOVE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_EARLY" "PF_IOD_0:EYE_MONITOR_EARLY[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_LATE" "PF_IOD_0:EYE_MONITOR_LATE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:IOD_OOR" "PF_IOD_0:DELAY_LINE_OUT_OF_RANGE[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERXIODBITALIGN_C1_L3:LP_IN" "L3_LP_DATA_N" "PF_IOD_0:L3_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_IO_CLK_PAUSE" "PF_IOD_0:HS_IO_CLK_PAUSE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HS_SEL" "PF_IOD_0:HS_SEL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_LP_DATA" "PF_IOD_0:L0_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_LP_DATA" "PF_IOD_0:L1_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_LP_DATA" "PF_IOD_0:L2_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_LP_DATA" "PF_IOD_0:L3_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_N" "RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RX_CLK_P" "RX_CLK_P" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L0_RXD_DATA" "PF_IOD_0:L0_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L1_RXD_DATA" "PF_IOD_0:L1_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L2_RXD_DATA" "PF_IOD_0:L2_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"L3_RXD_DATA" "PF_IOD_0:L3_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD" "RXD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_0:RXD_N" "RXD_N" }
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign CAM_IOD_TIP_TOP
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl
new file mode 100644
index 0000000..c93e253
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERESET_PF_C1.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of CORERESET_PF_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERESET_PF_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C1} -params { }
+# Exporting Component Description of CORERESET_PF_C1 to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl
new file mode 100644
index 0000000..ff4d7d2
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CORERXIODBITALIGN_C1.tcl
@@ -0,0 +1,10 @@
+# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERXIODBITALIGN_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -component_name {CORERXIODBITALIGN_C1} -params {\
+"DEM_TAP_WAIT_CNT_WIDTH:3" \
+"HOLD_TRNG:0" \
+"MIPI_TRNG:1" \
+"SKIP_TRNG:0" }
+# Exporting Component Description of CORERXIODBITALIGN_C1 to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl
new file mode 100644
index 0000000..2be1a39
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/PF_IOD_GENERIC_RX_C0.tcl
@@ -0,0 +1,43 @@
+# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component PF_IOD_GENERIC_RX_C0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -component_name {PF_IOD_GENERIC_RX_C0} -params {\
+"CLOCK_DELAY_VALUE:0" \
+"DATA_RATE:500" \
+"DATA_RATIO:8" \
+"DATA_WIDTH:7" \
+"DDR_MODE:DDR" \
+"DYN_USE_WIDE_MODE:false" \
+"EXPOSE_CLK_TRAIN_PORTS:false" \
+"EXPOSE_DYNAMIC_DELAY_CTRL:false" \
+"EXPOSE_EXTRA_TRAINING_PORTS:false" \
+"EXPOSE_FA_CLK_DATA:false" \
+"EXPOSE_RX_RAW_DATA:false" \
+"FABRIC_CLK_SOURCE:GLOBAL" \
+"FRACTIONAL_CLOCK_RATIO:RATIO" \
+"ICB_BCLK_OFFSET:0" \
+"ICB_USE_WIDE_MODE:true" \
+"IO_NUMBER:4" \
+"NEED_LANECTRL:false" \
+"NEED_TIP:false" \
+"PLL_BCLK_OFFSET:3" \
+"RATIO:4" \
+"RXCTL_SPLIT_WIDTH:1" \
+"RXD_LVDS_FAILSAFE_EN:false" \
+"RXD_SPLIT_WIDTH:4" \
+"RX_BIT_SLIP_EN:false" \
+"RX_CLK_DIFFERENTIAL:true" \
+"RX_CLK_LVDS_FAILSAFE_EN:false" \
+"RX_CLK_SOURCE:HS_IO_CLK" \
+"RX_CLK_TO_DATA:DYNAMIC" \
+"RX_DATA_BUS_MODE:RX_DATA_PER_IO" \
+"RX_DATA_DIFFERENTIAL:true" \
+"RX_ENABLED:true" \
+"RX_INTERFACE_NAME:RX_DDRX_B_G_DYN" \
+"RX_IOG_ARCHETYPE:RX_DDRX_L_DYN_X4" \
+"RX_MIPI_MODE:true" \
+"SIMULATION_MODE:FULL" \
+"USE_SHARED_PLL:false" \
+"X1_ADD_DELAY_LINE_ON_CLOCK:false" }
+# Exporting Component Description of PF_IOD_GENERIC_RX_C0 to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
new file mode 100644
index 0000000..c01db2d
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of CORERESET_PF_C2 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component CORERESET_PF_C2
+create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {CORERESET_PF_C2} -params { }
+# Exporting Component Description of CORERESET_PF_C2 to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
new file mode 100644
index 0000000..4a984f4
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
@@ -0,0 +1,126 @@
+# Creating SmartDesign IMX219_IF_TOP
+set sd_name {IMX219_IF_TOP}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_START} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LINE_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_P} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add CORERESET_PF_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}
+
+
+
+# Add CORERESET_PF_C2_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C2} -instance_name {CORERESET_PF_C2_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:BANK_y_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C2_0:PLL_POWERDOWN_B}
+
+
+
+# Add CSI2_RXDecoder_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C0} -instance_name {CSI2_RXDecoder_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[9:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_END_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_START_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_END_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ECC_ERROR_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:CRC_ERROR_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:EBD_VALID_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:VIRTUAL_CHANNEL_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:DATA_TYPE_O}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:WORD_COUNT_O}
+
+
+
+# Add PF_CCC_C2_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0}
+
+
+
+# Add PF_IOD_GENERIC_RX_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:RESTART_TRNG} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:SKIP_TRNG} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_DONE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_ERROR}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" "PF_IOD_GENERIC_RX_C0_0:ARST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_N_I" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "FRAME_START" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "FRAME_VALID" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "LINE_VALID" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "DATA_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" }
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign IMX219_IF_TOP
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
new file mode 100644
index 0000000..89b198a
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
@@ -0,0 +1,248 @@
+# Exporting Component Description of PF_CCC_C2 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component PF_CCC_C2
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_C2} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:7" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:170" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:62.5" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:0" \
+"PLL_LOCK_COUNT_1:0" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:5" \
+"PLL_REFDIV_1:1" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C2 to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
new file mode 100644
index 0000000..83c3c75
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
@@ -0,0 +1,157 @@
+set_io -port_name CSI1_PWND \
+ -pin_name Y13 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name CAM_C_N \
+ -pin_name AB13 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name CAM_C_P \
+ -pin_name AA13 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[0]} \
+ -pin_name AB12 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[1]} \
+ -pin_name W14 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[2]} \
+ -pin_name AA15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_N[3]} \
+ -pin_name AB15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[0]} \
+ -pin_name AA12 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[1]} \
+ -pin_name Y14 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[2]} \
+ -pin_name Y15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name {CAM_D_P[3]} \
+ -pin_name AB14 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+
+set_io -port_name P8_PIN32 \
+ -pin_name B15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN33 \
+ -pin_name A15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN34 \
+ -pin_name C15 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN35 \
+ -pin_name C14 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN36 \
+ -pin_name B4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN37 \
+ -pin_name C4 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN38 \
+ -pin_name C17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN39 \
+ -pin_name B17 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN40 \
+ -pin_name B18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN41 \
+ -pin_name A18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN42 \
+ -pin_name D6 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN43 \
+ -pin_name D7 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN44 \
+ -pin_name D8 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN45 \
+ -pin_name D9 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN46 \
+ -pin_name D18 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
new file mode 100644
index 0000000..98f843d
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-1FCG1152E
+# Create and Configure the core component mipicsi2rxdecoderPF_C0
+create_and_configure_core -core_vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -component_name {mipicsi2rxdecoderPF_C0} -params {\
+"g_DATAWIDTH:10" \
+"g_FIFO_SIZE:12" \
+"g_FORMAT:0" \
+"g_INPUT_DATA_INVERT:0" \
+"g_LANE_WIDTH:4" \
+"g_NUM_OF_PIXELS:1" }
+# Exporting Component Description of mipicsi2rxdecoderPF_C0 to TCL done
--
GitLab
From 58d3a123c213f6dd41e719b943db1c9d44068cb6 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Tue, 4 Jul 2023 16:39:32 +0100
Subject: [PATCH 02/19] MIPI-CSI: Correct CSI-PWDN signal polarity.
---
.../MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
index 2fbb9b9..b1d7035 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
@@ -57,7 +57,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[4:4]"
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[5:5]" "P8_PIN35"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[6:6]" "P8_PIN34"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[7:7]" "P8_PIN33"}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
+
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN32} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:TRNG_RST_N} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
--
GitLab
From dadeb78e07fd5365df376489d04d374726ece9ce Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 16 Jul 2023 18:48:27 +0100
Subject: [PATCH 03/19] MIPI-CSI: Handle variable design names.
---
.../MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
index b1d7035..5b54374 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
@@ -13,7 +13,7 @@ source script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
-set sd_name {BVF_GATEWARE}
+set sd_name ${top_level_name}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
--
GitLab
From e14cdd10b70b6687f96dc245d7ba92d311bfc9a6 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Thu, 20 Jul 2023 20:07:58 +0100
Subject: [PATCH 04/19] MIPI_CSI: Add GPIO to read status for board tests.
---
.../ADD_MIPI_CSI_INTERFACE.tcl | 50 ++-----
.../IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl | 138 ++++++++++++++++++
.../IMX219_PHY_TEST/IMX219_IF_TOP.tcl | 66 ++++++++-
.../constraints/MIPI_CSI_INTERFACE.pdc | 93 ------------
4 files changed, 208 insertions(+), 139 deletions(-)
create mode 100644 script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
index 5b54374..ef59270 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/ADD_MIPI_CSI_INTERFACE.tcl
@@ -10,56 +10,30 @@ source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CAM_IOD_TIP_TOP/CAM_IO
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CORERESET_PF_C2.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/PF_CCC_C2.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/mipicsi2rxdecoderPF_C0.tcl
+source script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl
source script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
set sd_name ${top_level_name}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN37} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN38} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI1_PWND} -port_direction {OUT}
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX219_IF_TOP} -instance_name {IMX219_IF_TOP_0}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {IMX219_IF_TOP_0:DATA_OUT} -pin_slices {"[0:0]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "IMX219_IF_TOP_0:INIT_DONE"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMCLK_RESET_N" "P8_PIN46"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:CAMERA_CLK" "P8_PIN45"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_START" "P8_PIN44"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:FRAME_VALID" "P8_PIN43"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:LINE_VALID" "P8_PIN42"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:PARALLEL_CLOCK" "P8_PIN41"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[0:0]" "P8_PIN40"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[1:1]" "P8_PIN39"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[2:2]" "P8_PIN38"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[3:3]" "P8_PIN37"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[4:4]" "P8_PIN36"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[5:5]" "P8_PIN35"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[6:6]" "P8_PIN34"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX219_IF_TOP_0:DATA_OUT[7:7]" "P8_PIN33"}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CSI1_PWND} -value {VCC}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN32} -value {GND}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "IMX219_IF_TOP_0:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "IMX219_IF_TOP_0:PRESETN"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:CSI_APB_MTARGET" "IMX219_IF_TOP_0:APB_TARGET"}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:CAMCLK_RESET_N}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:CAMERA_CLK}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:FRAME_START}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:FRAME_VALID}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:LINE_VALID}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:PARALLEL_CLOCK}
+
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX219_IF_TOP_0:TRNG_RST_N} -value {VCC}
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl
new file mode 100644
index 0000000..0ae8425
--- /dev/null
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/CoreGPIO_MIPI_CSI.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_MIPI_CSI to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_MIPI_CSI
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_MIPI_CSI} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:false" \
+"FIXED_CONFIG_12:false" \
+"FIXED_CONFIG_13:false" \
+"FIXED_CONFIG_14:false" \
+"FIXED_CONFIG_15:false" \
+"FIXED_CONFIG_16:false" \
+"FIXED_CONFIG_17:false" \
+"FIXED_CONFIG_18:false" \
+"FIXED_CONFIG_19:false" \
+"FIXED_CONFIG_20:false" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:11" \
+"IO_TYPE_0:0" \
+"IO_TYPE_1:0" \
+"IO_TYPE_2:0" \
+"IO_TYPE_3:0" \
+"IO_TYPE_4:0" \
+"IO_TYPE_5:0" \
+"IO_TYPE_6:0" \
+"IO_TYPE_7:0" \
+"IO_TYPE_8:0" \
+"IO_TYPE_9:0" \
+"IO_TYPE_10:0" \
+"IO_TYPE_11:0" \
+"IO_TYPE_12:0" \
+"IO_TYPE_13:0" \
+"IO_TYPE_14:0" \
+"IO_TYPE_15:0" \
+"IO_TYPE_16:0" \
+"IO_TYPE_17:0" \
+"IO_TYPE_18:0" \
+"IO_TYPE_19:0" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of CoreGPIO_MIPI_CSI to TCL done
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
index 4a984f4..a31f068 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/IMX219_IF_TOP.tcl
@@ -6,11 +6,18 @@ create_smartdesign -sd_name ${sd_name}
auto_promote_pad_pins -promote_all 0
# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_C_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_START} -port_direction {OUT}
@@ -20,17 +27,57 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_dire
# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_D_P} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
-sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_TARGET_PADDR" \
+"PSELx:APB_TARGET_PSEL" \
+"PENABLE:APB_TARGET_PENABLE" \
+"PWRITE:APB_TARGET_PWRITE" \
+"PRDATA:APB_TARGET_PRDATA" \
+"PWDATA:APB_TARGET_PWDATA" \
+"PREADY:APB_TARGET_PREADY" \
+"PSLVERR:APB_TARGET_PSLVERR" }
+
# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+# Add CoreGPIO_MIPI_CSI_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_MIPI_CSI} -instance_name {CoreGPIO_MIPI_CSI_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[10:10]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[10:10]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[3:3]} -value {VCC}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[4:4]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[4:4]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[5:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[5:5]} -value {VCC}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[6:6]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[6:6]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[7:7]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[7:7]} -value {VCC}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[8:8]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[8:8]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_MIPI_CSI_0:GPIO_IN} -pin_slices {[9:9]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_IN[9:9]} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_MIPI_CSI_0:GPIO_OE}
+
+
+
# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
@@ -88,16 +135,16 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_T
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C2_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "PF_IOD_GENERIC_RX_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CORERESET_PF_C2_0:CLK" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_C_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "CORERESET_PF_C2_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "CORERESET_PF_C2_0:INIT_DONE" "INIT_DONE" "PF_IOD_GENERIC_RX_C0_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C2_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:RESET_N_I" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "FRAME_START" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "FRAME_VALID" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_START_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[1:1]" "FRAME_START" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:FRAME_VALID_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[0:0]" "FRAME_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" }
@@ -106,17 +153,20 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I"
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "LINE_VALID" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "CoreGPIO_MIPI_CSI_0:GPIO_IN[2:2]" "LINE_VALID" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_MIPI_CSI_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_MIPI_CSI_0:PRESETN" "PRESETN" }
# Add bus net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "DATA_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_D_P" "PF_IOD_GENERIC_RX_C0_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" }
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "CoreGPIO_MIPI_CSI_0:APB_bif" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
diff --git a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
index 83c3c75..e6909e4 100644
--- a/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
+++ b/script_support/components/MIPI_CSI/IMX219_PHY_TEST/constraints/MIPI_CSI_INTERFACE.pdc
@@ -62,96 +62,3 @@ set_io -port_name {CAM_D_P[3]} \
-pin_name AB14 \
-fixed true \
-DIRECTION OUTPUT
-
-
-
-set_io -port_name P8_PIN32 \
- -pin_name B15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN33 \
- -pin_name A15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN34 \
- -pin_name C15 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN35 \
- -pin_name C14 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN36 \
- -pin_name B4 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN37 \
- -pin_name C4 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN38 \
- -pin_name C17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN39 \
- -pin_name B17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN40 \
- -pin_name B18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN41 \
- -pin_name A18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN42 \
- -pin_name D6 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN43 \
- -pin_name D7 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN44 \
- -pin_name D8 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN45 \
- -pin_name D9 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN46 \
- -pin_name D18 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
--
GitLab
From fc8eec11b3a868e9e8c954a02309cef9ffe0dd98 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Fri, 21 Jul 2023 10:39:03 +0100
Subject: [PATCH 05/19] Build options: Use "DEFAULT" for all gateware
components.
All gateware components now use the "DEFAULT" directory for their
default configuration. Previously a mix of "DEFAULT" and "NONE" were
used depending on the gateware component.
---
BUILD_BVF_GATEWARE.tcl | 4 ++--
.../HIGH_SPEED_CONNECTOR/DEFAULT/ADD_HIGH_SPEED_CONNECTOR.tcl | 0
.../DEFAULT/constraints/HIGH_SPEED_CONNECTOR.pdc | 0
.../components/MIPI_CSI/DEFAULT/ADD_MIPI_CSI_INTERFACE.tcl | 0
.../MIPI_CSI/DEFAULT/constraints/MIPI_CSI_INTERFACE.pdc | 0
5 files changed, 2 insertions(+), 2 deletions(-)
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/ADD_HIGH_SPEED_CONNECTOR.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/MIPI_CSI/DEFAULT/ADD_MIPI_CSI_INTERFACE.tcl
create mode 100644 script_support/components/MIPI_CSI/DEFAULT/constraints/MIPI_CSI_INTERFACE.pdc
diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index 963a974..2b438c4 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -89,14 +89,14 @@ puts "M.2 option selected: $m2_option"
if {[info exists HIGH_SPEED_CONN_OPTION]} {
set high_speed_conn_option "$HIGH_SPEED_CONN_OPTION"
} else {
- set high_speed_conn_option "NONE"
+ set high_speed_conn_option "DEFAULT"
}
puts "High speed connector option option selected: $high_speed_conn_option"
if {[info exists MIPI_CSI_OPTION]} {
set mipi_csi_option "$MIPI_CSI_OPTION"
} else {
- set mipi_csi_option "NONE"
+ set mipi_csi_option "DEFAULT"
}
puts "MIPI CSI option option selected: $mipi_csi_option"
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/ADD_HIGH_SPEED_CONNECTOR.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/ADD_HIGH_SPEED_CONNECTOR.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..e69de29
diff --git a/script_support/components/MIPI_CSI/DEFAULT/ADD_MIPI_CSI_INTERFACE.tcl b/script_support/components/MIPI_CSI/DEFAULT/ADD_MIPI_CSI_INTERFACE.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/script_support/components/MIPI_CSI/DEFAULT/constraints/MIPI_CSI_INTERFACE.pdc b/script_support/components/MIPI_CSI/DEFAULT/constraints/MIPI_CSI_INTERFACE.pdc
new file mode 100644
index 0000000..e69de29
--
GitLab
From f6dd4349a50a9e33c667d1254441f8c54f9af7b6 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Fri, 21 Jul 2023 11:35:23 +0100
Subject: [PATCH 06/19] Pin constraints: Correct I2C pins assignment on P9
header.
---
script_support/constraints/base_design.pdc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/script_support/constraints/base_design.pdc b/script_support/constraints/base_design.pdc
index fde5025..933f4cb 100644
--- a/script_support/constraints/base_design.pdc
+++ b/script_support/constraints/base_design.pdc
@@ -55,13 +55,13 @@ set_io -port_name P9_13 \
-DIRECTION OUTPUT
set_io -port_name P9_19 \
- -pin_name A11 \
+ -pin_name A10 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
set_io -port_name P9_20 \
- -pin_name A10 \
+ -pin_name A11 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
--
GitLab
From 68ac1551bda012541621044cfb028e1ae5b7c578 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sat, 22 Jul 2023 10:02:31 +0100
Subject: [PATCH 07/19] Core design: Optimize MSS GPIO_2 usage.
---
script_support/MSS_Configuration.cfg | 91 ++++++++++---------
.../components/BVF_RISCV_SUBSYSTEM.tcl | 23 +++--
.../components/CAPE/DEFAULT/CAPE.tcl | 3 +-
.../CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl | 22 ++---
.../components/CAPE/DEFAULT/P8_GPIO_LCD.tcl | 13 +--
script_support/components/CAPE/GPIOS/CAPE.tcl | 5 +-
.../CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl | 22 ++---
.../components/CAPE/GPIOS/CoreGPIO_LCD.tcl | 4 +-
.../components/CAPE/GPIOS/P8_GPIO_LCD.tcl | 11 +--
9 files changed, 91 insertions(+), 103 deletions(-)
diff --git a/script_support/MSS_Configuration.cfg b/script_support/MSS_Configuration.cfg
index 879c3e5..8cd805b 100644
--- a/script_support/MSS_Configuration.cfg
+++ b/script_support/MSS_Configuration.cfg
@@ -147,14 +147,18 @@ DDR4_ZQ_CALIB_TYPE 0
DDR4_ZQ_CAL_INIT_TIME 1024
DDR4_ZQ_CAL_L_TIME 512
DDR4_ZQ_CAL_S_TIME 128
-DDR_CACHED_32BIT_MEM_SIZE 32
-DDR_CACHED_32BIT_MEM_UNIT MB
-DDR_CACHED_64BIT_MEM_SIZE 1888
-DDR_CACHED_64BIT_MEM_UNIT MB
-DDR_NON_CACHED_32BIT_MEM_SIZE 128
+DDR_CACHED_32BIT_MEM_SIZE 1
+DDR_CACHED_32BIT_MEM_UNIT GB
+DDR_CACHED_32BIT_PHY_OFFSET 0x0
+DDR_CACHED_64BIT_MEM_SIZE 2
+DDR_CACHED_64BIT_MEM_UNIT GB
+DDR_CACHED_64BIT_PHY_OFFSET 0x0
+DDR_NON_CACHED_32BIT_MEM_SIZE 256
DDR_NON_CACHED_32BIT_MEM_UNIT MB
-DDR_NON_CACHED_64BIT_MEM_SIZE 0
+DDR_NON_CACHED_32BIT_PHY_OFFSET 0x0
+DDR_NON_CACHED_64BIT_MEM_SIZE 2
DDR_NON_CACHED_64BIT_MEM_UNIT GB
+DDR_NON_CACHED_64BIT_PHY_OFFSET 0x0
DDR_REFCLK DEDICATED_IO
DDR_SDRAM_TYPE LPDDR4
DIE MPFS025T
@@ -163,7 +167,7 @@ EMMC_DATA_7_4 MSSIO_B4
EMMC_SD_CLK_SOURCE MSS_PLL
EMMC_SD_SDIO_FREQ 200
EMMC_SD_SWITCHING DISABLED
-EMMC_SPEED_MODE DEFAULT_SPEED
+EMMC_SPEED_MODE HIGH_SPEED_400_ES
ENABLE_FEEDBACK_PORTS false
EXPOSE_BOOT_STATUS_PORTS false
FF_IN_PROGRESS UNUSED
@@ -307,12 +311,12 @@ GPIO_2_25 FABRIC
GPIO_2_25_DIR BI
GPIO_2_26 FABRIC
GPIO_2_26_DIR BI
-GPIO_2_27 UNUSED
-GPIO_2_27_DIR IN
-GPIO_2_28 UNUSED
-GPIO_2_28_DIR IN
-GPIO_2_29 UNUSED
-GPIO_2_29_DIR IN
+GPIO_2_27 FABRIC
+GPIO_2_27_DIR BI
+GPIO_2_28 FABRIC
+GPIO_2_28_DIR OUT
+GPIO_2_29 FABRIC
+GPIO_2_29_DIR OUT
GPIO_2_2_DIR BI
GPIO_2_3 FABRIC
GPIO_2_30 FABRIC
@@ -640,12 +644,12 @@ LPDDR4_BANK_ADDR_WIDTH 3
LPDDR4_CA_ODT RZQ4
LPDDR4_CLOCK_DDR 800.0
LPDDR4_COL_ADDR_WIDTH 10
-LPDDR4_CONTROLLER_ADD_CMD_DRIVE 34
-LPDDR4_CONTROLLER_CLK_DRIVE 34
-LPDDR4_CONTROLLER_DQS_DRIVE 40
-LPDDR4_CONTROLLER_DQS_ODT 40
-LPDDR4_CONTROLLER_DQ_DRIVE 40
-LPDDR4_CONTROLLER_DQ_ODT 40
+LPDDR4_CONTROLLER_ADD_CMD_DRIVE 48
+LPDDR4_CONTROLLER_CLK_DRIVE 48
+LPDDR4_CONTROLLER_DQS_DRIVE 48
+LPDDR4_CONTROLLER_DQS_ODT 80
+LPDDR4_CONTROLLER_DQ_DRIVE 48
+LPDDR4_CONTROLLER_DQ_ODT 80
LPDDR4_DM_MODE DM
LPDDR4_DQDQS_TRAINING_OFFSET 1
LPDDR4_DQ_ODT RZQ2
@@ -656,10 +660,10 @@ LPDDR4_MEMORY_FORMAT COMPONENT
LPDDR4_ODTE_CA 0
LPDDR4_ODTE_CK 0
LPDDR4_ODTE_CS 0
-LPDDR4_PULLUP_CAL VDDQ3
+LPDDR4_PULLUP_CAL VDDQ2P5
LPDDR4_RD_POSTAMBLE CK0P5
LPDDR4_RD_PREAMBLE STATIC
-LPDDR4_READ_LATENCY RL14
+LPDDR4_READ_LATENCY RL28
LPDDR4_ROW_ADDR_WIDTH 16
LPDDR4_SELF_REFRESH_ABORT_MODE 0
LPDDR4_SOC_ODT RZQ6
@@ -669,20 +673,20 @@ LPDDR4_TIMING_MRW 10
LPDDR4_TIMING_RAS 42
LPDDR4_TIMING_RC 63
LPDDR4_TIMING_RCD 18
-LPDDR4_TIMING_REFI 3.905
-LPDDR4_TIMING_RFC 380
+LPDDR4_TIMING_REFI 3.9
+LPDDR4_TIMING_RFC 280
LPDDR4_TIMING_RP 21
LPDDR4_TIMING_RRD 10
-LPDDR4_TIMING_RTP 10
+LPDDR4_TIMING_RTP 7.5
LPDDR4_TIMING_WR 18
-LPDDR4_TIMING_WTR 8
+LPDDR4_TIMING_WTR 10
LPDDR4_VREF_CA 50
LPDDR4_VREF_CALIB_ENABLE 1
LPDDR4_VREF_CALIB_RANGE 1
LPDDR4_VREF_CALIB_VALUE 31.2
LPDDR4_VREF_DATA 15
LPDDR4_WIDTH 32
-LPDDR4_WRITE_LATENCY WL8
+LPDDR4_WRITE_LATENCY WL14
LPDDR4_WR_POSTAMBLE CK0P5
LPDDR4_ZQ_CALIB_PERIOD 200
LPDDR4_ZQ_CAL_LATCH_TIME 30
@@ -718,7 +722,7 @@ MSSIO_0_LPMD_IBUF false
MSSIO_0_LPMD_OBUF false
MSSIO_0_LP_PERSIST false
MSSIO_0_MD_IBUF true
-MSSIO_0_OUT_DRIVE 8
+MSSIO_0_OUT_DRIVE 10
MSSIO_0_RES_PULL UP
MSSIO_0_SCHMITT_TRIGGER false
MSSIO_10_ATP_EN false
@@ -727,7 +731,7 @@ MSSIO_10_LPMD_IBUF false
MSSIO_10_LPMD_OBUF false
MSSIO_10_LP_PERSIST false
MSSIO_10_MD_IBUF true
-MSSIO_10_OUT_DRIVE 8
+MSSIO_10_OUT_DRIVE 10
MSSIO_10_RES_PULL UP
MSSIO_10_SCHMITT_TRIGGER false
MSSIO_11_ATP_EN false
@@ -736,7 +740,7 @@ MSSIO_11_LPMD_IBUF false
MSSIO_11_LPMD_OBUF false
MSSIO_11_LP_PERSIST false
MSSIO_11_MD_IBUF true
-MSSIO_11_OUT_DRIVE 8
+MSSIO_11_OUT_DRIVE 10
MSSIO_11_RES_PULL UP
MSSIO_11_SCHMITT_TRIGGER false
MSSIO_12_ATP_EN false
@@ -745,7 +749,7 @@ MSSIO_12_LPMD_IBUF false
MSSIO_12_LPMD_OBUF false
MSSIO_12_LP_PERSIST false
MSSIO_12_MD_IBUF true
-MSSIO_12_OUT_DRIVE 8
+MSSIO_12_OUT_DRIVE 10
MSSIO_12_RES_PULL UP
MSSIO_12_SCHMITT_TRIGGER false
MSSIO_13_ATP_EN false
@@ -817,7 +821,7 @@ MSSIO_1_LPMD_IBUF false
MSSIO_1_LPMD_OBUF false
MSSIO_1_LP_PERSIST false
MSSIO_1_MD_IBUF true
-MSSIO_1_OUT_DRIVE 8
+MSSIO_1_OUT_DRIVE 10
MSSIO_1_RES_PULL UP
MSSIO_1_SCHMITT_TRIGGER false
MSSIO_20_ATP_EN false
@@ -916,7 +920,7 @@ MSSIO_2_LPMD_IBUF false
MSSIO_2_LPMD_OBUF false
MSSIO_2_LP_PERSIST false
MSSIO_2_MD_IBUF true
-MSSIO_2_OUT_DRIVE 8
+MSSIO_2_OUT_DRIVE 10
MSSIO_2_RES_PULL UP
MSSIO_2_SCHMITT_TRIGGER false
MSSIO_30_ATP_EN false
@@ -997,7 +1001,7 @@ MSSIO_3_LPMD_IBUF false
MSSIO_3_LPMD_OBUF false
MSSIO_3_LP_PERSIST false
MSSIO_3_MD_IBUF true
-MSSIO_3_OUT_DRIVE 8
+MSSIO_3_OUT_DRIVE 10
MSSIO_3_RES_PULL UP
MSSIO_3_SCHMITT_TRIGGER false
MSSIO_4_ATP_EN false
@@ -1006,7 +1010,7 @@ MSSIO_4_LPMD_IBUF false
MSSIO_4_LPMD_OBUF false
MSSIO_4_LP_PERSIST false
MSSIO_4_MD_IBUF true
-MSSIO_4_OUT_DRIVE 8
+MSSIO_4_OUT_DRIVE 10
MSSIO_4_RES_PULL UP
MSSIO_4_SCHMITT_TRIGGER false
MSSIO_5_ATP_EN false
@@ -1015,7 +1019,7 @@ MSSIO_5_LPMD_IBUF false
MSSIO_5_LPMD_OBUF false
MSSIO_5_LP_PERSIST false
MSSIO_5_MD_IBUF true
-MSSIO_5_OUT_DRIVE 8
+MSSIO_5_OUT_DRIVE 10
MSSIO_5_RES_PULL UP
MSSIO_5_SCHMITT_TRIGGER false
MSSIO_6_ATP_EN false
@@ -1033,7 +1037,7 @@ MSSIO_7_LPMD_IBUF false
MSSIO_7_LPMD_OBUF false
MSSIO_7_LP_PERSIST false
MSSIO_7_MD_IBUF true
-MSSIO_7_OUT_DRIVE 8
+MSSIO_7_OUT_DRIVE 10
MSSIO_7_RES_PULL UP
MSSIO_7_SCHMITT_TRIGGER false
MSSIO_8_ATP_EN false
@@ -1042,7 +1046,7 @@ MSSIO_8_LPMD_IBUF false
MSSIO_8_LPMD_OBUF false
MSSIO_8_LP_PERSIST false
MSSIO_8_MD_IBUF true
-MSSIO_8_OUT_DRIVE 8
+MSSIO_8_OUT_DRIVE 10
MSSIO_8_RES_PULL UP
MSSIO_8_SCHMITT_TRIGGER false
MSSIO_9_ATP_EN false
@@ -1051,7 +1055,7 @@ MSSIO_9_LPMD_IBUF false
MSSIO_9_LPMD_OBUF false
MSSIO_9_LP_PERSIST false
MSSIO_9_MD_IBUF true
-MSSIO_9_OUT_DRIVE 8
+MSSIO_9_OUT_DRIVE 10
MSSIO_9_RES_PULL UP
MSSIO_9_SCHMITT_TRIGGER false
MSSIO_REFCLK_IOSTD LVDS25
@@ -1062,11 +1066,12 @@ MSSIO_REFCLK_THEVENIN OFF
MSS_AHB_APB_CLK_DIV 4
MSS_AXI_CLK_DIV 2
MSS_CLK_DIV 1
+MSS_MANUAL_DDR_PHY_OFFSET_ENABLE true
MSS_PLLOUT_FREQ 600.000
MSS_PMP_ENABLE false
MSS_REFCLK DEDICATED_IO
PACKAGE FCVG484
-PFSOC_MSS_VERSION 2022.2
+PFSOC_MSS_VERSION 2022.3
PLL_NW_REFCLK0_FREQ 100
PLL_NW_REFCLK1_FREQ 125
PMP_CAN0_CONTEXT_A_EN true
@@ -1097,10 +1102,10 @@ PMP_INITIATOR_U54_1_CONTEXT_A_EN true
PMP_INITIATOR_U54_1_CONTEXT_B_EN false
PMP_INITIATOR_U54_2_CONTEXT_A_EN true
PMP_INITIATOR_U54_2_CONTEXT_B_EN false
-PMP_INITIATOR_U54_3_CONTEXT_A_EN false
-PMP_INITIATOR_U54_3_CONTEXT_B_EN true
-PMP_INITIATOR_U54_4_CONTEXT_A_EN false
-PMP_INITIATOR_U54_4_CONTEXT_B_EN true
+PMP_INITIATOR_U54_3_CONTEXT_A_EN true
+PMP_INITIATOR_U54_3_CONTEXT_B_EN false
+PMP_INITIATOR_U54_4_CONTEXT_A_EN true
+PMP_INITIATOR_U54_4_CONTEXT_B_EN false
PMP_MMUART1_CONTEXT_A_EN true
PMP_MMUART1_CONTEXT_B_EN false
PMP_MMUART2_CONTEXT_A_EN true
diff --git a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
index 8c85360..83be93c 100644
--- a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
+++ b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
@@ -66,9 +66,9 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {USER_BUTTON} -port_directi
sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_CARD_CS} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SD_DET} -port_direction {IN}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_M2F} -port_direction {OUT} -port_range {[26:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_OE_M2F} -port_direction {OUT} -port_range {[26:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_F2M} -port_direction {IN} -port_range {[26:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_M2F} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_OE_M2F} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_2_F2M} -port_direction {IN} -port_range {[27:0]}
#-------------------------------------------------------------------------------
# Analog to Digital Converter pins (for cape analog inputs)
@@ -170,6 +170,11 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:I2C_0_SDA_F2M" "I2C0
sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C0_SDA_BIBUF:PAD" "I2C0_SDA"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"I2C0_SCL_BIBUF:PAD" "I2C0_SCL"}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_W_DISABLE1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_W_DISABLE2} -port_direction {OUT}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_W_DISABLE1" "PF_SOC_MSS:GPIO_2_M2F_28"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_W_DISABLE2" "PF_SOC_MSS:GPIO_2_M2F_29"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:I2C_1_SCL" "I2C_1_SCL" }
@@ -334,7 +339,7 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {PF_SOC_MSS:FIC_3_APB_M_PST
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[30:30]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[27:27]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[24:24]"}
@@ -366,7 +371,7 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_F2M} -pin_slices {"[0
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[30:30]" "PF_SOC_MSS:GPIO_2_F2M_30"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[29:29]" "PF_SOC_MSS:GPIO_2_F2M_29"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[28:28]" "PF_SOC_MSS:GPIO_2_F2M_28"}
-#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[27:27]" "PF_SOC_MSS:GPIO_2_F2M_27"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[27:27]" "PF_SOC_MSS:GPIO_2_F2M_27"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[26:26]" "PF_SOC_MSS:GPIO_2_F2M_26"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[25:25]" "PF_SOC_MSS:GPIO_2_F2M_25"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[24:24]" "PF_SOC_MSS:GPIO_2_F2M_24"}
@@ -401,7 +406,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_F2M[0:0]" "PF_SOC_MSS:GP
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[30:30]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[27:27]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[24:24]"}
@@ -433,7 +438,7 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_M2F} -pin_slices {"[0
#sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_30" "GPIO_2_M2F[30:30]"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_29" "GPIO_2_M2F[29:29]"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_28" "GPIO_2_M2F[28:28]"}
-#sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_27" "GPIO_2_M2F[27:27]"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_27" "GPIO_2_M2F[27:27]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_26" "GPIO_2_M2F[26:26]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_25" "GPIO_2_M2F[25:25]"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_24" "GPIO_2_M2F[24:24]"}
@@ -467,7 +472,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:GPIO_2_M2F_0" "GPIO_
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[30:30]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[27:27]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {"[24:24]"}
@@ -500,7 +505,7 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {GPIO_2_OE_M2F} -pin_slices {
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[30:30]" "PF_SOC_MSS:GPIO_2_OE_M2F_30"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[29:29]" "PF_SOC_MSS:GPIO_2_OE_M2F_29"}
#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[28:28]" "PF_SOC_MSS:GPIO_2_OE_M2F_28"}
-#sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[27:27]" "PF_SOC_MSS:GPIO_2_OE_M2F_27"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[27:27]" "PF_SOC_MSS:GPIO_2_OE_M2F_27"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[26:26]" "PF_SOC_MSS:GPIO_2_OE_M2F_26"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[25:25]" "PF_SOC_MSS:GPIO_2_OE_M2F_25"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_OE_M2F[24:24]" "PF_SOC_MSS:GPIO_2_OE_M2F_24"}
diff --git a/script_support/components/CAPE/DEFAULT/CAPE.tcl b/script_support/components/CAPE/DEFAULT/CAPE.tcl
index 8154e93..af2d92e 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -63,7 +63,7 @@ sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_na
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_4}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_28}
#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_28_PAD} -new_port_name {P8_5}
#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_29_PAD} -new_port_name {P8_6}
#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_30_PAD} -new_port_name {P8_7}
@@ -97,7 +97,6 @@ sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_nam
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_PCLK} -new_port_name {P8_28}
#-------------------------------------------------------------------------------
diff --git a/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl b/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
index a324423..22e5fd9 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
@@ -31,14 +31,14 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPI
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_24_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_25_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_26_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_28_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_29_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_30_BIBUF}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[2:2]"}
@@ -66,13 +66,13 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_sli
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[30:30]"}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[2:2]"}
@@ -100,13 +100,13 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[30:30]"}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[2:2]"}
@@ -134,7 +134,7 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[30:30]"}
@@ -167,7 +167,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:D" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:D" "GPIO_OUT[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:D" "GPIO_OUT[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:D" "GPIO_OUT[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:D" "GPIO_OUT[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:D" "GPIO_OUT[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:D" "GPIO_OUT[30:30]"}
@@ -200,7 +200,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:E" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:E" "GPIO_OE[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:E" "GPIO_OE[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:E" "GPIO_OE[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:E" "GPIO_OE[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:E" "GPIO_OE[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:E" "GPIO_OE[30:30]"}
@@ -233,7 +233,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:Y" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:Y" "GPIO_IN[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:Y" "GPIO_IN[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:Y" "GPIO_IN[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:Y" "GPIO_IN[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:Y" "GPIO_IN[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:Y" "GPIO_IN[30:30]"}
@@ -266,7 +266,7 @@ sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_22} -new_po
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_port_name {GPIO_24_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_25_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_25} -new_port_name {GPIO_26_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_27} -new_port_name {GPIO_28_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_28} -new_port_name {GPIO_29_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_29} -new_port_name {GPIO_30_PAD}
diff --git a/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl b/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
index ea0ab46..7461e9e 100644
--- a/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+++ b/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
@@ -27,7 +27,6 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_PCLK_GPIO_BIBUF}
@@ -38,7 +37,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"FIXED_CONFIG_0:true" "FIXED_CONFIG_1:true" "FIXED_CONFIG_2:true" "FIXED_CONFIG_3:true" "FIXED_CONFIG_4:true" \
"FIXED_CONFIG_5:true" "FIXED_CONFIG_6:true" "FIXED_CONFIG_7:true" "FIXED_CONFIG_8:true" "FIXED_CONFIG_9:true" \
"FIXED_CONFIG_10:true" "FIXED_CONFIG_11:true" "FIXED_CONFIG_12:true" "FIXED_CONFIG_13:true" "FIXED_CONFIG_14:true" \
-"FIXED_CONFIG_15:true" "FIXED_CONFIG_16:true" "FIXED_CONFIG_17:true" "FIXED_CONFIG_18:true" "FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_15:true" "FIXED_CONFIG_16:true" "FIXED_CONFIG_17:true" "FIXED_CONFIG_18:true" "FIXED_CONFIG_19:false" \
"FIXED_CONFIG_20:false" "FIXED_CONFIG_21:false" "FIXED_CONFIG_22:false" "FIXED_CONFIG_23:false" "FIXED_CONFIG_24:false" \
"FIXED_CONFIG_25:false" "FIXED_CONFIG_26:false" "FIXED_CONFIG_27:false" "FIXED_CONFIG_28:false" "FIXED_CONFIG_29:false" \
"FIXED_CONFIG_30:false" "FIXED_CONFIG_31:false" \
@@ -50,7 +49,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_INT_TYPE_20:7" "IO_INT_TYPE_21:7" "IO_INT_TYPE_22:7" "IO_INT_TYPE_23:7" "IO_INT_TYPE_24:7" \
"IO_INT_TYPE_25:7" "IO_INT_TYPE_26:7" "IO_INT_TYPE_27:7" "IO_INT_TYPE_28:7" "IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" "IO_INT_TYPE_31:7" \
-"IO_NUM:20" \
+"IO_NUM:19" \
"IO_TYPE_0:2" "IO_TYPE_1:2" "IO_TYPE_2:2" "IO_TYPE_3:2" "IO_TYPE_4:2" "IO_TYPE_5:2" "IO_TYPE_6:2" "IO_TYPE_7:2" "IO_TYPE_8:2" "IO_TYPE_9:2" \
"IO_TYPE_10:2" "IO_TYPE_11:2" "IO_TYPE_12:2" "IO_TYPE_13:2" "IO_TYPE_14:2" "IO_TYPE_15:2" "IO_TYPE_16:2" "IO_TYPE_17:2" "IO_TYPE_18:2" "IO_TYPE_19:2" \
"IO_TYPE_20:0" "IO_TYPE_21:0" "IO_TYPE_22:0" "IO_TYPE_23:0" "IO_TYPE_24:0" "IO_TYPE_25:0" "IO_TYPE_26:0" "IO_TYPE_27:0" "IO_TYPE_28:0" "IO_TYPE_29:0" \
@@ -62,7 +61,6 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"OE_TYPE:0"}
sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[16:16]"}
@@ -82,7 +80,6 @@ sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[16:16]"}
@@ -102,7 +99,6 @@ sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[19:19]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[18:18]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[17:17]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[16:16]"}
@@ -200,10 +196,6 @@ sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[18:1
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[18:18]" "LCD_VSYNC_GPIO_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[18:18]" "LCD_VSYNC_GPIO_BIBUF:E"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[19:19]" "LCD_PCLK_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[19:19]" "LCD_PCLK_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[19:19]" "LCD_PCLK_GPIO_BIBUF:E"}
-
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD} -new_port_name {LCD_DATA0}
@@ -226,7 +218,6 @@ sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {LCD_HSYNC}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {LCD_AC_BIAS}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {LCD_VSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {LCD_PCLK}
sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {}
diff --git a/script_support/components/CAPE/GPIOS/CAPE.tcl b/script_support/components/CAPE/GPIOS/CAPE.tcl
index c962d8b..12d4de8 100644
--- a/script_support/components/CAPE/GPIOS/CAPE.tcl
+++ b/script_support/components/CAPE/GPIOS/CAPE.tcl
@@ -63,10 +63,7 @@ sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_na
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_4}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_28_PAD} -new_port_name {P8_5}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_29_PAD} -new_port_name {P8_6}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_30_PAD} -new_port_name {P8_7}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P9_42}
#-------------------------------------------------------------------------------
diff --git a/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl b/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
index a324423..22e5fd9 100644
--- a/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
+++ b/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
@@ -31,14 +31,14 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPI
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_24_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_25_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_26_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_28_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_29_BIBUF}
#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_30_BIBUF}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[2:2]"}
@@ -66,13 +66,13 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_sli
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[30:30]"}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[2:2]"}
@@ -100,13 +100,13 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[30:30]"}
-sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[26:0]}
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[0:0]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[2:2]"}
@@ -134,7 +134,7 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[24:24]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[26:26]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[28:28]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[29:29]"}
#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[30:30]"}
@@ -167,7 +167,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:D" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:D" "GPIO_OUT[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:D" "GPIO_OUT[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:D" "GPIO_OUT[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:D" "GPIO_OUT[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:D" "GPIO_OUT[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:D" "GPIO_OUT[30:30]"}
@@ -200,7 +200,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:E" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:E" "GPIO_OE[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:E" "GPIO_OE[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:E" "GPIO_OE[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:E" "GPIO_OE[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:E" "GPIO_OE[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:E" "GPIO_OE[30:30]"}
@@ -233,7 +233,7 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:Y" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:Y" "GPIO_IN[24:24]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:Y" "GPIO_IN[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:Y" "GPIO_IN[26:26]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:Y" "GPIO_IN[28:28]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:Y" "GPIO_IN[29:29]"}
#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:Y" "GPIO_IN[30:30]"}
@@ -266,7 +266,7 @@ sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_22} -new_po
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_port_name {GPIO_24_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_25_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_25} -new_port_name {GPIO_26_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_27} -new_port_name {GPIO_28_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_28} -new_port_name {GPIO_29_PAD}
#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_29} -new_port_name {GPIO_30_PAD}
diff --git a/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl b/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
index 34303b6..fb39d71 100644
--- a/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
+++ b/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
@@ -23,7 +23,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"FIXED_CONFIG_16:true" \
"FIXED_CONFIG_17:true" \
"FIXED_CONFIG_18:true" \
-"FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_19:false" \
"FIXED_CONFIG_20:false" \
"FIXED_CONFIG_21:false" \
"FIXED_CONFIG_22:false" \
@@ -69,7 +69,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" \
"IO_INT_TYPE_31:7" \
-"IO_NUM:24" \
+"IO_NUM:23" \
"IO_TYPE_0:2" \
"IO_TYPE_1:2" \
"IO_TYPE_2:2" \
diff --git a/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl b/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
index dd92f56..5b5bf54 100644
--- a/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
+++ b/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
@@ -24,7 +24,6 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_16_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_17_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_18_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_19_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
@@ -33,7 +32,6 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD
sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[23:23]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[22:22]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[21:21]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[20:20]"}
@@ -59,7 +57,6 @@ sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[23:23]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[22:22]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[21:21]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[20:20]"}
@@ -85,7 +82,6 @@ sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[23:23]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[22:22]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[21:21]"}
sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[20:20]"}
@@ -207,10 +203,6 @@ sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[22:2
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[22:22]" "LCD_GPIO_18_BIBUF:Y"}
sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[22:22]" "LCD_GPIO_18_BIBUF:E"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[23:23]" "LCD_GPIO_19_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[23:23]" "LCD_GPIO_19_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[23:23]" "LCD_GPIO_19_BIBUF:E"}
-
@@ -236,13 +228,12 @@ sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {P8_19}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {P9_14}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {P9_16}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {P9_42}
+sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {LCD_PCLK}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_19} -new_port_name {LCD_HSYNC}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_20} -new_port_name {LCD_AC_BIAS}
sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_21} -new_port_name {LCD_VSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_22} -new_port_name {LCD_PCLK}
sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {}
--
GitLab
From 099a479e4f93f7a4ad062e81a05d0574ff64b610 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sat, 22 Jul 2023 20:07:48 +0100
Subject: [PATCH 08/19] Cape: Assign GPIOs for cape pins.
- Optimize MSS GPIO_2 usage.
- GPIOS build option now uses GPIOs for all cape pins except I2C on
P9_PIN19 and P9_PIN20 which are hard-wired to MSS I2C.
- Move user LEDs control to MSS GPIO_2.
---
script_support/components/BVF_GATEWARE.tcl | 14 +-
.../components/BVF_RISCV_SUBSYSTEM.tcl | 24 +-
.../components/CAPE/DEFAULT/ADD_CAPE.tcl | 19 +-
.../components/CAPE/DEFAULT/CAPE.tcl | 119 +++---
.../CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl | 69 +--
.../components/CAPE/DEFAULT/CAPE_PWM.tcl | 5 +-
.../components/CAPE/DEFAULT/CoreGPIO_LCD.tcl | 138 ++++++
.../components/CAPE/DEFAULT/P8_GPIO_LCD.tcl | 383 +++++++----------
.../CAPE/DEFAULT/constraints/cape.pdc | 195 ++++-----
.../components/CAPE/GPIOS/ADD_CAPE.tcl | 9 +-
script_support/components/CAPE/GPIOS/CAPE.tcl | 149 ++++---
.../CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl | 24 --
.../components/CAPE/GPIOS/CoreGPIO_LCD.tcl | 16 +-
.../components/CAPE/GPIOS/CoreGPIO_P9.tcl | 138 ++++++
.../components/CAPE/GPIOS/P8_GPIO_LCD.tcl | 401 +++++++-----------
.../components/CAPE/GPIOS/P9_GPIO.tcl | 220 ++++++++++
.../CAPE/GPIOS/constraints/cape.pdc | 182 +++++---
.../components/CAPE/NONE/constraints/cape.pdc | 15 +-
script_support/components/FIC3_INITIATOR.tcl | 2 +-
script_support/constraints/base_design.pdc | 76 ----
20 files changed, 1246 insertions(+), 952 deletions(-)
create mode 100644 script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
create mode 100644 script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl
create mode 100644 script_support/components/CAPE/GPIOS/P9_GPIO.tcl
diff --git a/script_support/components/BVF_GATEWARE.tcl b/script_support/components/BVF_GATEWARE.tcl
index 82feeb4..8a1cb4f 100644
--- a/script_support/components/BVF_GATEWARE.tcl
+++ b/script_support/components/BVF_GATEWARE.tcl
@@ -1,5 +1,5 @@
-source script_support/components/BVF_RISCV_SUBSYSTEM/USER_LED_GPIO_PADS.tcl
+#source script_support/components/BVF_RISCV_SUBSYSTEM/USER_LED_GPIO_PADS.tcl
# Creating SmartDesign BVF_GATEWARE
set sd_name ${top_level_name}
@@ -204,12 +204,12 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "BVF_RISCV_SUBSYSTEM:DQS
#-------------------------------------------------------------------------------
# User LEDs
#-------------------------------------------------------------------------------
-auto_promote_pad_pins -promote_all 1
-sd_instantiate_component -sd_name ${sd_name} -component_name {USER_LED_PADS} -instance_name {USER_LED_PADS_0}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OUT" "USER_LED_PADS_0:USER_LED_GPIO_OUT"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OE" "USER_LED_PADS_0:USER_LED_GPIO_OE"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_IN" "USER_LED_PADS_0:USER_LED_GPIO_IN"}
-auto_promote_pad_pins -promote_all 0
+#auto_promote_pad_pins -promote_all 1
+#sd_instantiate_component -sd_name ${sd_name} -component_name {USER_LED_PADS} -instance_name {USER_LED_PADS_0}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OUT" "USER_LED_PADS_0:USER_LED_GPIO_OUT"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OE" "USER_LED_PADS_0:USER_LED_GPIO_OE"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_IN" "USER_LED_PADS_0:USER_LED_GPIO_IN"}
+#auto_promote_pad_pins -promote_all 0
#-------------------------------------------------------------------------------
# MIPI CSI-2 RX interface
diff --git a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
index 83be93c..ff7a2f4 100644
--- a/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
+++ b/script_support/components/BVF_RISCV_SUBSYSTEM.tcl
@@ -1,4 +1,4 @@
-source script_support/components/BVF_RISCV_SUBSYSTEM/USER_LED_GPIO.tcl
+#source script_support/components/BVF_RISCV_SUBSYSTEM/USER_LED_GPIO.tcl
# Creating SmartDesign BVF_RISCV_SUBSYSTEM
set sd_name {BVF_RISCV_SUBSYSTEM}
@@ -101,9 +101,9 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction
#-------------------------------------------------------------------------------
# User LEDs
#-------------------------------------------------------------------------------
-sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_OUT} -port_direction {OUT} -port_range {[11:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_OE} -port_direction {OUT} -port_range {[11:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_IN} -port_direction {IN} -port_range {[11:0]}
+#sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_OUT} -port_direction {OUT} -port_range {[11:0]}
+#sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_OE} -port_direction {OUT} -port_range {[11:0]}
+#sd_create_bus_port -sd_name ${sd_name} -port_name {USER_LED_GPIO_IN} -port_direction {IN} -port_range {[11:0]}
@@ -302,14 +302,14 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SOC_MSS:MMUART_4_RXD_F2M" "M
#-------------------------------------------------------------------------------
# User LEDs
#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {USER_LED_GPIO} -instance_name {}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC3_INITIATOR:APBmslave0" "USER_LED_GPIO_0:APB_bif"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:PRESETN" "PRESETN"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_3_PCLK" "USER_LED_GPIO_0:PCLK"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_OE" "USER_LED_GPIO_OE"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_OUT" "USER_LED_GPIO_OUT"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_IN" "USER_LED_GPIO_IN"}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {USER_LED_GPIO_0:INT}
+#sd_instantiate_component -sd_name ${sd_name} -component_name {USER_LED_GPIO} -instance_name {}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC3_INITIATOR:APBmslave0" "USER_LED_GPIO_0:APB_bif"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:PRESETN" "PRESETN"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC_3_PCLK" "USER_LED_GPIO_0:PCLK"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_OE" "USER_LED_GPIO_OE"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_OUT" "USER_LED_GPIO_OUT"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_LED_GPIO_0:GPIO_IN" "USER_LED_GPIO_IN"}
+#sd_mark_pins_unused -sd_name ${sd_name} -pin_names {USER_LED_GPIO_0:INT}
#-------------------------------------------------------------------------------
# High speed connector VIO_ENABLE.
diff --git a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
index b18bfbd..8105274 100644
--- a/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/ADD_CAPE.tcl
@@ -4,6 +4,7 @@ puts "======== Add cape option: DEFAULT ========"
# Build cape's submodules
#-------------------------------------------------------------------------------
source script_support/components/CAPE/DEFAULT/APB_BUS_CONVERTER.tcl
+source script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
source script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
source script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
source script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
@@ -17,13 +18,14 @@ set sd_name ${top_level_name}
#-------------------------------------------------------------------------------
# Cape pins
#-------------------------------------------------------------------------------
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_19} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN19} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_14} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_16} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_42} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {OUT}
#-------------------------------------------------------------------------------
# Instantiate.
@@ -46,11 +48,12 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M"
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_PIN13_USER_LED_10" "P8_PIN13_USER_LED_10"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_19" "P8_19"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_14" "P9_14"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_16" "P9_16"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_42" "P9_42"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_PIN19" "P8_PIN19"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN14" "P9_PIN14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN16" "P9_PIN16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN42" "P9_PIN42"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
diff --git a/script_support/components/CAPE/DEFAULT/CAPE.tcl b/script_support/components/CAPE/DEFAULT/CAPE.tcl
index af2d92e..72e2641 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE.tcl
@@ -35,68 +35,59 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OU
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P9_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P9_28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P9_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P9_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_28}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_28_PAD} -new_port_name {P8_5}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_29_PAD} -new_port_name {P8_6}
-#sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_30_PAD} -new_port_name {P8_7}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN3_USER_LED_0}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN4_USER_LED_1}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN5_USER_LED_2}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN6_USER_LED_3}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN7_USER_LED_4}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN8_USER_LED_5}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN9_USER_LED_6}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN10_USER_LED_7}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN11_USER_LED_8}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN12_USER_LED_9}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN14_USER_LED_11}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN15}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN16}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN17}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN18}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P8_PIN20}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P8_PIN21}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P8_PIN22}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P8_PIN23}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P8_PIN24}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P8_PIN25}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P8_PIN26}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P8_PIN27}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P8_PIN28}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P8_PIN29}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_PIN30}
#-------------------------------------------------------------------------------
-# LCD interface stub
+# P8
#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_LCD} -instance_name {CAPE_LCD_STUB}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PCLK} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA0} -new_port_name {P8_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA1} -new_port_name {P8_32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA2} -new_port_name {P8_33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA3} -new_port_name {P8_34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA4} -new_port_name {P8_35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA5} -new_port_name {P8_36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA6} -new_port_name {P8_37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA7} -new_port_name {P8_38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA8} -new_port_name {P8_39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA9} -new_port_name {P8_40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA10} -new_port_name {P8_41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA11} -new_port_name {P8_42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA12} -new_port_name {P8_43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA13} -new_port_name {P8_44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA14} -new_port_name {P8_45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_name {P8_46}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
+sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PRESETN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PCLK} -port_name {}
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN31}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN32}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN33}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN34}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN35}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN36}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN37}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN38}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN39}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN40}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN41}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN42}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN43}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN44}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN45}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN46}
+
#-------------------------------------------------------------------------------
@@ -108,11 +99,13 @@ sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_0} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_1} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_2} -port_name {}
sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_3} -port_name {}
+sd_connect_pin_to_port -sd_name {CAPE} -pin_name {PWM_0:PWM_4} -port_name {}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_0_0} -new_port_name {P9_42}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_1} -new_port_name {P9_14}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_2} -new_port_name {P9_16}
-sd_rename_port -sd_name {CAPE} -current_port_name {PWM_3} -new_port_name {P8_19}
+sd_rename_port -sd_name {CAPE} -current_port_name {PWM_0_0} -new_port_name {P9_PIN42}
+sd_rename_port -sd_name {CAPE} -current_port_name {PWM_1} -new_port_name {P9_PIN14}
+sd_rename_port -sd_name {CAPE} -current_port_name {PWM_2} -new_port_name {P9_PIN16}
+sd_rename_port -sd_name {CAPE} -current_port_name {PWM_3} -new_port_name {P8_PIN13_USER_LED_10}
+sd_rename_port -sd_name {CAPE} -current_port_name {PWM_4} -new_port_name {P8_PIN19}
#-------------------------------------------------------------------------------
@@ -122,7 +115,7 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_LCD_STUB:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {}
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"}
diff --git a/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl b/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
index 22e5fd9..d9bdbaf 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE_DEFAULT_GPIOS.tcl
@@ -14,13 +14,11 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPI
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_16_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_18_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
@@ -32,9 +30,6 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPI
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_25_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_26_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_28_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_29_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_30_BIBUF}
@@ -67,9 +62,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_sli
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[30:30]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
@@ -101,9 +93,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[30:30]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
@@ -135,9 +124,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:D" "GPIO_OUT[0:0]"}
@@ -150,13 +136,11 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:D" "GPIO
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:D" "GPIO_OUT[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:D" "GPIO_OUT[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:D" "GPIO_OUT[9:9]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:D" "GPIO_OUT[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:D" "GPIO_OUT[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:D" "GPIO_OUT[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:D" "GPIO_OUT[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:D" "GPIO_OUT[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:D" "GPIO_OUT[15:15]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:D" "GPIO_OUT[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:D" "GPIO_OUT[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:D" "GPIO_OUT[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:D" "GPIO_OUT[19:19]"}
@@ -168,9 +152,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:D" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:D" "GPIO_OUT[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:D" "GPIO_OUT[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:D" "GPIO_OUT[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:D" "GPIO_OUT[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:D" "GPIO_OUT[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:E" "GPIO_OE[0:0]"}
@@ -183,13 +164,11 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:E" "GPIO
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:E" "GPIO_OE[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:E" "GPIO_OE[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:E" "GPIO_OE[9:9]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:E" "GPIO_OE[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:E" "GPIO_OE[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:E" "GPIO_OE[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:E" "GPIO_OE[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:E" "GPIO_OE[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:E" "GPIO_OE[15:15]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:E" "GPIO_OE[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:E" "GPIO_OE[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:E" "GPIO_OE[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:E" "GPIO_OE[19:19]"}
@@ -201,9 +180,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:E" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:E" "GPIO_OE[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:E" "GPIO_OE[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:E" "GPIO_OE[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:E" "GPIO_OE[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:E" "GPIO_OE[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:Y" "GPIO_IN[0:0]"}
@@ -216,13 +192,11 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:Y" "GPIO
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:Y" "GPIO_IN[7:7]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:Y" "GPIO_IN[8:8]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:Y" "GPIO_IN[9:9]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_10_BIBUF:Y" "GPIO_IN[10:10]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:Y" "GPIO_IN[11:11]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:Y" "GPIO_IN[12:12]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:Y" "GPIO_IN[13:13]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:Y" "GPIO_IN[14:14]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:Y" "GPIO_IN[15:15]"}
-sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_16_BIBUF:Y" "GPIO_IN[16:16]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:Y" "GPIO_IN[17:17]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:Y" "GPIO_IN[18:18]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:Y" "GPIO_IN[19:19]"}
@@ -234,9 +208,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:Y" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:Y" "GPIO_IN[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:Y" "GPIO_IN[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:Y" "GPIO_IN[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:Y" "GPIO_IN[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:Y" "GPIO_IN[30:30]"}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
@@ -249,27 +220,25 @@ sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_5} -new_por
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_15} -new_port_name {GPIO_16_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_16} -new_port_name {GPIO_17_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_17} -new_port_name {GPIO_18_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_18} -new_port_name {GPIO_19_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_19} -new_port_name {GPIO_20_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_20} -new_port_name {GPIO_21_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_21} -new_port_name {GPIO_22_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_22} -new_port_name {GPIO_23_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_port_name {GPIO_24_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_25_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_25} -new_port_name {GPIO_26_PAD}
-sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_27} -new_port_name {GPIO_28_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_28} -new_port_name {GPIO_29_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_29} -new_port_name {GPIO_30_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_9} -new_port_name {GPIO_11_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_10} -new_port_name {GPIO_12_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_11} -new_port_name {GPIO_13_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_12} -new_port_name {GPIO_14_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_13} -new_port_name {GPIO_15_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_14} -new_port_name {GPIO_17_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_15} -new_port_name {GPIO_18_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_16} -new_port_name {GPIO_19_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_17} -new_port_name {GPIO_20_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_18} -new_port_name {GPIO_21_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_19} -new_port_name {GPIO_22_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_20} -new_port_name {GPIO_23_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_21} -new_port_name {GPIO_24_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_22} -new_port_name {GPIO_25_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_port_name {GPIO_26_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_27_PAD}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {GPIO_IN[10:10]} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {GPIO_IN[16:16]} -value {GND}
# Re-enable auto promotion of pins of type 'pad'
diff --git a/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl b/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
index aaffab1..69ddf92 100644
--- a/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
+++ b/script_support/components/CAPE/DEFAULT/CAPE_PWM.tcl
@@ -26,7 +26,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -compone
"FIXED_PWM_POS_EN6:true" "FIXED_PWM_POS_EN7:true" "FIXED_PWM_POS_EN8:true" "FIXED_PWM_POS_EN9:true" "FIXED_PWM_POS_EN10:true" \
"FIXED_PWM_POS_EN11:true" "FIXED_PWM_POS_EN12:true" "FIXED_PWM_POS_EN13:true" "FIXED_PWM_POS_EN14:true" "FIXED_PWM_POS_EN15:true" \
"FIXED_PWM_POS_EN16:true" \
-"PWM_NUM:4" \
+"PWM_NUM:5" \
"PWM_STRETCH_VALUE1:false" "PWM_STRETCH_VALUE2:false" "PWM_STRETCH_VALUE3:false" "PWM_STRETCH_VALUE4:false" "PWM_STRETCH_VALUE5:false" \
"PWM_STRETCH_VALUE6:false" "PWM_STRETCH_VALUE7:false" "PWM_STRETCH_VALUE8:false" "PWM_STRETCH_VALUE9:false" "PWM_STRETCH_VALUE10:false" \
"PWM_STRETCH_VALUE11:false" "PWM_STRETCH_VALUE12:false" "PWM_STRETCH_VALUE13:false" "PWM_STRETCH_VALUE14:false" "PWM_STRETCH_VALUE15:false" \
@@ -45,6 +45,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -compone
sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[4:4]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[3:3]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[2:2]"}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {"[1:1]"}
@@ -54,10 +55,12 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:APBslave} -po
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PRESETN} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PCLK} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[0:0]} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[4:4]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[3:3]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[2:2]} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM[1:1]} -port_name {}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_3} -new_port_name {PWM_4}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_2} -new_port_name {PWM_3}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_1} -new_port_name {PWM_2}
sd_rename_port -sd_name ${sd_name} -current_port_name {PWM_0} -new_port_name {PWM_1}
diff --git a/script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl b/script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
new file mode 100644
index 0000000..564801b
--- /dev/null
+++ b/script_support/components/CAPE/DEFAULT/CoreGPIO_LCD.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_P8_UPPER
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P8_UPPER} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:false" \
+"FIXED_CONFIG_17:false" \
+"FIXED_CONFIG_18:false" \
+"FIXED_CONFIG_19:false" \
+"FIXED_CONFIG_20:false" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:16" \
+"IO_TYPE_0:2" \
+"IO_TYPE_1:2" \
+"IO_TYPE_2:2" \
+"IO_TYPE_3:2" \
+"IO_TYPE_4:2" \
+"IO_TYPE_5:2" \
+"IO_TYPE_6:2" \
+"IO_TYPE_7:2" \
+"IO_TYPE_8:2" \
+"IO_TYPE_9:2" \
+"IO_TYPE_10:2" \
+"IO_TYPE_11:2" \
+"IO_TYPE_12:2" \
+"IO_TYPE_13:2" \
+"IO_TYPE_14:2" \
+"IO_TYPE_15:2" \
+"IO_TYPE_16:2" \
+"IO_TYPE_17:2" \
+"IO_TYPE_18:2" \
+"IO_TYPE_19:2" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL done
diff --git a/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl b/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
index 7461e9e..9b16ecc 100644
--- a/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
+++ b/script_support/components/CAPE/DEFAULT/P8_GPIO_LCD.tcl
@@ -1,233 +1,174 @@
-# Creating SmartDesign P8_GPIO_LCD
-set sd_name {P8_GPIO_LCD}
+# Creating SmartDesign P8_GPIO_UPPER
+set sd_name {P8_GPIO_UPPER}
create_smartdesign -sd_name ${sd_name}
auto_promote_pad_pins -promote_all 1
# Add GPIO BIBUFs
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_0_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_1_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_2_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_3_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_4_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_5_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_6_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_7_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_8_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_10_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_11_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_12_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_13_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_14_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_15_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_16_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_17_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_18_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
-
-
-
-
-
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_LCD} -params {\
-"APB_WIDTH:32" \
-"FIXED_CONFIG_0:true" "FIXED_CONFIG_1:true" "FIXED_CONFIG_2:true" "FIXED_CONFIG_3:true" "FIXED_CONFIG_4:true" \
-"FIXED_CONFIG_5:true" "FIXED_CONFIG_6:true" "FIXED_CONFIG_7:true" "FIXED_CONFIG_8:true" "FIXED_CONFIG_9:true" \
-"FIXED_CONFIG_10:true" "FIXED_CONFIG_11:true" "FIXED_CONFIG_12:true" "FIXED_CONFIG_13:true" "FIXED_CONFIG_14:true" \
-"FIXED_CONFIG_15:true" "FIXED_CONFIG_16:true" "FIXED_CONFIG_17:true" "FIXED_CONFIG_18:true" "FIXED_CONFIG_19:false" \
-"FIXED_CONFIG_20:false" "FIXED_CONFIG_21:false" "FIXED_CONFIG_22:false" "FIXED_CONFIG_23:false" "FIXED_CONFIG_24:false" \
-"FIXED_CONFIG_25:false" "FIXED_CONFIG_26:false" "FIXED_CONFIG_27:false" "FIXED_CONFIG_28:false" "FIXED_CONFIG_29:false" \
-"FIXED_CONFIG_30:false" "FIXED_CONFIG_31:false" \
-"INT_BUS:0" \
-"IO_INT_TYPE_0:7" "IO_INT_TYPE_1:7" "IO_INT_TYPE_2:7" "IO_INT_TYPE_3:7" "IO_INT_TYPE_4:7" \
-"IO_INT_TYPE_5:7" "IO_INT_TYPE_6:7" "IO_INT_TYPE_7:7" "IO_INT_TYPE_8:7" "IO_INT_TYPE_9:7" \
-"IO_INT_TYPE_10:7" "IO_INT_TYPE_11:7" "IO_INT_TYPE_12:7" "IO_INT_TYPE_13:7" "IO_INT_TYPE_14:7" \
-"IO_INT_TYPE_15:7" "IO_INT_TYPE_16:7" "IO_INT_TYPE_17:7" "IO_INT_TYPE_18:7" "IO_INT_TYPE_19:7" \
-"IO_INT_TYPE_20:7" "IO_INT_TYPE_21:7" "IO_INT_TYPE_22:7" "IO_INT_TYPE_23:7" "IO_INT_TYPE_24:7" \
-"IO_INT_TYPE_25:7" "IO_INT_TYPE_26:7" "IO_INT_TYPE_27:7" "IO_INT_TYPE_28:7" "IO_INT_TYPE_29:7" \
-"IO_INT_TYPE_30:7" "IO_INT_TYPE_31:7" \
-"IO_NUM:19" \
-"IO_TYPE_0:2" "IO_TYPE_1:2" "IO_TYPE_2:2" "IO_TYPE_3:2" "IO_TYPE_4:2" "IO_TYPE_5:2" "IO_TYPE_6:2" "IO_TYPE_7:2" "IO_TYPE_8:2" "IO_TYPE_9:2" \
-"IO_TYPE_10:2" "IO_TYPE_11:2" "IO_TYPE_12:2" "IO_TYPE_13:2" "IO_TYPE_14:2" "IO_TYPE_15:2" "IO_TYPE_16:2" "IO_TYPE_17:2" "IO_TYPE_18:2" "IO_TYPE_19:2" \
-"IO_TYPE_20:0" "IO_TYPE_21:0" "IO_TYPE_22:0" "IO_TYPE_23:0" "IO_TYPE_24:0" "IO_TYPE_25:0" "IO_TYPE_26:0" "IO_TYPE_27:0" "IO_TYPE_28:0" "IO_TYPE_29:0" \
-"IO_TYPE_30:0" "IO_TYPE_31:0" \
-"IO_VAL_0:0" "IO_VAL_1:0" "IO_VAL_2:0" "IO_VAL_3:0" "IO_VAL_4:0" "IO_VAL_5:0" "IO_VAL_6:0" "IO_VAL_7:0" "IO_VAL_8:0" "IO_VAL_9:0" \
-"IO_VAL_10:0" "IO_VAL_11:0" "IO_VAL_12:0" "IO_VAL_13:0" "IO_VAL_14:0" "IO_VAL_15:0" "IO_VAL_16:0" "IO_VAL_17:0" "IO_VAL_18:0" "IO_VAL_19:0" \
-"IO_VAL_20:0" "IO_VAL_21:0" "IO_VAL_22:0" "IO_VAL_23:0" "IO_VAL_24:0" "IO_VAL_25:0" "IO_VAL_26:0" "IO_VAL_27:0" "IO_VAL_28:0" "IO_VAL_29:0" \
-"IO_VAL_30:0" "IO_VAL_31:0" \
-"OE_TYPE:0"}
-
-sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[0:0]"}
-
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[0:0]" "LCD_GPIO_0_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[0:0]" "LCD_GPIO_0_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[0:0]" "LCD_GPIO_0_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[1:1]" "LCD_GPIO_1_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[1:1]" "LCD_GPIO_1_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[1:1]" "LCD_GPIO_1_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[2:2]" "LCD_GPIO_2_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[2:2]" "LCD_GPIO_2_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[2:2]" "LCD_GPIO_2_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[3:3]" "LCD_GPIO_3_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[3:3]" "LCD_GPIO_3_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[3:3]" "LCD_GPIO_3_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[4:4]" "LCD_GPIO_4_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[4:4]" "LCD_GPIO_4_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[4:4]" "LCD_GPIO_4_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[5:5]" "LCD_GPIO_5_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[5:5]" "LCD_GPIO_5_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[5:5]" "LCD_GPIO_5_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[6:6]" "LCD_GPIO_6_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[6:6]" "LCD_GPIO_6_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[6:6]" "LCD_GPIO_6_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[7:7]" "LCD_GPIO_7_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[7:7]" "LCD_GPIO_7_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[7:7]" "LCD_GPIO_7_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[8:8]" "LCD_GPIO_8_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[8:8]" "LCD_GPIO_8_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[8:8]" "LCD_GPIO_8_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[9:9]" "LCD_GPIO_9_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[9:9]" "LCD_GPIO_9_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[9:9]" "LCD_GPIO_9_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[10:10]" "LCD_GPIO_10_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[10:10]" "LCD_GPIO_10_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[10:10]" "LCD_GPIO_10_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[11:11]" "LCD_GPIO_11_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[11:11]" "LCD_GPIO_11_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[11:11]" "LCD_GPIO_11_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[12:12]" "LCD_GPIO_12_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[12:12]" "LCD_GPIO_12_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[12:12]" "LCD_GPIO_12_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[13:13]" "LCD_GPIO_13_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[13:13]" "LCD_GPIO_13_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[13:13]" "LCD_GPIO_13_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[14:14]" "LCD_GPIO_14_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[14:14]" "LCD_GPIO_14_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[14:14]" "LCD_GPIO_14_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[15:15]" "LCD_GPIO_15_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[15:15]" "LCD_GPIO_15_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[15:15]" "LCD_GPIO_15_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[16:16]" "LCD_HSYNC_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[16:16]" "LCD_HSYNC_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[16:16]" "LCD_HSYNC_GPIO_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[18:18]" "LCD_VSYNC_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[18:18]" "LCD_VSYNC_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[18:18]" "LCD_VSYNC_GPIO_BIBUF:E"}
-
-
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD} -new_port_name {LCD_DATA0}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_0} -new_port_name {LCD_DATA1}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_1} -new_port_name {LCD_DATA2}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_2} -new_port_name {LCD_DATA3}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_3} -new_port_name {LCD_DATA4}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_4} -new_port_name {LCD_DATA5}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_5} -new_port_name {LCD_DATA6}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_6} -new_port_name {LCD_DATA7}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_7} -new_port_name {LCD_DATA8}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_8} -new_port_name {LCD_DATA9}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_9} -new_port_name {LCD_DATA10}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_10} -new_port_name {LCD_DATA11}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_11} -new_port_name {LCD_DATA12}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_12} -new_port_name {LCD_DATA13}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_13} -new_port_name {LCD_DATA14}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name {LCD_DATA15}
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {LCD_HSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {LCD_AC_BIAS}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {LCD_VSYNC}
-
-
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:APB_bif} -port_name {}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[0:0]"}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
+
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PRESETN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PCLK} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:APB_bif} -port_name {}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:INT}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P8_GPIO_LCD
+# Generate SmartDesign P8_GPIO_UPPER
generate_component -component_name ${sd_name}
diff --git a/script_support/components/CAPE/DEFAULT/constraints/cape.pdc b/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
index 582d6b9..39b8ae4 100644
--- a/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
+++ b/script_support/components/CAPE/DEFAULT/constraints/cape.pdc
@@ -1,302 +1,275 @@
-#set_io -port_name P9_PWR_BUT \
-# -pin_name V16 \
-# -fixed true \
-# -DIRECTION INPUT
-
-set_io -port_name P9_12 \
- -pin_name C5 \
+set_io -port_name P9_11 \
+ -pin_name B5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_14 \
- -pin_name C6 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
-
-set_io -port_name P9_15 \
- -pin_name A5 \
+set_io -port_name P9_13 \
+ -pin_name D19 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_16 \
- -pin_name A6 \
+set_io -port_name P9_PIN14 \
+ -pin_name C6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_17 \
- -pin_name C9 \
+set_io -port_name P9_PIN16 \
+ -pin_name A6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_18 \
- -pin_name C10 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION OUT
-
-set_io -port_name P9_21 \
- -pin_name B8 \
+set_io -port_name P9_PIN42 \
+ -pin_name E14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_22 \
- -pin_name A8 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+#-------------------------------------------------------------------------------
-set_io -port_name P9_23 \
- -pin_name C12 \
- -fixed true \
- -io_std LVCMOS33 \
+set_io -port_name P8_PIN3_USER_LED_0 \
+ -pin_name V22 \
+ -fixed true \
-DIRECTION INOUT
-set_io -port_name P9_24 \
- -pin_name B12 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+set_io -port_name P8_PIN4_USER_LED_1 \
+ -pin_name W22 \
+ -fixed true \
+ -DIRECTION INOUT
-set_io -port_name P9_25 \
- -pin_name B7 \
- -fixed true \
- -io_std LVCMOS33 \
+set_io -port_name P8_PIN5_USER_LED_2 \
+ -pin_name V19 \
+ -fixed true \
-DIRECTION INOUT
-set_io -port_name P9_26 \
- -pin_name A7 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+set_io -port_name P8_PIN6_USER_LED_3 \
+ -pin_name V20 \
+ -fixed true \
+ -DIRECTION INOUT
-set_io -port_name P9_27 \
- -pin_name D11 \
- -fixed true \
- -io_std LVCMOS33 \
+set_io -port_name P8_PIN7_USER_LED_4 \
+ -pin_name V15 \
+ -fixed true \
-DIRECTION INOUT
-#--- re-assigned from NC
-set_io -port_name P9_28 \
- -pin_name C11 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+set_io -port_name P8_PIN8_USER_LED_5 \
+ -pin_name V14 \
+ -fixed true \
+ -DIRECTION INOUT
-set_io -port_name P9_29 \
- -pin_name F17 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+set_io -port_name P8_PIN9_USER_LED_6 \
+ -pin_name V21 \
+ -fixed true \
+ -DIRECTION INOUT
-set_io -port_name P9_30 \
- -pin_name F16 \
+set_io -port_name P8_PIN10_USER_LED_7 \
+ -pin_name W21 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN11_USER_LED_8 \
+ -pin_name Y21 \
-fixed true \
- -io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_31 \
- -pin_name E18 \
+set_io -port_name P8_PIN12_USER_LED_9 \
+ -pin_name Y20 \
-fixed true \
- -io_std LVCMOS33 \
- -DIRECTION OUT
+ -DIRECTION INOUT
-set_io -port_name P9_41 \
- -pin_name E15 \
+set_io -port_name P8_PIN13_USER_LED_10 \
+ -pin_name B10 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_42 \
- -pin_name E14 \
- -fixed true \
+set_io -port_name P8_PIN14_USER_LED_11 \
+ -pin_name B9 \
-io_std LVCMOS33 \
- -DIRECTION OUT
+ -fixed true \
+ -DIRECTION INOUT
-#-------------------------------------------------------------------------------
-set_io -port_name P8_15 \
+set_io -port_name P8_PIN15 \
-pin_name T12 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_16 \
+set_io -port_name P8_PIN16 \
-pin_name U12 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_17 \
+set_io -port_name P8_PIN17 \
-pin_name W13 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_18 \
+set_io -port_name P8_PIN18 \
-pin_name T16 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_19 \
+set_io -port_name P8_PIN19 \
-pin_name W18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_20 \
+set_io -port_name P8_PIN20 \
-pin_name R16 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_21 \
+set_io -port_name P8_PIN21 \
-pin_name AA21 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_22 \
+set_io -port_name P8_PIN22 \
-pin_name AA22 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_23 \
+set_io -port_name P8_PIN23 \
-pin_name AB18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_24 \
+set_io -port_name P8_PIN24 \
-pin_name AA18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_25 \
+set_io -port_name P8_PIN25 \
-pin_name V17 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_26 \
+set_io -port_name P8_PIN26 \
-pin_name A12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_27 \
+set_io -port_name P8_PIN27 \
-pin_name A13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_28 \
+set_io -port_name P8_PIN28 \
-pin_name B14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_29 \
+set_io -port_name P8_PIN29 \
-pin_name B13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_30 \
+set_io -port_name P8_PIN30 \
-pin_name D14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_31 \
+set_io -port_name P8_PIN31 \
-pin_name D13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_32 \
+set_io -port_name P8_PIN32 \
-pin_name B15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_33 \
+set_io -port_name P8_PIN33 \
-pin_name A15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_34 \
+set_io -port_name P8_PIN34 \
-pin_name C15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_35 \
+set_io -port_name P8_PIN35 \
-pin_name C14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_36 \
+set_io -port_name P8_PIN36 \
-pin_name B4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_37 \
+set_io -port_name P8_PIN37 \
-pin_name C4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_38 \
+set_io -port_name P8_PIN38 \
-pin_name C17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_39 \
+set_io -port_name P8_PIN39 \
-pin_name B17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_40 \
+set_io -port_name P8_PIN40 \
-pin_name B18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_41 \
+set_io -port_name P8_PIN41 \
-pin_name A18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_42 \
+set_io -port_name P8_PIN42 \
-pin_name D6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_43 \
+set_io -port_name P8_PIN43 \
-pin_name D7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_44 \
+set_io -port_name P8_PIN44 \
-pin_name D8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_45 \
+set_io -port_name P8_PIN45 \
-pin_name D9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_46 \
+set_io -port_name P8_PIN46 \
-pin_name D18 \
-fixed true \
-io_std LVCMOS33 \
diff --git a/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl b/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
index 5453ca4..331f13f 100644
--- a/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
+++ b/script_support/components/CAPE/GPIOS/ADD_CAPE.tcl
@@ -6,8 +6,10 @@ puts "======== Add cape option: GPIOS ========"
source script_support/components/CAPE/GPIOS/APB_BUS_CONVERTER.tcl
source script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
source script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
+source script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl
+source script_support/components/CAPE/GPIOS/P9_GPIO.tcl
source script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
-source script_support/components/CAPE/GPIOS/CAPE_PWM.tcl
+#source script_support/components/CAPE/GPIOS/CAPE_PWM.tcl
source script_support/components/CAPE/GPIOS/CAPE.tcl
#-------------------------------------------------------------------------------
@@ -47,3 +49,8 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+sd_delete_ports -sd_name ${sd_name} -port_names {P9_11}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_RXD} -value {GND}
+sd_delete_ports -sd_name ${sd_name} -port_names {P9_13}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_4_TXD}
+
diff --git a/script_support/components/CAPE/GPIOS/CAPE.tcl b/script_support/components/CAPE/GPIOS/CAPE.tcl
index 12d4de8..8e14242 100644
--- a/script_support/components/CAPE/GPIOS/CAPE.tcl
+++ b/script_support/components/CAPE/GPIOS/CAPE.tcl
@@ -6,7 +6,7 @@ create_smartdesign -sd_name ${sd_name}
# Create APB Bus
#-------------------------------------------------------------------------------
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
-"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:false" "APBSLOT3ENABLE:false" \
+"APBSLOT0ENABLE:false" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:true" "APBSLOT3ENABLE:false" \
"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
@@ -35,87 +35,96 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OU
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_OE} -port_name {}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_DEFAULT_GPIOS:GPIO_IN} -port_name {}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_16}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_20}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_12}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_15}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_17}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_18}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_21}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_22}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_23}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_24}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_25}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_26}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P9_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P9_28}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P9_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P9_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P9_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P9_41}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P9_42}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN3_USER_LED_0}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN4_USER_LED_1}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN5_USER_LED_2}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN6_USER_LED_3}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN7_USER_LED_4}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN8_USER_LED_5}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN9_USER_LED_6}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN10_USER_LED_7}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN11_USER_LED_8}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN12_USER_LED_9}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN13_USER_LED_10}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN14_USER_LED_11}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN15}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN16}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN17}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN18}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P8_PIN19}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P8_PIN20}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P8_PIN21}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P8_PIN22}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P8_PIN23}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_21_PAD} -new_port_name {P8_PIN24}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_22_PAD} -new_port_name {P8_PIN25}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_23_PAD} -new_port_name {P8_PIN26}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_24_PAD} -new_port_name {P8_PIN27}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_25_PAD} -new_port_name {P8_PIN28}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_26_PAD} -new_port_name {P8_PIN29}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_27_PAD} -new_port_name {P8_PIN30}
#-------------------------------------------------------------------------------
-# LCD interface stub
+# P8
#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_LCD} -instance_name {CAPE_LCD_STUB}
-
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CAPE_LCD_STUB:PCLK} -port_name {}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA0} -new_port_name {P8_31}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA1} -new_port_name {P8_32}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA2} -new_port_name {P8_33}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA3} -new_port_name {P8_34}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA4} -new_port_name {P8_35}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA5} -new_port_name {P8_36}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA6} -new_port_name {P8_37}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA7} -new_port_name {P8_38}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA8} -new_port_name {P8_39}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA9} -new_port_name {P8_40}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA10} -new_port_name {P8_41}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA11} -new_port_name {P8_42}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA12} -new_port_name {P8_43}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA13} -new_port_name {P8_44}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA14} -new_port_name {P8_45}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_DATA15} -new_port_name {P8_46}
-
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_HSYNC} -new_port_name {P8_29}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_AC_BIAS} -new_port_name {P8_30}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_VSYNC} -new_port_name {P8_27}
-sd_rename_port -sd_name ${sd_name} -current_port_name {LCD_PCLK} -new_port_name {P8_28}
-
+sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PRESETN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:PCLK} -port_name {}
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P8_PIN31}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P8_PIN32}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P8_PIN33}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P8_PIN34}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P8_PIN35}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P8_PIN36}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P8_PIN37}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P8_PIN38}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P8_PIN39}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P8_PIN40}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P8_PIN41}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P8_PIN42}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P8_PIN43}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P8_PIN44}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P8_PIN45}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P8_PIN46}
#-------------------------------------------------------------------------------
-# PWM
+# P9
#-------------------------------------------------------------------------------
-sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
-
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_0}
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_1}
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_2}
-sd_mark_pins_unused -sd_name {CAPE} -pin_names {PWM_0:PWM_3}
-
+sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_0_PAD} -new_port_name {P9_PIN11}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_1_PAD} -new_port_name {P9_PIN12}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_2_PAD} -new_port_name {P9_PIN13}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_3_PAD} -new_port_name {P9_PIN14}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_4_PAD} -new_port_name {P9_PIN15}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_5_PAD} -new_port_name {P9_PIN16}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_6_PAD} -new_port_name {P9_PIN17}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_7_PAD} -new_port_name {P9_PIN18}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_8_PAD} -new_port_name {P9_PIN21}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_9_PAD} -new_port_name {P9_PIN22}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_10_PAD} -new_port_name {P9_PIN23}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_11_PAD} -new_port_name {P9_PIN24}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_12_PAD} -new_port_name {P9_PIN25}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_13_PAD} -new_port_name {P9_PIN26}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_14_PAD} -new_port_name {P9_PIN27}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_15_PAD} -new_port_name {P9_PIN28}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_16_PAD} -new_port_name {P9_PIN29}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_17_PAD} -new_port_name {P9_PIN30}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_18_PAD} -new_port_name {P9_PIN31}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_19_PAD} -new_port_name {P9_PIN41}
+sd_rename_port -sd_name ${sd_name} -current_port_name {GPIO_20_PAD} -new_port_name {P9_PIN42}
#-------------------------------------------------------------------------------
# Connections
#-------------------------------------------------------------------------------
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "PWM_0:PRESETN"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "PWM_0:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "P9_GPIO_0:PRESETN"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "P9_GPIO_0:PCLK"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_LCD_STUB:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:APB_bif" "CoreAPB3_CAPE_0:APBmslave2"}
sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {APB_BUS_CONVERTER_0:APB_SLAVE} -port_name {}
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster"}
diff --git a/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl b/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
index 22e5fd9..1f508ba 100644
--- a/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
+++ b/script_support/components/CAPE/GPIOS/CAPE_DEFAULT_GPIOS.tcl
@@ -32,9 +32,6 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPI
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_25_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_26_BIBUF}
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_28_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_29_BIBUF}
-#sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_30_BIBUF}
@@ -67,9 +64,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_sli
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[30:30]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
@@ -101,9 +95,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[30:30]"}
sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
@@ -135,9 +126,6 @@ sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slic
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[25:25]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[26:26]"}
sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[28:28]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[29:29]"}
-#sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:D" "GPIO_OUT[0:0]"}
@@ -168,9 +156,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:D" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:D" "GPIO_OUT[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:D" "GPIO_OUT[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:D" "GPIO_OUT[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:D" "GPIO_OUT[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:D" "GPIO_OUT[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:E" "GPIO_OE[0:0]"}
@@ -201,9 +186,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:E" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:E" "GPIO_OE[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:E" "GPIO_OE[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:E" "GPIO_OE[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:E" "GPIO_OE[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:E" "GPIO_OE[30:30]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:Y" "GPIO_IN[0:0]"}
@@ -234,9 +216,6 @@ sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:Y" "GPI
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:Y" "GPIO_IN[25:25]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:Y" "GPIO_IN[26:26]"}
sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_28_BIBUF:Y" "GPIO_IN[28:28]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_29_BIBUF:Y" "GPIO_IN[29:29]"}
-#sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_30_BIBUF:Y" "GPIO_IN[30:30]"}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
@@ -267,9 +246,6 @@ sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_po
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_25_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_25} -new_port_name {GPIO_26_PAD}
sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_26} -new_port_name {GPIO_27_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_27} -new_port_name {GPIO_28_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_28} -new_port_name {GPIO_29_PAD}
-#sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_29} -new_port_name {GPIO_30_PAD}
# Re-enable auto promotion of pins of type 'pad'
diff --git a/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl b/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
index fb39d71..564801b 100644
--- a/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
+++ b/script_support/components/CAPE/GPIOS/CoreGPIO_LCD.tcl
@@ -1,8 +1,8 @@
-# Exporting Component Description of CoreGPIO_LCD to TCL
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL
# Family: PolarFireSoC
# Part Number: MPFS025T-FCVG484E
-# Create and Configure the core component CoreGPIO_LCD
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_LCD} -params {\
+# Create and Configure the core component CoreGPIO_P8_UPPER
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P8_UPPER} -params {\
"APB_WIDTH:32" \
"FIXED_CONFIG_0:true" \
"FIXED_CONFIG_1:true" \
@@ -20,9 +20,9 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"FIXED_CONFIG_13:true" \
"FIXED_CONFIG_14:true" \
"FIXED_CONFIG_15:true" \
-"FIXED_CONFIG_16:true" \
-"FIXED_CONFIG_17:true" \
-"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_16:false" \
+"FIXED_CONFIG_17:false" \
+"FIXED_CONFIG_18:false" \
"FIXED_CONFIG_19:false" \
"FIXED_CONFIG_20:false" \
"FIXED_CONFIG_21:false" \
@@ -69,7 +69,7 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" \
"IO_INT_TYPE_31:7" \
-"IO_NUM:23" \
+"IO_NUM:16" \
"IO_TYPE_0:2" \
"IO_TYPE_1:2" \
"IO_TYPE_2:2" \
@@ -135,4 +135,4 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_VAL_30:0" \
"IO_VAL_31:0" \
"OE_TYPE:0" }
-# Exporting Component Description of CoreGPIO_LCD to TCL done
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL done
diff --git a/script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl b/script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl
new file mode 100644
index 0000000..1516b5a
--- /dev/null
+++ b/script_support/components/CAPE/GPIOS/CoreGPIO_P9.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_P9 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_P9
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P9} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:true" \
+"FIXED_CONFIG_17:true" \
+"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_20:true" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:21" \
+"IO_TYPE_0:2" \
+"IO_TYPE_1:2" \
+"IO_TYPE_2:2" \
+"IO_TYPE_3:2" \
+"IO_TYPE_4:2" \
+"IO_TYPE_5:2" \
+"IO_TYPE_6:2" \
+"IO_TYPE_7:2" \
+"IO_TYPE_8:2" \
+"IO_TYPE_9:2" \
+"IO_TYPE_10:2" \
+"IO_TYPE_11:2" \
+"IO_TYPE_12:2" \
+"IO_TYPE_13:2" \
+"IO_TYPE_14:2" \
+"IO_TYPE_15:2" \
+"IO_TYPE_16:2" \
+"IO_TYPE_17:2" \
+"IO_TYPE_18:2" \
+"IO_TYPE_19:2" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of CoreGPIO_P9 to TCL done
diff --git a/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl b/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
index 5b5bf54..d14a5ae 100644
--- a/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
+++ b/script_support/components/CAPE/GPIOS/P8_GPIO_LCD.tcl
@@ -1,251 +1,174 @@
-# Creating SmartDesign P8_GPIO_LCD
-set sd_name {P8_GPIO_LCD}
+# Creating SmartDesign P8_GPIO_UPPER
+set sd_name {P8_GPIO_UPPER}
create_smartdesign -sd_name ${sd_name}
auto_promote_pad_pins -promote_all 1
# Add GPIO BIBUFs
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_0_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_1_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_2_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_3_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_4_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_5_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_6_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_7_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_8_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_9_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_10_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_11_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_12_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_13_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_14_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_15_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_16_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_17_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_GPIO_18_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_HSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_AC_BIAS_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_VSYNC_GPIO_BIBUF}
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {LCD_PCLK_GPIO_BIBUF}
-
-
-sd_instantiate_component -sd_name {P8_GPIO_LCD} -component_name {CoreGPIO_LCD} -instance_name {}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[22:22]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[21:21]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[20:20]"}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OE} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[22:22]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[21:21]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[20:20]"}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_OUT} -pin_slices {"[0:0]"}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[22:22]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[21:21]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[20:20]"}
-
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[19:19]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[18:18]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[17:17]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[16:16]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[15:15]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[14:14]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[13:13]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[12:12]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:GPIO_IN} -pin_slices {"[0:0]"}
-
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[0:0]" "LCD_GPIO_0_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[0:0]" "LCD_GPIO_0_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[0:0]" "LCD_GPIO_0_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[1:1]" "LCD_GPIO_1_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[1:1]" "LCD_GPIO_1_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[1:1]" "LCD_GPIO_1_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[2:2]" "LCD_GPIO_2_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[2:2]" "LCD_GPIO_2_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[2:2]" "LCD_GPIO_2_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[3:3]" "LCD_GPIO_3_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[3:3]" "LCD_GPIO_3_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[3:3]" "LCD_GPIO_3_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[4:4]" "LCD_GPIO_4_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[4:4]" "LCD_GPIO_4_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[4:4]" "LCD_GPIO_4_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[5:5]" "LCD_GPIO_5_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[5:5]" "LCD_GPIO_5_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[5:5]" "LCD_GPIO_5_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[6:6]" "LCD_GPIO_6_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[6:6]" "LCD_GPIO_6_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[6:6]" "LCD_GPIO_6_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[7:7]" "LCD_GPIO_7_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[7:7]" "LCD_GPIO_7_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[7:7]" "LCD_GPIO_7_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[8:8]" "LCD_GPIO_8_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[8:8]" "LCD_GPIO_8_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[8:8]" "LCD_GPIO_8_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[9:9]" "LCD_GPIO_9_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[9:9]" "LCD_GPIO_9_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[9:9]" "LCD_GPIO_9_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[10:10]" "LCD_GPIO_10_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[10:10]" "LCD_GPIO_10_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[10:10]" "LCD_GPIO_10_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[11:11]" "LCD_GPIO_11_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[11:11]" "LCD_GPIO_11_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[11:11]" "LCD_GPIO_11_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[12:12]" "LCD_GPIO_12_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[12:12]" "LCD_GPIO_12_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[12:12]" "LCD_GPIO_12_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[13:13]" "LCD_GPIO_13_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[13:13]" "LCD_GPIO_13_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[13:13]" "LCD_GPIO_13_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[14:14]" "LCD_GPIO_14_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[14:14]" "LCD_GPIO_14_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[14:14]" "LCD_GPIO_14_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[15:15]" "LCD_GPIO_15_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[15:15]" "LCD_GPIO_15_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[15:15]" "LCD_GPIO_15_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[16:16]" "LCD_HSYNC_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[16:16]" "LCD_HSYNC_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[16:16]" "LCD_HSYNC_GPIO_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[17:17]" "LCD_AC_BIAS_GPIO_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[18:18]" "LCD_VSYNC_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[18:18]" "LCD_VSYNC_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[18:18]" "LCD_VSYNC_GPIO_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[19:19]" "LCD_PCLK_GPIO_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[19:19]" "LCD_PCLK_GPIO_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[19:19]" "LCD_PCLK_GPIO_BIBUF:E"}
-
-
-
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[20:20]" "LCD_GPIO_16_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[20:20]" "LCD_GPIO_16_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[20:20]" "LCD_GPIO_16_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[21:21]" "LCD_GPIO_17_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[21:21]" "LCD_GPIO_17_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[21:21]" "LCD_GPIO_17_BIBUF:E"}
-
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OUT[22:22]" "LCD_GPIO_18_BIBUF:D"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_IN[22:22]" "LCD_GPIO_18_BIBUF:Y"}
-sd_connect_pins -sd_name {P8_GPIO_LCD} -pin_names {"CoreGPIO_LCD_0:GPIO_OE[22:22]" "LCD_GPIO_18_BIBUF:E"}
-
-
-
-
-
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD} -new_port_name {LCD_DATA0}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_0} -new_port_name {LCD_DATA1}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_1} -new_port_name {LCD_DATA2}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_2} -new_port_name {LCD_DATA3}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_3} -new_port_name {LCD_DATA4}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_4} -new_port_name {LCD_DATA5}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_5} -new_port_name {LCD_DATA6}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_6} -new_port_name {LCD_DATA7}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_7} -new_port_name {LCD_DATA8}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_8} -new_port_name {LCD_DATA9}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_9} -new_port_name {LCD_DATA10}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_10} -new_port_name {LCD_DATA11}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_11} -new_port_name {LCD_DATA12}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_12} -new_port_name {LCD_DATA13}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_13} -new_port_name {LCD_DATA14}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_14} -new_port_name {LCD_DATA15}
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_15} -new_port_name {P8_19}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_16} -new_port_name {P9_14}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_17} -new_port_name {P9_16}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_18} -new_port_name {LCD_PCLK}
-
-
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_19} -new_port_name {LCD_HSYNC}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_20} -new_port_name {LCD_AC_BIAS}
-sd_rename_port -sd_name {P8_GPIO_LCD} -current_port_name {PAD_21} -new_port_name {LCD_VSYNC}
-
-
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PRESETN} -port_name {}
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:PCLK} -port_name {}
-sd_connect_pin_to_port -sd_name {P8_GPIO_LCD} -pin_name {CoreGPIO_LCD_0:APB_bif} -port_name {}
-
-sd_mark_pins_unused -sd_name {P8_GPIO_LCD} -pin_names {CoreGPIO_LCD_0:INT}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {"[0:0]"}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
+
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PRESETN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:PCLK} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:APB_bif} -port_name {}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:INT}
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign P8_GPIO_LCD
+# Generate SmartDesign P8_GPIO_UPPER
generate_component -component_name ${sd_name}
diff --git a/script_support/components/CAPE/GPIOS/P9_GPIO.tcl b/script_support/components/CAPE/GPIOS/P9_GPIO.tcl
new file mode 100644
index 0000000..0230e58
--- /dev/null
+++ b/script_support/components/CAPE/GPIOS/P9_GPIO.tcl
@@ -0,0 +1,220 @@
+# Creating SmartDesign P9_GPIO
+set sd_name {P9_GPIO}
+create_smartdesign -sd_name ${sd_name}
+
+auto_promote_pad_pins -promote_all 1
+
+# Add GPIO BIBUFs
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_16_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_18_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_20_BIBUF}
+
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P9} -instance_name {}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {"[0:0]"}
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {"[0:0]"}
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[6:6]" "GPIO_6_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[6:6]" "GPIO_6_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[6:6]" "GPIO_6_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[7:7]" "GPIO_7_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[7:7]" "GPIO_7_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[7:7]" "GPIO_7_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[16:16]" "GPIO_16_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[16:16]" "GPIO_16_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[16:16]" "GPIO_16_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[17:17]" "GPIO_17_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[17:17]" "GPIO_17_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[17:17]" "GPIO_17_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[18:18]" "GPIO_18_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[18:18]" "GPIO_18_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[18:18]" "GPIO_18_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[19:19]" "GPIO_19_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[19:19]" "GPIO_19_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[19:19]" "GPIO_19_BIBUF:E"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[20:20]" "GPIO_20_BIBUF:D"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[20:20]" "GPIO_20_BIBUF:Y"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[20:20]" "GPIO_20_BIBUF:E"}
+
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_9} -new_port_name {GPIO_10_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_10} -new_port_name {GPIO_11_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_11} -new_port_name {GPIO_12_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_12} -new_port_name {GPIO_13_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_13} -new_port_name {GPIO_14_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_14} -new_port_name {GPIO_15_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_15} -new_port_name {GPIO_16_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_16} -new_port_name {GPIO_17_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_17} -new_port_name {GPIO_18_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_18} -new_port_name {GPIO_19_PAD}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PAD_19} -new_port_name {GPIO_20_PAD}
+
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:PRESETN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:PCLK} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:APB_bif} -port_name {}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:INT}
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign P9_GPIO
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/CAPE/GPIOS/constraints/cape.pdc b/script_support/components/CAPE/GPIOS/constraints/cape.pdc
index 582d6b9..5fa4c39 100644
--- a/script_support/components/CAPE/GPIOS/constraints/cape.pdc
+++ b/script_support/components/CAPE/GPIOS/constraints/cape.pdc
@@ -1,119 +1,125 @@
-#set_io -port_name P9_PWR_BUT \
-# -pin_name V16 \
-# -fixed true \
-# -DIRECTION INPUT
+set_io -port_name P9_PIN11 \
+ -pin_name B5 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
-set_io -port_name P9_12 \
+set_io -port_name P9_PIN12 \
-pin_name C5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_14 \
+set_io -port_name P9_PIN13 \
+ -pin_name D19 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P9_PIN14 \
-pin_name C6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_15 \
+set_io -port_name P9_PIN15 \
-pin_name A5 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_16 \
+set_io -port_name P9_PIN16 \
-pin_name A6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_17 \
+set_io -port_name P9_PIN17 \
-pin_name C9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_18 \
+set_io -port_name P9_PIN18 \
-pin_name C10 \
-io_std LVCMOS33 \
-fixed true \
-DIRECTION OUT
-set_io -port_name P9_21 \
+set_io -port_name P9_PIN21 \
-pin_name B8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_22 \
+set_io -port_name P9_PIN22 \
-pin_name A8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_23 \
+set_io -port_name P9_PIN23 \
-pin_name C12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_24 \
+set_io -port_name P9_PIN24 \
-pin_name B12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_25 \
+set_io -port_name P9_PIN25 \
-pin_name B7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_26 \
+set_io -port_name P9_PIN26 \
-pin_name A7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_27 \
+set_io -port_name P9_PIN27 \
-pin_name D11 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-#--- re-assigned from NC
-set_io -port_name P9_28 \
+set_io -port_name P9_PIN28 \
-pin_name C11 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_29 \
+set_io -port_name P9_PIN29 \
-pin_name F17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_30 \
+set_io -port_name P9_PIN30 \
-pin_name F16 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_31 \
+set_io -port_name P9_PIN31 \
-pin_name E18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION OUT
-set_io -port_name P9_41 \
+set_io -port_name P9_PIN41 \
-pin_name E15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P9_42 \
+set_io -port_name P9_PIN42 \
-pin_name E14 \
-fixed true \
-io_std LVCMOS33 \
@@ -121,182 +127,246 @@ set_io -port_name P9_42 \
#-------------------------------------------------------------------------------
-set_io -port_name P8_15 \
+set_io -port_name P8_PIN3_USER_LED_0 \
+ -pin_name V22 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN4_USER_LED_1 \
+ -pin_name W22 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN5_USER_LED_2 \
+ -pin_name V19 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN6_USER_LED_3 \
+ -pin_name V20 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN7_USER_LED_4 \
+ -pin_name V15 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN8_USER_LED_5 \
+ -pin_name V14 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN9_USER_LED_6 \
+ -pin_name V21 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN10_USER_LED_7 \
+ -pin_name W21 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN11_USER_LED_8 \
+ -pin_name Y21 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN12_USER_LED_9 \
+ -pin_name Y20 \
+ -fixed true \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN13_USER_LED_10 \
+ -pin_name B10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION INOUT
+
+set_io -port_name P8_PIN14_USER_LED_11 \
+ -pin_name B9 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION INOUT
+
+
+
+set_io -port_name P8_PIN15 \
-pin_name T12 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_16 \
+set_io -port_name P8_PIN16 \
-pin_name U12 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_17 \
+set_io -port_name P8_PIN17 \
-pin_name W13 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_18 \
+set_io -port_name P8_PIN18 \
-pin_name T16 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_19 \
+set_io -port_name P8_PIN19 \
-pin_name W18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_20 \
+set_io -port_name P8_PIN20 \
-pin_name R16 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_21 \
+set_io -port_name P8_PIN21 \
-pin_name AA21 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_22 \
+set_io -port_name P8_PIN22 \
-pin_name AA22 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_23 \
+set_io -port_name P8_PIN23 \
-pin_name AB18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_24 \
+set_io -port_name P8_PIN24 \
-pin_name AA18 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_25 \
+set_io -port_name P8_PIN25 \
-pin_name V17 \
-fixed true \
-DIRECTION INOUT
-set_io -port_name P8_26 \
+set_io -port_name P8_PIN26 \
-pin_name A12 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_27 \
+set_io -port_name P8_PIN27 \
-pin_name A13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_28 \
+set_io -port_name P8_PIN28 \
-pin_name B14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_29 \
+set_io -port_name P8_PIN29 \
-pin_name B13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_30 \
+set_io -port_name P8_PIN30 \
-pin_name D14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_31 \
+set_io -port_name P8_PIN31 \
-pin_name D13 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_32 \
+set_io -port_name P8_PIN32 \
-pin_name B15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_33 \
+set_io -port_name P8_PIN33 \
-pin_name A15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_34 \
+set_io -port_name P8_PIN34 \
-pin_name C15 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_35 \
+set_io -port_name P8_PIN35 \
-pin_name C14 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_36 \
+set_io -port_name P8_PIN36 \
-pin_name B4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_37 \
+set_io -port_name P8_PIN37 \
-pin_name C4 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_38 \
+set_io -port_name P8_PIN38 \
-pin_name C17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_39 \
+set_io -port_name P8_PIN39 \
-pin_name B17 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_40 \
+set_io -port_name P8_PIN40 \
-pin_name B18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_41 \
+set_io -port_name P8_PIN41 \
-pin_name A18 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_42 \
+set_io -port_name P8_PIN42 \
-pin_name D6 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_43 \
+set_io -port_name P8_PIN43 \
-pin_name D7 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_44 \
+set_io -port_name P8_PIN44 \
-pin_name D8 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_45 \
+set_io -port_name P8_PIN45 \
-pin_name D9 \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INOUT
-set_io -port_name P8_46 \
+set_io -port_name P8_PIN46 \
-pin_name D18 \
-fixed true \
-io_std LVCMOS33 \
diff --git a/script_support/components/CAPE/NONE/constraints/cape.pdc b/script_support/components/CAPE/NONE/constraints/cape.pdc
index 09d0fb5..3838d4d 100644
--- a/script_support/components/CAPE/NONE/constraints/cape.pdc
+++ b/script_support/components/CAPE/NONE/constraints/cape.pdc
@@ -1,4 +1,11 @@
-#
-# Intentionality empty constraints file.
-# Used when the cape interface is not used in the design.
-#
\ No newline at end of file
+set_io -port_name P9_11 \
+ -pin_name B5 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION INPUT
+
+set_io -port_name P9_13 \
+ -pin_name D19 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION OUTPUT
diff --git a/script_support/components/FIC3_INITIATOR.tcl b/script_support/components/FIC3_INITIATOR.tcl
index d176e83..5f740a0 100644
--- a/script_support/components/FIC3_INITIATOR.tcl
+++ b/script_support/components/FIC3_INITIATOR.tcl
@@ -4,7 +4,7 @@
# Create and Configure the core component FIC3_INITIATOR
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {FIC3_INITIATOR} -params {\
"APB_DWIDTH:32" \
-"APBSLOT0ENABLE:true" \
+"APBSLOT0ENABLE:false" \
"APBSLOT1ENABLE:true" \
"APBSLOT2ENABLE:true" \
"APBSLOT3ENABLE:false" \
diff --git a/script_support/constraints/base_design.pdc b/script_support/constraints/base_design.pdc
index 933f4cb..c9da7ce 100644
--- a/script_support/constraints/base_design.pdc
+++ b/script_support/constraints/base_design.pdc
@@ -42,18 +42,6 @@ set_io -port_name M2_W_DISABLE2 \
-fixed true \
-DIRECTION OUTPUT
-set_io -port_name P9_11 \
- -pin_name B5 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION INPUT
-
-set_io -port_name P9_13 \
- -pin_name D19 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION OUTPUT
-
set_io -port_name P9_19 \
-pin_name A10 \
-fixed true \
@@ -71,67 +59,3 @@ set_io -port_name SD_DET \
-fixed true \
-io_std LVCMOS33 \
-DIRECTION INPUT
-
-
-set_io -port_name P8_PIN3_USER_LED_0 \
- -pin_name V22 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN4_USER_LED_1 \
- -pin_name W22 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN5_USER_LED_2 \
- -pin_name V19 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN6_USER_LED_3 \
- -pin_name V20 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN7_USER_LED_4 \
- -pin_name V15 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN8_USER_LED_5 \
- -pin_name V14 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN9_USER_LED_6 \
- -pin_name V21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN10_USER_LED_7 \
- -pin_name W21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN11_USER_LED_8 \
- -pin_name Y21 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN12_USER_LED_9 \
- -pin_name Y20 \
- -fixed true \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN13_USER_LED_10 \
- -pin_name B10 \
- -fixed true \
- -io_std LVCMOS33 \
- -DIRECTION INOUT
-
-set_io -port_name P8_PIN14_USER_LED_11 \
- -pin_name B9 \
- -io_std LVCMOS33 \
- -fixed true \
- -DIRECTION INOUT
-
--
GitLab
From d5cf925ecfec587140d8456d27dab1c3db8df383 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 11:10:43 +0100
Subject: [PATCH 09/19] Board validation: Rework LED report of high-speed
connector loopbacks.
---
.../ADD_HIGH_SPEED_CONNECTOR.tcl | 66 ++++++++--------
.../constraints/HIGH_SPEED_CONNECTOR.pdc | 77 +++++++++++++++++--
2 files changed, 100 insertions(+), 43 deletions(-)
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
index 0ac86c2..663be42 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
@@ -13,7 +13,6 @@ create_hdl_core -file $project_dir/hdl/pattern_gen.v -module {PATTERN_GEN} -libr
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
-#source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_OSC_0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -28,7 +27,6 @@ source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STU
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_CCC_C1.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
-#source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_PWM_C0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
@@ -46,39 +44,35 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:XCVR_INIT_DON
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RCOSC_160MHZ_GL" "HIGH_SPEED_INTERFACE_0:RCOSC_160MHZ_GL"}
-sd_delete_nets -sd_name ${sd_name} -net_names {BVF_RISCV_SUBSYSTEM_USER_LED_GPIO_OUT}
-sd_delete_nets -sd_name ${sd_name} -net_names {BVF_RISCV_SUBSYSTEM_USER_LED_GPIO_OE}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OUT}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:USER_LED_GPIO_OE}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {USER_LED_PADS_0:USER_LED_GPIO_OE} -value {VCC}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[11:11]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[10:10]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[9:9]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[8:8]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[7:7]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[6:6]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[5:5]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[4:4]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[3:3]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[2:2]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[1:1]"}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {USER_LED_PADS_0:USER_LED_GPIO_OUT} -pin_slices {"[0:0]"}
-
-
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_RX_VALID" "USER_LED_PADS_0:USER_LED_GPIO_OUT[0:0]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[1:1]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_ERROR" "USER_LED_PADS_0:USER_LED_GPIO_OUT[2:2]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID" "USER_LED_PADS_0:USER_LED_GPIO_OUT[3:3]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[4:4]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_ERROR" "USER_LED_PADS_0:USER_LED_GPIO_OUT[5:5]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID" "USER_LED_PADS_0:USER_LED_GPIO_OUT[6:6]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[7:7]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "USER_LED_PADS_0:USER_LED_GPIO_OUT[8:8]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:TEST_MODE_0_LED" "USER_LED_PADS_0:USER_LED_GPIO_OUT[9:9]"}
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REFCLK_PLL_LOCK" "USER_LED_PADS_0:USER_LED_GPIO_OUT[11:11]"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REFCLK_CCC_OUT" "USER_LED_PADS_0:USER_LED_GPIO_OUT[10:10]"}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN3_USER_LED_0} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN4_USER_LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN5_USER_LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN6_USER_LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN7_USER_LED_4} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN8_USER_LED_5} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN9_USER_LED_6} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN10_USER_LED_7} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN11_USER_LED_8} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN12_USER_LED_9} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN14_USER_LED_11} -port_direction {OUT}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_RX_VALID" "P8_PIN3_USER_LED_0"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_LOCK" "P8_PIN4_USER_LED_1"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_ERROR" "P8_PIN5_USER_LED_2"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID" "P8_PIN6_USER_LED_3"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_LOCK" "P8_PIN7_USER_LED_4"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_ERROR" "P8_PIN8_USER_LED_5"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID" "P8_PIN9_USER_LED_6"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "P8_PIN10_USER_LED_7"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "P8_PIN11_USER_LED_8"}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN12_USER_LED_9} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN13_USER_LED_10} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN14_USER_LED_11} -value {GND}
+
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_3_LED}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_2_LED}
@@ -113,5 +107,5 @@ sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_
# Override software control of VIO.
sd_delete_nets -sd_name ${sd_name} -net_names {VIO_ENABLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:VIO_ENABLE}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VIO_ENABLE} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VIO_ENABLE} -value {GND}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
index dc6babf..a360be8 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
@@ -1,3 +1,66 @@
+set_io -port_name P8_PIN3_USER_LED_0 \
+ -pin_name V22 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN4_USER_LED_1 \
+ -pin_name W22 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN5_USER_LED_2 \
+ -pin_name V19 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN6_USER_LED_3 \
+ -pin_name V20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN7_USER_LED_4 \
+ -pin_name V15 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN8_USER_LED_5 \
+ -pin_name V14 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN9_USER_LED_6 \
+ -pin_name V21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN10_USER_LED_7 \
+ -pin_name W21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN11_USER_LED_8 \
+ -pin_name Y21 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN12_USER_LED_9 \
+ -pin_name Y20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN13_USER_LED_10 \
+ -pin_name B10 \
+ -fixed true \
+ -io_std LVCMOS33 \
+ -DIRECTION OUTPUT
+
+set_io -port_name P8_PIN14_USER_LED_11 \
+ -pin_name B9 \
+ -io_std LVCMOS33 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
set_io -port_name XCVR_TX1_N \
-pin_name H21 \
-DIRECTION OUTPUT
@@ -66,13 +129,13 @@ set_io -port_name XCVR_0B_REFCLK_N \
-DIRECTION INPUT
-set_io -port_name XCVR_0C_REFCLK_P \
- -pin_name J19 \
- -DIRECTION INPUT
-
-set_io -port_name XCVR_0C_REFCLK_N \
- -pin_name J20 \
- -DIRECTION INPUT
+#set_io -port_name XCVR_0C_REFCLK_P \
+# -pin_name J19 \
+# -DIRECTION INPUT
+#
+#set_io -port_name XCVR_0C_REFCLK_N \
+# -pin_name J20 \
+# -DIRECTION INPUT
--
GitLab
From 41aecc16ddbe58aa8f9011c7302f114d81297771 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 15:27:41 +0100
Subject: [PATCH 10/19] Board validation: Add SYZYGY clock inputs validation.
---
BUILD_BVF_GATEWARE.tcl | 2 ++
.../ADD_HIGH_SPEED_CONNECTOR.tcl | 6 ++--
.../HIGH_SPEED_INTERFACE.tcl | 30 +++++++++++-----
.../PF_TX_PLL_XCVR1.tcl | 35 +++++++++++++++++++
.../constraints/HIGH_SPEED_CONNECTOR.pdc | 14 ++++----
.../constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 8 +++++
6 files changed, 78 insertions(+), 17 deletions(-)
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index 2b438c4..7f41fd0 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -199,6 +199,7 @@ import_files \
-convert_EDN_to_HDL 0 \
-io_pdc "${constraint_path}/base_design.pdc" \
-fp_pdc "${constraint_path}/NW_PLL.pdc" \
+ -fp_pdc "./script_support/components/HIGH_SPEED_CONNECTOR/$high_speed_conn_option/constraints/fp/HIGH_SPEED_CONNECTOR.pdc" \
-sdc "${constraint_path}/fic_clocks.sdc" \
-io_pdc "./script_support/components/CAPE/$cape_option/constraints/cape.pdc" \
-io_pdc "./script_support/components/M2/$m2_option/constraints/M2.pdc" \
@@ -219,6 +220,7 @@ organize_tool_files \
-tool {PLACEROUTE} \
-file "${project_dir}/constraint/io/base_design.pdc" \
-file "${project_dir}/constraint/fp/NW_PLL.pdc" \
+ -file "${project_dir}/constraint/fp/HIGH_SPEED_CONNECTOR.pdc" \
-file "${project_dir}/constraint/fic_clocks.sdc" \
-file "${project_dir}/constraint/io/cape.pdc" \
-file "${project_dir}/constraint/io/M2.pdc" \
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
index 663be42..af8b955 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
@@ -26,6 +26,7 @@ source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STU
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_CCC_C1.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
@@ -69,8 +70,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX
sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "P8_PIN10_USER_LED_7"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "P8_PIN11_USER_LED_8"}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN12_USER_LED_9} -value {GND}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN13_USER_LED_10} -value {GND}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0B_REF_CLK_PLL_LOCK" "P8_PIN12_USER_LED_9"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REF_CLK_PLL_LOCK" "P8_PIN13_USER_LED_10"}
+
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN14_USER_LED_11} -value {GND}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
index 28d2db5..52f457b 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
@@ -57,8 +57,8 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_RX_VALID} -port_dire
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_ERROR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_LOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_RX_VALID} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_CCC_OUT} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REF_CLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REF_CLK_PLL_LOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_N} -port_direction {OUT} -port_is_pad {1}
@@ -91,6 +91,11 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2
+# Add AND2_1 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}
+
+
+
# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
@@ -170,6 +175,12 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:CLK_125}
+# Add PF_TX_PLL_XCVR1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_XCVR1} -instance_name {PF_TX_PLL_XCVR1_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_XCVR1_0:CLK_125}
+
+
+
# Add PF_XCVR_REF_CLK_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}
@@ -205,9 +216,12 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_3_
# Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" "XCVR_0B_REF_CLK_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_TX_PLL_0_0:PLL_LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_0:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_1:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_0:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "PF_TX_PLL_XCVR1_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "XCVR_LOOPBACK_1:XCVR_REF_CLK_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[1:1]" }
@@ -236,10 +250,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PCLK" "PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PRESETN" "PRESETN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_0:XCVR_REF_CLK" "XCVR_LOOPBACK_1:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_0:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:OUT0_FABCLK_0" "XCVR_0C_REFCLK_CCC_OUT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REFCLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:OUT0_FABCLK_0" "PF_TX_PLL_XCVR1_0:FAB_REF_CLK" "XCVR_LOOPBACK_1:XCVR_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "XCVR_LOOPBACK_0:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_1:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_2:RCOSC_160MHZ_GL" }
@@ -268,7 +281,8 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_P" "X
# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "HSIO_CoreGPIO_C0_0:APB_bif" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_0:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_1:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_2:CLKS_FROM_TXPLL_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_0:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_2:CLKS_FROM_TXPLL_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_XCVR1_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_1:CLKS_FROM_TXPLL_0" }
# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
new file mode 100644
index 0000000..25161ed
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_TX_PLL_XCVR1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_XCVR1} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
index a360be8..ee8c96c 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
@@ -129,13 +129,13 @@ set_io -port_name XCVR_0B_REFCLK_N \
-DIRECTION INPUT
-#set_io -port_name XCVR_0C_REFCLK_P \
-# -pin_name J19 \
-# -DIRECTION INPUT
-#
-#set_io -port_name XCVR_0C_REFCLK_N \
-# -pin_name J20 \
-# -DIRECTION INPUT
+set_io -port_name XCVR_0C_REFCLK_P \
+ -pin_name J19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0C_REFCLK_N \
+ -pin_name J20 \
+ -DIRECTION INPUT
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..06e341a
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1,8 @@
+
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_0/I_IO -fixed true -x 1014 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_0/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1009 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_TX_PLL_0_0/PF_TX_PLL_0_0/txpll_isnt_0 -fixed true -x 1009 -y 77
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_2/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_0_0/PF_XCVR_REF_CLK_0_0/I_IO -fixed true -x 1015 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_TX_PLL_XCVR1_0/PF_TX_PLL_XCVR1_0/txpll_isnt_0 -fixed true -x 1008 -y 77
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_1/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 47
--
GitLab
From 7d2bc3777cabaeb1931fdb228f1c30d729250c3c Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 16:08:09 +0100
Subject: [PATCH 11/19] Board validation: Route XCVR status signals to GPIO
inputs.
---
.../HIGH_SPEED_INTERFACE.tcl | 54 ++++++++++++-------
.../HSIO_CoreGPIO_C0.tcl | 42 +++++++--------
2 files changed, 55 insertions(+), 41 deletions(-)
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
index 52f457b..4bc372c 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
@@ -104,17 +104,23 @@ sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIB
# Add HSIO_CoreGPIO_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HSIO_CoreGPIO_C0} -instance_name {HSIO_CoreGPIO_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[0:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[10:10]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[11:11]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[12:12]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[13:13]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[13:13]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[14:14]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[14:14]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[19:19]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[1:1]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[1:1]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[2:2]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[3:3]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[6:6]}
@@ -134,6 +140,14 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[14:14]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[15:15]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[19:19]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:3]}
@@ -216,38 +230,38 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_3_
# Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_CCC_C0_0:PLL_LOCK_0" "XCVR_0B_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "HSIO_CoreGPIO_C0_0:GPIO_IN[17:17]" "PF_CCC_C0_0:PLL_LOCK_0" "XCVR_0B_REF_CLK_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_TX_PLL_0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_0:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "PF_TX_PLL_XCVR1_0:PLL_LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "HSIO_CoreGPIO_C0_0:GPIO_IN[18:18]" "PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REF_CLK_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "XCVR_LOOPBACK_1:XCVR_REF_CLK_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[0:0]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[4:4]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[1:1]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71P" "HSIO_CoreGPIO_C0_0:GPIO_IN[1:1]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73N_C2P_CLKN" "HSIO_CoreGPIO_C0_0:GPIO_OUT[2:2]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73P_C2P_CLKP" "HSIO_CoreGPIO_C0_0:GPIO_IN[2:2]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81N" "HSIO_CoreGPIO_C0_0:GPIO_IN[15:15]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71P" "HSIO_CoreGPIO_C0_0:GPIO_IN[5:5]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73N_C2P_CLKN" "HSIO_CoreGPIO_C0_0:GPIO_OUT[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73P_C2P_CLKP" "HSIO_CoreGPIO_C0_0:GPIO_IN[7:7]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81N" "HSIO_CoreGPIO_C0_0:GPIO_IN[19:19]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81P" "SYS_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82N" "BIBUF_0:PAD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82P" "MAC_1_MDC_M2F" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[3:3]" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83P" "HSIO_CoreGPIO_C0_0:GPIO_IN[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83P" "HSIO_CoreGPIO_C0_0:GPIO_IN[6:6]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "MAC_1_MDO_M2F" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "MAC_1_MDO_OE_M2F" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "MAC_1_MDI_F2M" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "XCVR_LOOPBACK_0:DEVICE_INIT_DONE" "XCVR_LOOPBACK_1:DEVICE_INIT_DONE" "XCVR_LOOPBACK_2:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "XCVR_LOOPBACK_0:EXT_RST_N" "XCVR_LOOPBACK_1:EXT_RST_N" "XCVR_LOOPBACK_2:EXT_RST_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[10:10]" "XCVR3_RX_VALID" "XCVR_LOOPBACK_0:rx_val_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[11:11]" "XCVR3_LOCK" "XCVR_LOOPBACK_0:lock_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[12:12]" "XCVR3_ERROR" "XCVR_LOOPBACK_0:error_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[4:4]" "XCVR1_RX_VALID" "XCVR_LOOPBACK_1:rx_val_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[5:5]" "XCVR1_LOCK" "XCVR_LOOPBACK_1:lock_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[6:6]" "XCVR1_ERROR" "XCVR_LOOPBACK_1:error_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[7:7]" "XCVR2_RX_VALID" "XCVR_LOOPBACK_2:rx_val_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]" "XCVR2_LOCK" "XCVR_LOOPBACK_2:lock_o" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[10:10]" "XCVR1_ERROR" "XCVR_LOOPBACK_1:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[11:11]" "XCVR2_RX_VALID" "XCVR_LOOPBACK_2:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[12:12]" "XCVR2_LOCK" "XCVR_LOOPBACK_2:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[13:13]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[14:14]" "XCVR3_RX_VALID" "XCVR_LOOPBACK_0:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[15:15]" "XCVR3_LOCK" "XCVR_LOOPBACK_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[16:16]" "XCVR3_ERROR" "XCVR_LOOPBACK_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]" "XCVR1_RX_VALID" "XCVR_LOOPBACK_1:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR1_LOCK" "XCVR_LOOPBACK_1:lock_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PCLK" "PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PRESETN" "PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_0:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" }
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
index c766113..8b5fec7 100644
--- a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
@@ -20,10 +20,10 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"FIXED_CONFIG_13:true" \
"FIXED_CONFIG_14:true" \
"FIXED_CONFIG_15:true" \
-"FIXED_CONFIG_16:false" \
-"FIXED_CONFIG_17:false" \
-"FIXED_CONFIG_18:false" \
-"FIXED_CONFIG_19:false" \
+"FIXED_CONFIG_16:true" \
+"FIXED_CONFIG_17:true" \
+"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_19:true" \
"FIXED_CONFIG_20:false" \
"FIXED_CONFIG_21:false" \
"FIXED_CONFIG_22:false" \
@@ -69,23 +69,23 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -compon
"IO_INT_TYPE_29:7" \
"IO_INT_TYPE_30:7" \
"IO_INT_TYPE_31:7" \
-"IO_NUM:16" \
-"IO_TYPE_0:2" \
-"IO_TYPE_1:2" \
-"IO_TYPE_2:2" \
-"IO_TYPE_3:2" \
-"IO_TYPE_4:2" \
-"IO_TYPE_5:2" \
-"IO_TYPE_6:2" \
-"IO_TYPE_7:2" \
-"IO_TYPE_8:2" \
-"IO_TYPE_9:2" \
-"IO_TYPE_10:2" \
-"IO_TYPE_11:2" \
-"IO_TYPE_12:2" \
-"IO_TYPE_13:2" \
-"IO_TYPE_14:2" \
-"IO_TYPE_15:2" \
+"IO_NUM:20" \
+"IO_TYPE_0:1" \
+"IO_TYPE_1:1" \
+"IO_TYPE_2:1" \
+"IO_TYPE_3:1" \
+"IO_TYPE_4:0" \
+"IO_TYPE_5:0" \
+"IO_TYPE_6:0" \
+"IO_TYPE_7:0" \
+"IO_TYPE_8:0" \
+"IO_TYPE_9:0" \
+"IO_TYPE_10:0" \
+"IO_TYPE_11:0" \
+"IO_TYPE_12:0" \
+"IO_TYPE_13:0" \
+"IO_TYPE_14:0" \
+"IO_TYPE_15:0" \
"IO_TYPE_16:0" \
"IO_TYPE_17:0" \
"IO_TYPE_18:0" \
--
GitLab
From 43fc1ffcfb6e3cd57897eb2219369ff2a3e88142 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 16:34:25 +0100
Subject: [PATCH 12/19] Board tests: Add SYGYGY connector tests build option.
---
.../ADD_HIGH_SPEED_CONNECTOR.tcl | 125 +++++++
.../HIGH_SPEED_INTERFACE.tcl | 306 ++++++++++++++++++
.../HSIO_CoreGPIO_C0.tcl | 138 ++++++++
.../BOARD_TESTS_SEEED_STUDIO/PF_CCC_C1.tcl | 249 ++++++++++++++
.../PF_TX_PLL_XCVR1.tcl | 35 ++
.../PF_XCVR_REF_CLK_C0.tcl | 12 +
.../XCVR_LOOPBACK/PF_CCC_01.tcl | 248 ++++++++++++++
.../XCVR_LOOPBACK/PF_CCC_C0.tcl | 249 ++++++++++++++
.../XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl | 9 +
.../XCVR_LOOPBACK/PF_OSC_0.tcl | 12 +
.../XCVR_LOOPBACK/PF_TX_PLL_0.tcl | 35 ++
.../XCVR_LOOPBACK/PF_XCVR_0.tcl | 55 ++++
.../XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl | 12 +
.../XCVR_LOOPBACK/Reset_Block.tcl | 66 ++++
.../XCVR_LOOPBACK/Reset_sync_rx.tcl | 6 +
.../XCVR_LOOPBACK/Reset_sync_tx.tcl | 6 +
.../XCVR_LOOPBACK/XCVR_LOOPBACK.tcl | 151 +++++++++
.../constraints/HIGH_SPEED_CONNECTOR.pdc | 148 +++++++++
.../constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 8 +
19 files changed, 1870 insertions(+)
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_CCC_C1.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_01.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_OSC_0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_Block.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_rx.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_tx.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
new file mode 100644
index 0000000..943f07d
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/ADD_HIGH_SPEED_CONNECTOR.tcl
@@ -0,0 +1,125 @@
+
+puts "======== Add High Speed Connector option: BOARD_VALIDATION_SEEED_STUDIO ========"
+
+# Import source files
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_chk.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/pattern_gen.v}
+import_files -hdl_source {script_support/HDL/XCVR_LOOPBACK/startup.v}
+
+build_design_hierarchy
+create_hdl_core -file $project_dir/hdl/startup.v -module {STARTUP} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_chk.v -module {PATTERN_CHK} -library {work} -package {}
+create_hdl_core -file $project_dir/hdl/pattern_gen.v -module {PATTERN_GEN} -library {work} -package {}
+
+
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_rx.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_tx.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/Reset_Block.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
+
+
+
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_CCC_C1.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
+source script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
+
+
+
+
+set sd_name ${top_level_name}
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {HIGH_SPEED_INTERFACE} -instance_name {HIGH_SPEED_INTERFACE_0}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_RESET_N_M2F" "HIGH_SPEED_INTERFACE_0:EXT_RST_N"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:DEVICE_INIT_DONE" "HIGH_SPEED_INTERFACE_0:DEVICE_INIT_DONE"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:XCVR_INIT_DONE" "HIGH_SPEED_INTERFACE_0:XCVR_INIT_DONE"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:RCOSC_160MHZ_GL" "HIGH_SPEED_INTERFACE_0:RCOSC_160MHZ_GL"}
+
+
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN3_USER_LED_0} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN4_USER_LED_1} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN5_USER_LED_2} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN6_USER_LED_3} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN7_USER_LED_4} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN8_USER_LED_5} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN9_USER_LED_6} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN10_USER_LED_7} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN11_USER_LED_8} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN12_USER_LED_9} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+#sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN14_USER_LED_11} -port_direction {OUT}
+#
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_RX_VALID" "P8_PIN3_USER_LED_0"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_LOCK" "P8_PIN4_USER_LED_1"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR1_ERROR" "P8_PIN5_USER_LED_2"}
+#
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID" "P8_PIN6_USER_LED_3"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_LOCK" "P8_PIN7_USER_LED_4"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR2_ERROR" "P8_PIN8_USER_LED_5"}
+#
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID" "P8_PIN9_USER_LED_6"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_LOCK" "P8_PIN10_USER_LED_7"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR3_ERROR" "P8_PIN11_USER_LED_8"}
+#
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0B_REF_CLK_PLL_LOCK" "P8_PIN12_USER_LED_9"}
+#sd_connect_pins -sd_name ${sd_name} -pin_names {"HIGH_SPEED_INTERFACE_0:XCVR_0C_REF_CLK_PLL_LOCK" "P8_PIN13_USER_LED_10"}
+#
+#sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {P8_PIN14_USER_LED_11} -value {GND}
+
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_3_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:TEST_MODE_1_LED}
+
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO82P} -port_name {}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDI_F2M" "HIGH_SPEED_INTERFACE_0:MAC_1_MDI_F2M"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDC_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDC_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_OE_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_OE_M2F"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MAC_1_MDO_M2F" "HIGH_SPEED_INTERFACE_0:MAC_1_MDO_M2F"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "HIGH_SPEED_INTERFACE_0:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:PRESETN"}
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:HSI_APB_MTARGET" "HIGH_SPEED_INTERFACE_0:APB_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_0_FABRIC_RESET_N" "HIGH_SPEED_INTERFACE_0:SYS_RESET_N"}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73P_C2P_CLKP} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO83P} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO70N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO71N} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO73N_C2P_CLKN} -port_name {}
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {HIGH_SPEED_INTERFACE_0:B0_HSIO81P} -port_name {}
+
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR_0C_REF_CLK_PLL_LOCK}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR1_ERROR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR1_LOCK}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR1_RX_VALID}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR2_ERROR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR2_LOCK}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR2_RX_VALID}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR3_ERROR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR3_LOCK}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR3_RX_VALID}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HIGH_SPEED_INTERFACE_0:XCVR_0B_REF_CLK_PLL_LOCK}
+
+# Override software control of VIO.
+sd_delete_nets -sd_name ${sd_name} -net_names {VIO_ENABLE}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:VIO_ENABLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {VIO_ENABLE} -value {GND}
+
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
new file mode 100644
index 0000000..4bc372c
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HIGH_SPEED_INTERFACE.tcl
@@ -0,0 +1,306 @@
+# Creating SmartDesign HIGH_SPEED_INTERFACE
+set sd_name {HIGH_SPEED_INTERFACE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73P_C2P_CLKP} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83P} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDC_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDO_OE_M2F} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_RESET_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REFCLK_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX1_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX1_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX2_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RX3_P} -port_direction {IN} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO70N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO71N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO73N_C2P_CLKN} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO81P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82P} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO83N} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MAC_1_MDI_F2M} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR1_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR2_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_ERROR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR3_RX_VALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0B_REF_CLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_0C_REF_CLK_PLL_LOCK} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX1_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX2_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_TX3_P} -port_direction {OUT} -port_is_pad {1}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {B0_HSIO82N} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_TARGET_PADDR" \
+"PSELx:APB_TARGET_PSEL" \
+"PENABLE:APB_TARGET_PENABLE" \
+"PWRITE:APB_TARGET_PWRITE" \
+"PRDATA:APB_TARGET_PRDATA" \
+"PWDATA:APB_TARGET_PWDATA" \
+"PREADY:APB_TARGET_PREADY" \
+"PSLVERR:APB_TARGET_PSLVERR" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add AND2_1 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}
+
+
+
+# Add BIBUF_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
+
+
+
+# Add HSIO_CoreGPIO_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {HSIO_CoreGPIO_C0} -instance_name {HSIO_CoreGPIO_C0_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[0:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[0:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[1:1]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[1:1]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[2:2]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_IN[3:3]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {HSIO_CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:GPIO_OUT[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HSIO_CoreGPIO_C0_0:INT}
+
+
+
+# Add PF_CCC_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0}
+
+
+
+# Add PF_CCC_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_CCC_C1_0:PLL_POWERDOWN_N_0} -value {VCC}
+
+
+
+# Add PF_CLK_DIV_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}
+
+
+
+# Add PF_TX_PLL_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_0} -instance_name {PF_TX_PLL_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:CLK_125}
+
+
+
+# Add PF_TX_PLL_XCVR1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_XCVR1} -instance_name {PF_TX_PLL_XCVR1_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_XCVR1_0:CLK_125}
+
+
+
+# Add PF_XCVR_REF_CLK_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}
+
+
+
+# Add PF_XCVR_REF_CLK_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_C0_0:REF_CLK}
+
+
+
+# Add XCVR_LOOPBACK_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_0}
+
+
+
+# Add XCVR_LOOPBACK_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_1}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_0_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_1_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_1:TEST_MODE_3_LED}
+
+
+
+# Add XCVR_LOOPBACK_2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_LOOPBACK} -instance_name {XCVR_LOOPBACK_2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_0_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_1_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_2_LED}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_LOOPBACK_2:TEST_MODE_3_LED}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "HSIO_CoreGPIO_C0_0:GPIO_IN[17:17]" "PF_CCC_C0_0:PLL_LOCK_0" "XCVR_0B_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_TX_PLL_0_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "XCVR_LOOPBACK_0:XCVR_REF_CLK_LOCK" "XCVR_LOOPBACK_2:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "PF_TX_PLL_XCVR1_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "HSIO_CoreGPIO_C0_0:GPIO_IN[18:18]" "PF_CCC_C1_0:PLL_LOCK_0" "XCVR_0C_REF_CLK_PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "XCVR_LOOPBACK_1:XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO70P" "HSIO_CoreGPIO_C0_0:GPIO_IN[4:4]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO71P" "HSIO_CoreGPIO_C0_0:GPIO_IN[5:5]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73N_C2P_CLKN" "HSIO_CoreGPIO_C0_0:GPIO_OUT[3:3]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO73P_C2P_CLKP" "HSIO_CoreGPIO_C0_0:GPIO_IN[7:7]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81N" "HSIO_CoreGPIO_C0_0:GPIO_IN[19:19]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO81P" "SYS_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82N" "BIBUF_0:PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO82P" "MAC_1_MDC_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83N" "HSIO_CoreGPIO_C0_0:GPIO_OUT[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"B0_HSIO83P" "HSIO_CoreGPIO_C0_0:GPIO_IN[6:6]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "MAC_1_MDO_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "MAC_1_MDO_OE_M2F" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "MAC_1_MDI_F2M" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "XCVR_LOOPBACK_0:DEVICE_INIT_DONE" "XCVR_LOOPBACK_1:DEVICE_INIT_DONE" "XCVR_LOOPBACK_2:DEVICE_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "XCVR_LOOPBACK_0:EXT_RST_N" "XCVR_LOOPBACK_1:EXT_RST_N" "XCVR_LOOPBACK_2:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[10:10]" "XCVR1_ERROR" "XCVR_LOOPBACK_1:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[11:11]" "XCVR2_RX_VALID" "XCVR_LOOPBACK_2:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[12:12]" "XCVR2_LOCK" "XCVR_LOOPBACK_2:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[13:13]" "XCVR2_ERROR" "XCVR_LOOPBACK_2:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[14:14]" "XCVR3_RX_VALID" "XCVR_LOOPBACK_0:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[15:15]" "XCVR3_LOCK" "XCVR_LOOPBACK_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[16:16]" "XCVR3_ERROR" "XCVR_LOOPBACK_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[8:8]" "XCVR1_RX_VALID" "XCVR_LOOPBACK_1:rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:GPIO_IN[9:9]" "XCVR1_LOCK" "XCVR_LOOPBACK_1:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"HSIO_CoreGPIO_C0_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_TX_PLL_0_0:FAB_REF_CLK" "XCVR_LOOPBACK_0:XCVR_REF_CLK" "XCVR_LOOPBACK_2:XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:OUT0_FABCLK_0" "PF_TX_PLL_XCVR1_0:FAB_REF_CLK" "XCVR_LOOPBACK_1:XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:FAB_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "XCVR_LOOPBACK_0:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_1:RCOSC_160MHZ_GL" "XCVR_LOOPBACK_2:RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_N" "XCVR_0B_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_P" "XCVR_0B_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "XCVR_0C_REFCLK_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "XCVR_0C_REFCLK_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "XCVR_LOOPBACK_0:TEST_MODE_0_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "XCVR_LOOPBACK_0:TEST_MODE_1_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "XCVR_LOOPBACK_0:TEST_MODE_2_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_3_LED" "XCVR_LOOPBACK_0:TEST_MODE_3_LED" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_INIT_DONE" "XCVR_LOOPBACK_0:XCVR_INIT_DONE" "XCVR_LOOPBACK_1:XCVR_INIT_DONE" "XCVR_LOOPBACK_2:XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_RXD_N" "XCVR_RX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_RXD_P" "XCVR_RX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_TXD_N" "XCVR_TX3_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_0:LANE0_TXD_P" "XCVR_TX3_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_RXD_N" "XCVR_RX1_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_RXD_P" "XCVR_RX1_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_TXD_N" "XCVR_TX1_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_1:LANE0_TXD_P" "XCVR_TX1_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_N" "XCVR_RX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_RXD_P" "XCVR_RX2_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_N" "XCVR_TX2_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_LOOPBACK_2:LANE0_TXD_P" "XCVR_TX2_P" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "HSIO_CoreGPIO_C0_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_0:CLKS_FROM_TXPLL_0" "XCVR_LOOPBACK_2:CLKS_FROM_TXPLL_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_XCVR1_0:CLKS_TO_XCVR" "XCVR_LOOPBACK_1:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign HIGH_SPEED_INTERFACE
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
new file mode 100644
index 0000000..8b5fec7
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/HSIO_CoreGPIO_C0.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component HSIO_CoreGPIO_C0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {HSIO_CoreGPIO_C0} -params {\
+"APB_WIDTH:32" \
+"FIXED_CONFIG_0:true" \
+"FIXED_CONFIG_1:true" \
+"FIXED_CONFIG_2:true" \
+"FIXED_CONFIG_3:true" \
+"FIXED_CONFIG_4:true" \
+"FIXED_CONFIG_5:true" \
+"FIXED_CONFIG_6:true" \
+"FIXED_CONFIG_7:true" \
+"FIXED_CONFIG_8:true" \
+"FIXED_CONFIG_9:true" \
+"FIXED_CONFIG_10:true" \
+"FIXED_CONFIG_11:true" \
+"FIXED_CONFIG_12:true" \
+"FIXED_CONFIG_13:true" \
+"FIXED_CONFIG_14:true" \
+"FIXED_CONFIG_15:true" \
+"FIXED_CONFIG_16:true" \
+"FIXED_CONFIG_17:true" \
+"FIXED_CONFIG_18:true" \
+"FIXED_CONFIG_19:true" \
+"FIXED_CONFIG_20:false" \
+"FIXED_CONFIG_21:false" \
+"FIXED_CONFIG_22:false" \
+"FIXED_CONFIG_23:false" \
+"FIXED_CONFIG_24:false" \
+"FIXED_CONFIG_25:false" \
+"FIXED_CONFIG_26:false" \
+"FIXED_CONFIG_27:false" \
+"FIXED_CONFIG_28:false" \
+"FIXED_CONFIG_29:false" \
+"FIXED_CONFIG_30:false" \
+"FIXED_CONFIG_31:false" \
+"INT_BUS:0" \
+"IO_INT_TYPE_0:7" \
+"IO_INT_TYPE_1:7" \
+"IO_INT_TYPE_2:7" \
+"IO_INT_TYPE_3:7" \
+"IO_INT_TYPE_4:7" \
+"IO_INT_TYPE_5:7" \
+"IO_INT_TYPE_6:7" \
+"IO_INT_TYPE_7:7" \
+"IO_INT_TYPE_8:7" \
+"IO_INT_TYPE_9:7" \
+"IO_INT_TYPE_10:7" \
+"IO_INT_TYPE_11:7" \
+"IO_INT_TYPE_12:7" \
+"IO_INT_TYPE_13:7" \
+"IO_INT_TYPE_14:7" \
+"IO_INT_TYPE_15:7" \
+"IO_INT_TYPE_16:7" \
+"IO_INT_TYPE_17:7" \
+"IO_INT_TYPE_18:7" \
+"IO_INT_TYPE_19:7" \
+"IO_INT_TYPE_20:7" \
+"IO_INT_TYPE_21:7" \
+"IO_INT_TYPE_22:7" \
+"IO_INT_TYPE_23:7" \
+"IO_INT_TYPE_24:7" \
+"IO_INT_TYPE_25:7" \
+"IO_INT_TYPE_26:7" \
+"IO_INT_TYPE_27:7" \
+"IO_INT_TYPE_28:7" \
+"IO_INT_TYPE_29:7" \
+"IO_INT_TYPE_30:7" \
+"IO_INT_TYPE_31:7" \
+"IO_NUM:20" \
+"IO_TYPE_0:1" \
+"IO_TYPE_1:1" \
+"IO_TYPE_2:1" \
+"IO_TYPE_3:1" \
+"IO_TYPE_4:0" \
+"IO_TYPE_5:0" \
+"IO_TYPE_6:0" \
+"IO_TYPE_7:0" \
+"IO_TYPE_8:0" \
+"IO_TYPE_9:0" \
+"IO_TYPE_10:0" \
+"IO_TYPE_11:0" \
+"IO_TYPE_12:0" \
+"IO_TYPE_13:0" \
+"IO_TYPE_14:0" \
+"IO_TYPE_15:0" \
+"IO_TYPE_16:0" \
+"IO_TYPE_17:0" \
+"IO_TYPE_18:0" \
+"IO_TYPE_19:0" \
+"IO_TYPE_20:0" \
+"IO_TYPE_21:0" \
+"IO_TYPE_22:0" \
+"IO_TYPE_23:0" \
+"IO_TYPE_24:0" \
+"IO_TYPE_25:0" \
+"IO_TYPE_26:0" \
+"IO_TYPE_27:0" \
+"IO_TYPE_28:0" \
+"IO_TYPE_29:0" \
+"IO_TYPE_30:0" \
+"IO_TYPE_31:0" \
+"IO_VAL_0:0" \
+"IO_VAL_1:0" \
+"IO_VAL_2:0" \
+"IO_VAL_3:0" \
+"IO_VAL_4:0" \
+"IO_VAL_5:0" \
+"IO_VAL_6:0" \
+"IO_VAL_7:0" \
+"IO_VAL_8:0" \
+"IO_VAL_9:0" \
+"IO_VAL_10:0" \
+"IO_VAL_11:0" \
+"IO_VAL_12:0" \
+"IO_VAL_13:0" \
+"IO_VAL_14:0" \
+"IO_VAL_15:0" \
+"IO_VAL_16:0" \
+"IO_VAL_17:0" \
+"IO_VAL_18:0" \
+"IO_VAL_19:0" \
+"IO_VAL_20:0" \
+"IO_VAL_21:0" \
+"IO_VAL_22:0" \
+"IO_VAL_23:0" \
+"IO_VAL_24:0" \
+"IO_VAL_25:0" \
+"IO_VAL_26:0" \
+"IO_VAL_27:0" \
+"IO_VAL_28:0" \
+"IO_VAL_29:0" \
+"IO_VAL_30:0" \
+"IO_VAL_31:0" \
+"OE_TYPE:0" }
+# Exporting Component Description of HSIO_CoreGPIO_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_CCC_C1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_CCC_C1.tcl
new file mode 100644
index 0000000..2e1d947
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_CCC_C1.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_CCC_C1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:*} -component_name {PF_CCC_C1} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:12" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:true" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:125" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C1 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
new file mode 100644
index 0000000..25161ed
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_TX_PLL_XCVR1.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_TX_PLL_XCVR1
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:2.0.300} -component_name {PF_TX_PLL_XCVR1} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_XCVR1 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
new file mode 100644
index 0000000..55f816c
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/PF_XCVR_REF_CLK_C0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_XCVR_REF_CLK_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -component_name {PF_XCVR_REF_CLK_C0} -params {\
+"ENABLE_FAB_CLK_0:true" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_01.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_01.tcl
new file mode 100644
index 0000000..c6ba95c
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_01.tcl
@@ -0,0 +1,248 @@
+# Exporting Component Description of PF_CCC_01 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CCC_01
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CCC:* -component_name {PF_CCC_01} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:1" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:10" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:125" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:0" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:160" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:0" \
+"PLL_LOCK_COUNT_1:0" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:4" \
+"PLL_REFDIV_1:1" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_01 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl
new file mode 100644
index 0000000..3abd00e
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CCC_C0.tcl
@@ -0,0 +1,249 @@
+# Exporting Component Description of PF_CCC_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_CCC_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:*} -component_name {PF_CCC_C0} -params {\
+"DLL_CLK_0_BANKCLK_EN:false" \
+"DLL_CLK_0_DEDICATED_EN:false" \
+"DLL_CLK_0_FABCLK_EN:false" \
+"DLL_CLK_1_BANKCLK_EN:false" \
+"DLL_CLK_1_DEDICATED_EN:false" \
+"DLL_CLK_1_FABCLK_EN:false" \
+"DLL_CLK_P_EN:false" \
+"DLL_CLK_P_OPTIONS_EN:false" \
+"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_REF_OPTIONS_EN:false" \
+"DLL_CLK_S_EN:false" \
+"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
+"DLL_CLK_S_OPTIONS_EN:false" \
+"DLL_DELAY4:0" \
+"DLL_DYNAMIC_CODE_EN:false" \
+"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"DLL_EXPORT_PWRDWN:false" \
+"DLL_FB_CLK:Primary" \
+"DLL_FB_EN:false" \
+"DLL_FINE_PHASE_CODE:0" \
+"DLL_IN:133" \
+"DLL_JITTER:0" \
+"DLL_MODE:PHASE_REF_MODE" \
+"DLL_ONLY_EN:false" \
+"DLL_OUT_0:1" \
+"DLL_OUT_1:1" \
+"DLL_PRIM_PHASE:90" \
+"DLL_PRIM_PHASE_CODE:0" \
+"DLL_SEC_PHASE:90" \
+"DLL_SEC_PHASE_CODE:0" \
+"DLL_SELECTED_IN:Output2" \
+"FF_REQUIRES_LOCK_EN_0:0" \
+"GL0_0_BANKCLK_USED:false" \
+"GL0_0_BYPASS:0" \
+"GL0_0_BYPASS_EN:false" \
+"GL0_0_DEDICATED_USED:false" \
+"GL0_0_DIV:8" \
+"GL0_0_DIVSTART:0" \
+"GL0_0_DYNAMIC_PH:false" \
+"GL0_0_EXPOSE_EN:false" \
+"GL0_0_FABCLK_GATED_USED:false" \
+"GL0_0_FABCLK_USED:true" \
+"GL0_0_FREQ_SEL:false" \
+"GL0_0_IS_USED:true" \
+"GL0_0_OUT_FREQ:156.25" \
+"GL0_0_PHASE_INDEX:0" \
+"GL0_0_PHASE_SEL:false" \
+"GL0_0_PLL_PHASE:0" \
+"GL0_1_BANKCLK_USED:false" \
+"GL0_1_BYPASS:0" \
+"GL0_1_BYPASS_EN:false" \
+"GL0_1_DEDICATED_USED:false" \
+"GL0_1_DIV:1" \
+"GL0_1_DIVSTART:0" \
+"GL0_1_DYNAMIC_PH:false" \
+"GL0_1_EXPOSE_EN:false" \
+"GL0_1_FABCLK_USED:false" \
+"GL0_1_FREQ_SEL:false" \
+"GL0_1_IS_USED:true" \
+"GL0_1_OUT_FREQ:100" \
+"GL0_1_PHASE_INDEX:0" \
+"GL0_1_PHASE_SEL:false" \
+"GL0_1_PLL_PHASE:0" \
+"GL1_0_BANKCLK_USED:false" \
+"GL1_0_BYPASS:0" \
+"GL1_0_BYPASS_EN:false" \
+"GL1_0_DEDICATED_USED:false" \
+"GL1_0_DIV:1" \
+"GL1_0_DIVSTART:0" \
+"GL1_0_DYNAMIC_PH:false" \
+"GL1_0_EXPOSE_EN:false" \
+"GL1_0_FABCLK_GATED_USED:false" \
+"GL1_0_FABCLK_USED:true" \
+"GL1_0_FREQ_SEL:false" \
+"GL1_0_IS_USED:false" \
+"GL1_0_OUT_FREQ:100" \
+"GL1_0_PHASE_INDEX:0" \
+"GL1_0_PHASE_SEL:false" \
+"GL1_0_PLL_PHASE:0" \
+"GL1_1_BANKCLK_USED:false" \
+"GL1_1_BYPASS:0" \
+"GL1_1_BYPASS_EN:false" \
+"GL1_1_DEDICATED_USED:false" \
+"GL1_1_DIV:1" \
+"GL1_1_DIVSTART:0" \
+"GL1_1_DYNAMIC_PH:false" \
+"GL1_1_EXPOSE_EN:false" \
+"GL1_1_FABCLK_USED:false" \
+"GL1_1_FREQ_SEL:false" \
+"GL1_1_IS_USED:false" \
+"GL1_1_OUT_FREQ:0" \
+"GL1_1_PHASE_INDEX:0" \
+"GL1_1_PHASE_SEL:false" \
+"GL1_1_PLL_PHASE:0" \
+"GL2_0_BANKCLK_USED:false" \
+"GL2_0_BYPASS:0" \
+"GL2_0_BYPASS_EN:false" \
+"GL2_0_DEDICATED_USED:false" \
+"GL2_0_DIV:1" \
+"GL2_0_DIVSTART:0" \
+"GL2_0_DYNAMIC_PH:false" \
+"GL2_0_EXPOSE_EN:false" \
+"GL2_0_FABCLK_GATED_USED:false" \
+"GL2_0_FABCLK_USED:true" \
+"GL2_0_FREQ_SEL:false" \
+"GL2_0_IS_USED:false" \
+"GL2_0_OUT_FREQ:100" \
+"GL2_0_PHASE_INDEX:0" \
+"GL2_0_PHASE_SEL:false" \
+"GL2_0_PLL_PHASE:0" \
+"GL2_1_BANKCLK_USED:false" \
+"GL2_1_BYPASS:0" \
+"GL2_1_BYPASS_EN:false" \
+"GL2_1_DEDICATED_USED:false" \
+"GL2_1_DIV:1" \
+"GL2_1_DIVSTART:0" \
+"GL2_1_DYNAMIC_PH:false" \
+"GL2_1_EXPOSE_EN:false" \
+"GL2_1_FABCLK_USED:false" \
+"GL2_1_FREQ_SEL:false" \
+"GL2_1_IS_USED:false" \
+"GL2_1_OUT_FREQ:0" \
+"GL2_1_PHASE_INDEX:0" \
+"GL2_1_PHASE_SEL:false" \
+"GL2_1_PLL_PHASE:0" \
+"GL3_0_BANKCLK_USED:false" \
+"GL3_0_BYPASS:0" \
+"GL3_0_BYPASS_EN:false" \
+"GL3_0_DEDICATED_USED:false" \
+"GL3_0_DIV:1" \
+"GL3_0_DIVSTART:0" \
+"GL3_0_DYNAMIC_PH:false" \
+"GL3_0_EXPOSE_EN:false" \
+"GL3_0_FABCLK_GATED_USED:false" \
+"GL3_0_FABCLK_USED:true" \
+"GL3_0_FREQ_SEL:false" \
+"GL3_0_IS_USED:false" \
+"GL3_0_OUT_FREQ:100" \
+"GL3_0_PHASE_INDEX:0" \
+"GL3_0_PHASE_SEL:false" \
+"GL3_0_PLL_PHASE:0" \
+"GL3_1_BANKCLK_USED:false" \
+"GL3_1_BYPASS:0" \
+"GL3_1_BYPASS_EN:false" \
+"GL3_1_DEDICATED_USED:false" \
+"GL3_1_DIV:1" \
+"GL3_1_DIVSTART:0" \
+"GL3_1_DYNAMIC_PH:false" \
+"GL3_1_EXPOSE_EN:false" \
+"GL3_1_FABCLK_USED:false" \
+"GL3_1_FREQ_SEL:false" \
+"GL3_1_IS_USED:false" \
+"GL3_1_OUT_FREQ:0" \
+"GL3_1_PHASE_INDEX:0" \
+"GL3_1_PHASE_SEL:false" \
+"GL3_1_PLL_PHASE:0" \
+"PLL_ALLOW_CCC_EXT_FB:false" \
+"PLL_BANDWIDTH_0:2" \
+"PLL_BANDWIDTH_1:1" \
+"PLL_BYPASS_GO_B_0:false" \
+"PLL_BYPASS_GO_B_1:false" \
+"PLL_BYPASS_POST_0:0" \
+"PLL_BYPASS_POST_0_0:false" \
+"PLL_BYPASS_POST_0_1:false" \
+"PLL_BYPASS_POST_0_2:false" \
+"PLL_BYPASS_POST_0_3:false" \
+"PLL_BYPASS_POST_1:0" \
+"PLL_BYPASS_POST_1_0:false" \
+"PLL_BYPASS_POST_1_1:false" \
+"PLL_BYPASS_POST_1_2:false" \
+"PLL_BYPASS_POST_1_3:false" \
+"PLL_BYPASS_PRE_0:0" \
+"PLL_BYPASS_PRE_0_0:false" \
+"PLL_BYPASS_PRE_0_1:false" \
+"PLL_BYPASS_PRE_0_2:false" \
+"PLL_BYPASS_PRE_0_3:false" \
+"PLL_BYPASS_PRE_1:0" \
+"PLL_BYPASS_PRE_1_0:false" \
+"PLL_BYPASS_PRE_1_1:false" \
+"PLL_BYPASS_PRE_1_2:false" \
+"PLL_BYPASS_PRE_1_3:false" \
+"PLL_BYPASS_SEL_0:0" \
+"PLL_BYPASS_SEL_0_0:false" \
+"PLL_BYPASS_SEL_0_1:false" \
+"PLL_BYPASS_SEL_0_2:false" \
+"PLL_BYPASS_SEL_0_3:false" \
+"PLL_BYPASS_SEL_1:0" \
+"PLL_BYPASS_SEL_1_0:false" \
+"PLL_BYPASS_SEL_1_1:false" \
+"PLL_BYPASS_SEL_1_2:false" \
+"PLL_BYPASS_SEL_1_3:false" \
+"PLL_DELAY_LINE_REF_FB_0:false" \
+"PLL_DELAY_LINE_REF_FB_1:false" \
+"PLL_DELAY_LINE_USED_0:false" \
+"PLL_DELAY_LINE_USED_1:false" \
+"PLL_DELAY_STEPS_0:1" \
+"PLL_DELAY_STEPS_1:1" \
+"PLL_DLL_CASCADED_EN:false" \
+"PLL_DYNAMIC_CONTROL_EN_0:true" \
+"PLL_DYNAMIC_CONTROL_EN_1:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
+"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
+"PLL_EXPORT_PWRDWN:false" \
+"PLL_EXT_MAX_ADDR_0:128" \
+"PLL_EXT_MAX_ADDR_1:128" \
+"PLL_EXT_WAVE_SEL_0:0" \
+"PLL_EXT_WAVE_SEL_1:0" \
+"PLL_FB_CLK_0:GL0_0" \
+"PLL_FB_CLK_1:GL0_1" \
+"PLL_FEEDBACK_MODE_0:Post-VCO" \
+"PLL_FEEDBACK_MODE_1:Post-VCO" \
+"PLL_IN_FREQ_0:100" \
+"PLL_IN_FREQ_1:100" \
+"PLL_INT_MODE_EN_0:false" \
+"PLL_INT_MODE_EN_1:false" \
+"PLL_LOCK_COUNT_0:8" \
+"PLL_LOCK_COUNT_1:8" \
+"PLL_LP_REQUIRES_LOCK_EN_0:false" \
+"PLL_LP_REQUIRES_LOCK_EN_1:false" \
+"PLL_PLL_CASCADED_EN:false" \
+"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
+"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
+"PLL_REF_CLK_SEL_0:false" \
+"PLL_REF_CLK_SEL_1:false" \
+"PLL_REFDIV_0:1" \
+"PLL_REFDIV_1:1" \
+"PLL_RESET_ON_LOCK_0:true" \
+"PLL_SPREAD_MODE_0:false" \
+"PLL_SPREAD_MODE_1:false" \
+"PLL_SSM_DEPTH_0:5" \
+"PLL_SSM_DEPTH_1:5" \
+"PLL_SSM_DIVVAL_0:1" \
+"PLL_SSM_DIVVAL_1:1" \
+"PLL_SSM_FREQ_0:32" \
+"PLL_SSM_FREQ_1:32" \
+"PLL_SSM_RAND_PATTERN_0:2" \
+"PLL_SSM_RAND_PATTERN_1:2" \
+"PLL_SSMD_EN_0:false" \
+"PLL_SSMD_EN_1:false" \
+"PLL_SYNC_CORNER_PLL:false" \
+"PLL_SYNC_EN:false" \
+"PLL_VCO_MODE_0:MIN_JITTER" \
+"PLL_VCO_MODE_1:MIN_JITTER" }
+# Exporting Component Description of PF_CCC_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
new file mode 100644
index 0000000..c6a23b9
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_CLK_DIV_C0.tcl
@@ -0,0 +1,9 @@
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_CLK_DIV_C0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_CLK_DIV:* -component_name {PF_CLK_DIV_C0} -params {\
+"DIVIDER:4" \
+"ENABLE_BIT_SLIP:false" \
+"ENABLE_SRESET:false" }
+# Exporting Component Description of PF_CLK_DIV_C0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_OSC_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_OSC_0.tcl
new file mode 100644
index 0000000..88eb2d4
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_OSC_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_OSC_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_OSC_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_OSC:1.0.102 -component_name {PF_OSC_0} -params {\
+"RCOSC_2MHZ_CLK_DIV_EN:false" \
+"RCOSC_2MHZ_GL_EN:false" \
+"RCOSC_2MHZ_NGMUX_EN:false" \
+"RCOSC_160MHZ_CLK_DIV_EN:false" \
+"RCOSC_160MHZ_GL_EN:true" \
+"RCOSC_160MHZ_NGMUX_EN:false" }
+# Exporting Component Description of PF_OSC_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
new file mode 100644
index 0000000..71025d8
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_TX_PLL_0.tcl
@@ -0,0 +1,35 @@
+# Exporting Component Description of PF_TX_PLL_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_TX_PLL_0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_TX_PLL:*} -component_name {PF_TX_PLL_0} -params {\
+"CORE:PF_TX_PLL" \
+"INIT:0x0" \
+"TxPLL_AUX_LOW_SEL:true" \
+"TxPLL_AUX_OUT:125" \
+"TxPLL_BANDWIDTH:Low" \
+"TxPLL_CLK_125_EN:true" \
+"TxPLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
+"TxPLL_EXT_WAVE_SEL:0" \
+"TxPLL_FAB_LOCK_EN:false" \
+"TxPLL_FAB_REF:200" \
+"TxPLL_INTEGER_MODE:false" \
+"TxPLL_JITTER_MODE_AT_POWERUP:true" \
+"TxPLL_JITTER_MODE_CUT_OFF_FREQ:5000" \
+"TxPLL_JITTER_MODE_OPTIMIZE_FOR:0" \
+"TxPLL_JITTER_MODE_REFCLK_FREQ:125" \
+"TxPLL_JITTER_MODE_REFCLK_SEL:DEDICATED" \
+"TxPLL_JITTER_MODE_SEL:10G SyncE 32Bit" \
+"TxPLL_JITTER_MODE_WANDER:15" \
+"TxPLL_MODE:NORMAL" \
+"TxPLL_OUT:2500.000" \
+"TxPLL_REF:156.25" \
+"TxPLL_RN_FILTER:false" \
+"TxPLL_SOURCE:FABRIC" \
+"TxPLL_SSM_DEPTH:0" \
+"TxPLL_SSM_DIVVAL:1" \
+"TxPLL_SSM_DOWN_SPREAD:false" \
+"TxPLL_SSM_FREQ:64" \
+"TxPLL_SSM_RAND_PATTERN:0" \
+"VCOFREQUENCY:1600" }
+# Exporting Component Description of PF_TX_PLL_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
new file mode 100644
index 0000000..1d1081e
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_0.tcl
@@ -0,0 +1,55 @@
+# Exporting Component Description of PF_XCVR_0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-1FCVG484I
+# Create and Configure the core component PF_XCVR_0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -component_name {PF_XCVR_0} -params {\
+"EXPOSE_ALL_DEBUG_PORTS:false" \
+"EXPOSE_FWF_EN_PORTS:false" \
+"SHOW_UNIVERSAL_SOLN_PORTS:true" \
+"UI_CDR_LOCK_MODE:Lock to data" \
+"UI_CDR_REFERENCE_CLK_FREQ:156.25" \
+"UI_CDR_REFERENCE_CLK_SOURCE:Fabric" \
+"UI_CDR_REFERENCE_CLK_TOLERANCE:1" \
+"UI_ENABLE_32BIT_DATA_WIDTH:false" \
+"UI_ENABLE_64B66B:true" \
+"UI_ENABLE_64B67B:false" \
+"UI_ENABLE_64B6XB_MODE:false" \
+"UI_ENABLE_8B10B_MODE:true" \
+"UI_ENABLE_BER:false" \
+"UI_ENABLE_DISPARITY:false" \
+"UI_ENABLE_FIBRE_CHANNEL_DISPARITY:false" \
+"UI_ENABLE_PHASE_COMP_MODE:false" \
+"UI_ENABLE_PIPE_MODE:false" \
+"UI_ENABLE_PMA_MODE:false" \
+"UI_ENABLE_SCRAMBLING:false" \
+"UI_ENABLE_SWITCH_BETWEEN_CDR_REFCLKS:false" \
+"UI_ENABLE_SWITCH_BETWEEN_TXPLLS:false" \
+"UI_EXPOSE_APBLINK_PORTS:false" \
+"UI_EXPOSE_CDR_BITSLIP_PORT:false" \
+"UI_EXPOSE_DYNAMIC_RECONFIGURATION_PORTS:false" \
+"UI_EXPOSE_JA_CLOCK_PORT:false" \
+"UI_EXPOSE_RX_READY_VAL_CDR_PORT:false" \
+"UI_EXPOSE_TX_BYPASS_DATA:false" \
+"UI_EXPOSE_TX_ELEC_IDLE:false" \
+"UI_INTERFACE_RXCLOCK:Regional" \
+"UI_INTERFACE_TXCLOCK:Regional" \
+"UI_IS_CONFIGURED:true" \
+"UI_NUMBER_OF_LANES:1" \
+"UI_PCS_ARST_N:RX Only" \
+"UI_PIPE_PROTOCOL_USED:PCIe" \
+"UI_PMA_ARST_N:TX and RX PMA" \
+"UI_PROTOCOL_PRESET_USED:None" \
+"UI_RX_DATA_RATE:5000" \
+"UI_RX_PCS_FAB_IF_WIDTH:32" \
+"UI_SATA_IDLE_BURST_TIMING:MAC" \
+"UI_TX_CLK_DIV_FACTOR:1" \
+"UI_TX_DATA_RATE:5000" \
+"UI_TX_PCS_FAB_IF_WIDTH:32" \
+"UI_TX_RX_MODE:Duplex" \
+"UI_USE_INTERFACE_CLK_AS_PLL_REFCLK:false" \
+"UI_XCVR_RX_CALIBRATION:None (CDR)" \
+"UI_XCVR_RX_DATA_EYE_CALIBRATION:false" \
+"UI_XCVR_RX_DFE_COEFF_CALIBRATION:false" \
+"UI_XCVR_RX_ENHANCED_MANAGEMENT:true" \
+"XT_ES_DEVICE:false" }
+# Exporting Component Description of PF_XCVR_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
new file mode 100644
index 0000000..94d64dc
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/PF_XCVR_REF_CLK_0.tcl
@@ -0,0 +1,12 @@
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component PF_XCVR_REF_CLK_0
+create_and_configure_core -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:* -component_name {PF_XCVR_REF_CLK_0} -params {\
+"ENABLE_FAB_CLK_0:false" \
+"ENABLE_FAB_CLK_1:false" \
+"ENABLE_REF_CLK_0:true" \
+"ENABLE_REF_CLK_1:false" \
+"REF_CLK_MODE_0:DIFFERENTIAL" \
+"REF_CLK_MODE_1:LVCMOS" }
+# Exporting Component Description of PF_XCVR_REF_CLK_0 to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_Block.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_Block.tcl
new file mode 100644
index 0000000..56de848
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_Block.tcl
@@ -0,0 +1,66 @@
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvv Create Transceivers Reset Block vvvvvvvvvvvvvvvvvvvvvvv"
+puts "vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv"
+
+# Creating SmartDesign Reset_Block
+set sd_name {Reset_Block}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_x_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_y_VDDI_STATUS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_clk} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_ready} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk_stable} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_clk} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_chk_rst_n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {Pattern_gen_rst_n} -port_direction {OUT}
+
+
+
+# Add Reset_sync_rx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_rx} -instance_name {Reset_sync_rx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_rx_0:PLL_POWERDOWN_B}
+
+
+
+# Add Reset_sync_tx_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_sync_tx} -instance_name {Reset_sync_tx_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:SS_BUSY} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FF_US_RESTORE} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:FPGA_POR_N} -value {VCC}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Reset_sync_tx_0:PLL_POWERDOWN_B}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_x_VDDI_STATUS" "Reset_sync_rx_0:BANK_x_VDDI_STATUS" "Reset_sync_tx_0:BANK_x_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_y_VDDI_STATUS" "Reset_sync_rx_0:BANK_y_VDDI_STATUS" "Reset_sync_tx_0:BANK_y_VDDI_STATUS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_sync_rx_0:EXT_RST_N" "Reset_sync_tx_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "Reset_sync_rx_0:INIT_DONE" "Reset_sync_tx_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_chk_rst_n" "Reset_sync_rx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Pattern_gen_rst_n" "Reset_sync_tx_0:FABRIC_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_clk" "Reset_sync_rx_0:CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RX_ready" "Reset_sync_rx_0:PLL_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:CLK" "TX_clk" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_sync_tx_0:PLL_LOCK" "TX_clk_stable" }
+
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign Reset_Block
+generate_component -component_name ${sd_name}
+
+puts "^^^^^^^^^^^^^^^^^ Create Transceivers Reset Block Complete ^^^^^^^^^^^^^^^^^^^"
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_rx.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_rx.tcl
new file mode 100644
index 0000000..b2fad00
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_rx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_rx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_rx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_rx} -params { }
+# Exporting Component Description of Reset_sync_rx to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_tx.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_tx.tcl
new file mode 100644
index 0000000..18005a5
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/Reset_sync_tx.tcl
@@ -0,0 +1,6 @@
+# Exporting Component Description of Reset_sync_tx to TCL
+# Family: PolarFire
+# Part Number: MPF300TS-1FCG1152I
+# Create and Configure the core component Reset_sync_tx
+create_and_configure_core -core_vlnv Actel:DirectCore:CORERESET_PF:2.3.100 -component_name {Reset_sync_tx} -params { }
+# Exporting Component Description of Reset_sync_tx to TCL done
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
new file mode 100644
index 0000000..31bb785
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/XCVR_LOOPBACK/XCVR_LOOPBACK.tcl
@@ -0,0 +1,151 @@
+# Creating SmartDesign XCVR_LOOPBACK
+set sd_name {XCVR_LOOPBACK}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_BIT_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RCOSC_160MHZ_GL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_REF_CLK} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_0_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_1_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_2_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TEST_MODE_3_LED} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {error_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {lock_o} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val_o} -port_direction {OUT}
+
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_0} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {slave} -port_bif_mapping {\
+"LOCK:CLKS_FROM_TXPLL_0_TX_PLL_LOCK_0" \
+"BIT_CLK:CLKS_FROM_TXPLL_0_TX_BIT_CLK_0" \
+"REF_CLK_TO_LANE:CLKS_FROM_TXPLL_0_TX_PLL_REF_CLK_0" }
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add pattern_chk_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_CHK} -instance_name {pattern_chk_0}
+# Exporting Parameters of instance pattern_chk_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_chk_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_chk_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {pattern_chk_0:s_count} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:RESET_EN} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:generate_err} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:LANE_ARST_N}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:start_i} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:clear_i} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_count_o}
+
+
+
+# Add pattern_gen_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {PATTERN_GEN} -instance_name {pattern_gen_0}
+# Exporting Parameters of instance pattern_gen_0
+sd_configure_core_instance -sd_name ${sd_name} -instance_name {pattern_gen_0} -params {\
+"g_DATA_WID:32" \
+"STATE_0:0" \
+"STATE_1:1" \
+"STATE_2:2" \
+"STATE_3:3" \
+"STATE_4:4" \
+"STATE_5:5" }\
+-validate_rules 0
+sd_save_core_instance_config -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_update_instance -sd_name ${sd_name} -instance_name {pattern_gen_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_gen_0:generate_err_i} -value {GND}
+
+
+
+# Add PF_XCVR_0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_IDLE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_TX_DISPFNC} -value {GND}
+
+
+
+# Add Reset_Block_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_Block} -instance_name {Reset_Block_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_x_VDDI_STATUS} -value {VCC}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Reset_Block_0:BANK_y_VDDI_STATUS} -value {VCC}
+
+
+
+# Add startup_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {STARTUP} -instance_name {startup_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_XCVR_0_0:LANE0_TX_CLK_STABLE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "XCVR_REF_CLK_LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "Reset_Block_0:TX_clk_stable" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "Reset_Block_0:INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"EXT_RST_N" "Reset_Block_0:EXT_RST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_0_0:LANE0_RXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_0_0:LANE0_RXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_0_0:LANE0_TXD_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_0_0:LANE0_TXD_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_ARST_N" "PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE0_PMA_ARST_N" "XCVR_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CTRL_CLK" "RCOSC_160MHZ_GL" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_CDR_REF_CLK_FAB" "XCVR_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CLK_R" "Reset_Block_0:RX_clk" "pattern_chk_0:clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_READY" "Reset_Block_0:RX_ready" "pattern_chk_0:RX_READY" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_VAL" "pattern_chk_0:rx_val_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_R" "Reset_Block_0:TX_clk" "pattern_gen_0:clk_i" "startup_0:tx_clk_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_chk_rst_n" "TEST_MODE_3_LED" "pattern_chk_0:ARST_N" "pattern_chk_0:reset_n_i" "startup_0:pattern_chk_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_gen_rst_n" "startup_0:pattern_gen_n_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_0_LED" "pattern_chk_0:s_count[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_1_LED" "pattern_chk_0:s_count[1:1]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TEST_MODE_2_LED" "pattern_chk_0:s_count[2:2]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"error_o" "pattern_chk_0:error_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"lock_o" "pattern_chk_0:lock_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_chk_0:rx_val_o" "rx_val_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_0:reset_n_i" "startup_0:start_gen_o" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_RX_K" "pattern_chk_0:Rx_K_Char_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_TX_K" "pattern_gen_0:Tx_K_Char_o" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CODE_VIOLATION" "pattern_chk_0:LCV_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "pattern_chk_0:data_in_i" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DISPARITY_ERROR" "pattern_chk_0:DISP_ERR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_DATA" "pattern_gen_0:data_out_o" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_FROM_TXPLL_0" "PF_XCVR_0_0:CLKS_FROM_TXPLL_0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign XCVR_LOOPBACK
+generate_component -component_name ${sd_name}
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..dc6babf
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1,148 @@
+set_io -port_name XCVR_TX1_N \
+ -pin_name H21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX1_P \
+ -pin_name H22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX2_N \
+ -pin_name P21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX2_P \
+ -pin_name P22 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_N \
+ -pin_name T21 \
+ -DIRECTION OUTPUT
+
+set_io -port_name XCVR_TX3_P \
+ -pin_name T22 \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name XCVR_RX1_N \
+ -pin_name K21 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX1_P \
+ -pin_name K22 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_N \
+ -pin_name M21 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX2_P \
+ -pin_name M22 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_N \
+ -pin_name R19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_RX3_P \
+ -pin_name R20 \
+ -DIRECTION INPUT
+
+
+#set_io -port_name XCVR_0A_REFCLK_P \
+# -pin_name L19 \
+# -DIRECTION INPUT
+#
+#set_io -port_name XCVR_0A_REFCLK_N \
+# -pin_name L20 \
+# -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0B_REFCLK_P \
+ -pin_name N19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0B_REFCLK_N \
+ -pin_name N20 \
+ -DIRECTION INPUT
+
+
+set_io -port_name XCVR_0C_REFCLK_P \
+ -pin_name J19 \
+ -DIRECTION INPUT
+
+set_io -port_name XCVR_0C_REFCLK_N \
+ -pin_name J20 \
+ -DIRECTION INPUT
+
+
+
+set_io -port_name B0_HSIO70N \
+ -pin_name AB20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO70P \
+ -pin_name AB19 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO71N \
+ -pin_name AA20 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO71P \
+ -pin_name AB21 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO73N_C2P_CLKN \
+ -pin_name U17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO73P_C2P_CLKP \
+ -pin_name T17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO81N \
+ -pin_name AA17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO81P \
+ -pin_name AB17 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO82N \
+ -pin_name Y16 \
+ -fixed true \
+ -DIRECTION INOUT
+
+
+set_io -port_name B0_HSIO82P \
+ -pin_name AA16 \
+ -fixed true \
+ -DIRECTION INPUT
+
+
+set_io -port_name B0_HSIO83N \
+ -pin_name W17 \
+ -fixed true \
+ -DIRECTION OUTPUT
+
+
+set_io -port_name B0_HSIO83P \
+ -pin_name W16 \
+ -fixed true \
+ -DIRECTION INPUT
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..06e341a
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1,8 @@
+
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_0/I_IO -fixed true -x 1014 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_0/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1009 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_TX_PLL_0_0/PF_TX_PLL_0_0/txpll_isnt_0 -fixed true -x 1009 -y 77
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_2/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_XCVR_REF_CLK_0_0/PF_XCVR_REF_CLK_0_0/I_IO -fixed true -x 1015 -y 74
+set_location -inst_name HIGH_SPEED_INTERFACE_0/PF_TX_PLL_XCVR1_0/PF_TX_PLL_XCVR1_0/txpll_isnt_0 -fixed true -x 1008 -y 77
+set_location -inst_name HIGH_SPEED_INTERFACE_0/XCVR_LOOPBACK_1/PF_XCVR_0_0/I_XCVR/LANE0 -fixed true -x 1008 -y 47
--
GitLab
From b1a286e90d6025fc17c732ffe89f45e911d585d6 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 18:52:42 +0100
Subject: [PATCH 13/19] SYZYGY: Add floor placement constraints for all build
options.
---
.../constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
.../constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
.../DEFAULT/constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
.../IO_BOARD_VALIDATION/constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
.../IO_STUB/constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
.../NONE/constraints/fp/HIGH_SPEED_CONNECTOR.pdc | 1 +
6 files changed, 6 insertions(+)
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/NONE/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_OPAL_KELLY/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO_2_LANES/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/DEFAULT/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_BOARD_VALIDATION/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/IO_STUB/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/NONE/constraints/fp/HIGH_SPEED_CONNECTOR.pdc b/script_support/components/HIGH_SPEED_CONNECTOR/NONE/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
new file mode 100644
index 0000000..329be74
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/NONE/constraints/fp/HIGH_SPEED_CONNECTOR.pdc
@@ -0,0 +1 @@
+# No floor placement required for this build option.
--
GitLab
From 77fe29fe946d42e9f6761dc33f781a5d6ca452cc Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Tue, 27 Jun 2023 12:00:02 +0100
Subject: [PATCH 14/19] PCIe: Add device tree overlay
---
.../components/M2/DEFAULT/device-tree-overlay/pcie.dtso | 9 +++++++++
1 file changed, 9 insertions(+)
create mode 100644 script_support/components/M2/DEFAULT/device-tree-overlay/pcie.dtso
diff --git a/script_support/components/M2/DEFAULT/device-tree-overlay/pcie.dtso b/script_support/components/M2/DEFAULT/device-tree-overlay/pcie.dtso
new file mode 100644
index 0000000..0c8fa68
--- /dev/null
+++ b/script_support/components/M2/DEFAULT/device-tree-overlay/pcie.dtso
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&pcie {
+ status = "okay";
+};
--
GitLab
From 2d4d5a454888015706839d819edf9a8f39a5e0c1 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 18:13:20 +0100
Subject: [PATCH 15/19] Device tree: Add test devive tree for cape and SYZYGY.
---
.../CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso | 10 ++++++++++
.../device-tree-overlay/syzygy-test-gpios.dtso | 9 +++++++++
.../device-tree-overlay/syzygy-test-gpios.dtso | 9 +++++++++
3 files changed, 28 insertions(+)
create mode 100644 script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
create mode 100644 script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
diff --git a/script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso b/script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso
new file mode 100644
index 0000000..dc69c5c
--- /dev/null
+++ b/script_support/components/CAPE/GPIOS/device-tree-overlay/cape-gpios.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+
+&cape_gpios_p9 {
+ status = "okay";
+};
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
new file mode 100644
index 0000000..84b44f8
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_TESTS_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&hsi_gpios {
+ status = "okay";
+};
diff --git a/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
new file mode 100644
index 0000000..84b44f8
--- /dev/null
+++ b/script_support/components/HIGH_SPEED_CONNECTOR/BOARD_VALIDATION_SEEED_STUDIO/device-tree-overlay/syzygy-test-gpios.dtso
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&hsi_gpios {
+ status = "okay";
+};
--
GitLab
From c8c9130e41a8dfa59875d397d531ce27782fa675 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 23 Jul 2023 22:13:18 +0100
Subject: [PATCH 16/19] Programming: Enable auto-update.
---
BUILD_BVF_GATEWARE.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index 7f41fd0..f78007a 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -265,7 +265,7 @@ if !{[info exists ONLY_CREATE_DESIGN]} {
run_tool -name {GENERATEPROGRAMMINGDATA}
configure_envm -cfg_file {script_support/components/MSS/ENVM.cfg}
source ./script_support/export_spi_prog_file.tcl
-# configure_spiflash -cfg_file {./script_support/spiflash.cfg}
+ configure_spiflash -cfg_file {./script_support/spiflash.cfg}
run_tool -name {GENERATEPROGRAMMINGFILE}
# run_tool -name {GENERATE_SPI_FLASH_IMAGE}
source ./script_support/export_flashproexpress.tcl
--
GitLab
From 6cecbf8de4f8ce72419e27797347eae7a01e29a9 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 6 Aug 2023 18:28:27 +0100
Subject: [PATCH 17/19] Add download of MIPI CSI Rx Decoder IP block.
---
BUILD_BVF_GATEWARE.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index f78007a..e2dbbbf 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -170,7 +170,6 @@ download_core -vlnv {Actel:SgCore:PF_PCIE:*} -location {www.microchip-ip.com/rep
download_core -vlnv {Actel:SgCore:PF_TX_PLL:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
-#download_core -vlnv {Actel:DirectCore:COREAXI4DMACONTROLLER:2.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:Simulation:CLK_GEN:1.0.1} -location {www.microchip-ip.com/repositories/SgCore}
@@ -181,6 +180,7 @@ download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microc
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_IO:*} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:*} -location {www.microchip-ip.com/repositories/SgCore}
+download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location {www.microchip-ip.com/repositories/DirectCore}
#
# // Generate base design
--
GitLab
From 155b42d81af5eed26137883db6380051db03936a Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Fri, 11 Aug 2023 17:56:24 +0100
Subject: [PATCH 18/19] Doc: Update Readme links and script arguments.
---
IHC_SUBSYSTEM_block_diagram.svg | 4 -
Readme.md | 216 ++++++--------------------------
block_diagram.svg | 3 -
3 files changed, 35 insertions(+), 188 deletions(-)
delete mode 100644 IHC_SUBSYSTEM_block_diagram.svg
delete mode 100644 block_diagram.svg
diff --git a/IHC_SUBSYSTEM_block_diagram.svg b/IHC_SUBSYSTEM_block_diagram.svg
deleted file mode 100644
index 617a1a4..0000000
--- a/IHC_SUBSYSTEM_block_diagram.svg
+++ /dev/null
@@ -1,4 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Do not edit this file with editors other than diagrams.net -->
-<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
-<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1" width="1947px" height="1451px" viewBox="-0.5 -0.5 1947 1451" content="<mxfile host="Electron" modified="2021-10-22T11:39:40.919Z" agent="5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/15.4.0 Chrome/91.0.4472.164 Electron/13.5.0 Safari/537.36" etag="kTS40SdD4Be1CIF_7t9N" version="15.4.0" type="device"><diagram id="-lVU6hSQ6pfmJltsPebP" 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-0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 208px; margin-left: 1576px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">CH1_ACK_IRQ</div></div></div></foreignObject><text x="1576" y="208" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">CH1_ACK_IRQ</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 236px; margin-left: 1176px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">SIDE_A_MSG_PRESENT</div></div></div></foreignObject><text x="1176" y="236" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">SIDE_A_MSG_PRESENT</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 238px; margin-left: 1574px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">CH2_MSG_PRESENT_IRQ</div></div></div></foreignObject><text x="1574" y="238" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">CH2_MSG_PRESENT_IRQ</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 258px; margin-left: 1166px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">SIDE_A_ACK_FROM_B</div></div></div></foreignObject><text x="1166" y="258" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">SIDE_A_ACK_FROM_B</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 268px; margin-left: 1575px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">CH2_ACK_IRQ</div></div></div></foreignObject><text x="1575" y="268" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">CH2_ACK_IRQ</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 298px; margin-left: 1576px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; 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1px; height: 1px; padding-top: 518px; margin-left: 1576px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">CH0_MSG_PRESENT_IRQ</div></div></div></foreignObject><text x="1576" y="518" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">CH0_MSG_PRESENT_IRQ</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 538px; margin-left: 1576px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">CH0_ACK_IRQ</div></div></div></foreignObject><text x="1576" y="538" fill="#000000" font-family="Helvetica" font-size="11px" text-anchor="end">CH0_ACK_IRQ</text></switch></g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-end; width: 1px; height: 1px; padding-top: 358px; margin-left: 1181px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; 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\ No newline at end of file
diff --git a/Readme.md b/Readme.md
index 3bc7c68..e8ee46a 100644
--- a/Readme.md
+++ b/Readme.md
@@ -1,197 +1,51 @@
-# B-V-F
+# BeagleV Fire Gateware
## Description
-This repository can be used to generate a reference design for the B-V-F. This reference design will have the same or extended functionality compared to the pre-programmed FPGA design on the B-V-F.
+This repository is used to generate the BeagleV Fire FPGA design. The scripts in this repository concentrate on generating the FPGA digital logic content and generating bitstreams. The complete gateware for the BeagleV Fire also includes a first stage bootloader (HSS) which configures the entire PolarFire SoC device. It is therefore recommended to use the **BeagleV Fire Bitstream Builder** to generate the complete gateware including the HSS for the BeagleV Fire. The BeagleV Fire Bitstream Builder is availabe [here](https://git.beagleboard.org/beaglev-fire/bitstream-builder)
-A Libero SoC Tcl script is provided to generate the reference design using Libero SoC along with device specific I/O constraints.
+**The scripts contained in this repository are only recommended to be used in isolation when modifying the FPGA digital logic.** Otherwise please use the [BeagleV Fire Bitstream Builder](https://git.beagleboard.org/beaglev-fire/bitstream-builder).
-This repository supports Libero SoC v2021.3, which is available for download [here](https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads).
+A set of Libero SoC Tcl scripts are provided to generate the FPGA design using Libero SoC along with device specific I/O constraints.
-## Using the reference design generation Tcl script
+This repository supports Libero SoC v2022.3, which is available for download [here](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#downloads).
+## Using the reference design generation Tcl script
+The gateware is built by executing a Libero Tcl script. The default gateware configuration is built using the command below:
```
-libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE"
+libero SCRIPT:BUILD_BVF_GATEWARE.tcl
```
-Create absolute minimal design:
+Arguments can be passed to the Tcl script to select build options for the design or prevent Libero from running through the entire flow.
```
-libero SCRIPT:B_V_F_REFERENCE_DESIGN.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE"
+libero SCRIPT:BUILD_BVF_GATEWARE.tcl "SCRIPT_ARGS: ONLY_CREATE_DESIGN M2_OPTION:NONE CAPE_OPTION:NONE"
```
+### Available arguments:
+
+#### ONLY_CREATE_DESIGN
+Stops the FPGA flow before running synthesis. This is useful to inspect the generated FPGA design before running throught the Synthesis/Place and route/Bitstream FPGA flow.
+
+#### CAPE_OPTION
+Specifes the build option for the digital logic attached to the cape connectors. Valid values are the directory names in ./script_support/components/CAPE. If you wish to create an alternate build option, add a new directory in ./script_support/components/CAPE using one of the existing ones as template. This is a good place to start if you want to play with FPGA digital logic.
+
+#### M2_OPTION
+Specifes the build option for the digital logic attached to the M.2 connector. Options are DEFAULT to enable the wi-fi interface or NONE if you do not need wi-fi and want to use the third transceiver on the SYZYGY connector..
+
+#### HIGH_SPEED_CONN_OPTION
+Specifes the build option for the digital logic attached to the SYZYGY high speed connector. Valid values are the directory names in ./script_support/components/HIGH_SPEED_CONNECTOR. If you wish to create an alternate build option, add a new directory in ./script_support/components/HIGH_SPEED_CONNECTOR using one of the existing ones as template. This is a good place to experiment if you want to use wired communications up to 12.5Gbps.
+
+#### MIPI_CSI_OPTION
+Specifies the build option associated with the camera interface. Valid values are the directory names in ./script_support/components/MIPI_CSI. If you wish to create an alternate build option, add a new directory using one of the existing ones as template.
+
+#### PROJECT_LOCATION
+Specifies where the generated Libero project will be located.
+#### TOP_LEVEL_NAME
+Specifies the name of the gateware's top level module. This will also be the name of the FPGA design reported through System Services and displayed at boot time by the Hart Software Services (HSS). This will allow you to identify what is actually programmed on the board.
+#### PROG_EXPORT_PATH
+Specifies the location where the programming files will be exported.
-#### Standard design generation
-
-To generate the standard reference design which is capable of running the majority of bare metal example applications and run Linux® the following flow can be used:
-
-1. Clone or download the repository
-2. Open Libero v2021.3
-3. Open the execute script dialog (CTRL + U)
-4. Execute the "B_V_F_REFERENCE_DESIGN.tcl" script
-5. Configure the design if required
-6. Run the Libero SoC design flow to program a device
-
-## Headers
-
-### P9
-
-| Header Pin | FPGA Pin | Usage |
-|------------|----------|------------------------------|
-| 1 | n/a | DGND |
-| 2 | n/a | DGND |
-| 3 | n/a | VDD_3V3 |
-| 4 | n/a | VDD_3V3 |
-| 5 | n/a | VDD_5V |
-| 6 | n/a | VDD_5V |
-| 7 | n/a | SYS_5V |
-| 8 | n/a | SYS_5V |
-| 9 | n/a | Not connected |
-| 10 | n/a | SYSRESETn |
-| 11 | B5 | MMUART_4 Rx |
-| 12 | C5 | MSS GPIO_2[11] (@0x20122000) |
-| 13 | D19 | MMUART_4 Tx |
-| 14 | C6 | PWM channel 1 (@0x41000000) |
-| 15 | A5 | MSS GPIO_2[12] (@0x20122000) |
-| 16 | A6 | PWM channel 2 (@0x41000000) |
-| 17 | C9 | MSS GPIO_2[13] (@0x20122000) |
-| 18 | C10 | MSS GPIO_2[14] (@0x20122000) |
-| 19 | A11 | MSS I2C0 SCL |
-| 20 | A10 | MSS I2C0 SDA |
-| 21 | B8 | MSS GPIO_2[15] (@0x20122000) |
-| 22 | A8 | MSS GPIO_2[16] (@0x20122000) |
-| 23 | C12 | MSS GPIO_2[17] (@0x20122000) |
-| 24 | B12 | MSS GPIO_2[18] (@0x20122000) |
-| 25 | B7 | MSS GPIO_2[19] (@0x20122000) |
-| 26 | A7 | MSS GPIO_2[20] (@0x20122000) |
-| 27 | D11 | MSS GPIO_2[21] (@0x20122000) |
-| 28 | C11 | MSS GPIO_2[22] (@0x20122000) |
-| 29 | F17 | MSS GPIO_2[23] (@0x20122000) |
-| 30 | F16 | MSS GPIO_2[24] (@0x20122000) |
-| 31 | E18 | MSS GPIO_2[25] (@0x20122000) |
-| 32 | n/a | VDD_ADC |
-| 33 | n/a | ADC channel 4 |
-| 34 | n/a | GNDA_ADC |
-| 35 | n/a | ADC channel 6 |
-| 36 | n/a | ADC channel 5 |
-| 37 | n/a | ADC channel 2 |
-| 38 | n/a | ADC channel 3 |
-| 39 | n/a | ADC channel 0 |
-| 40 | n/a | ADC channel 1 |
-| 41 | E15 | MSS GPIO_2[26] (@0x20122000) |
-| 42 | E14 | PWM channel 0 (@0x41000000) |
-| 43 | n/a | GND |
-| 44 | n/a | GND |
-| 45 | n/a | GND |
-| 46 | n/a | GND |
-
-### P8
-
-| Header Pin | FPGA Pin | Usage |
-|------------|----------|-----------------------------------------|
-| 1 | n/a | DGND |
-| 2 | n/a | DGND |
-| 3 | V22 | Base design FPGA GPIO[0] (@0x40000000) |
-| 4 | W22 | Base design FPGA GPIO[1] (@0x40000000) |
-| 5 | V19 | Base design FPGA GPIO[2] (@0x40000000) |
-| 6 | V20 | Base design FPGA GPIO[3] (@0x40000000) |
-| 7 | V15 | Base design FPGA GPIO[4] (@0x40000000) |
-| 8 | V14 | Base design FPGA GPIO[5] (@0x40000000) |
-| 9 | V21 | Base design FPGA GPIO[6] (@0x40000000) |
-| 10 | W21 | Base design FPGA GPIO[7] (@0x40000000) |
-| 11 | Y21 | Base design FPGA GPIO[8] (@0x40000000) |
-| 12 | Y20 | Base design FPGA GPIO[9] (@0x40000000) |
-| 13 | B10 | Base design FPGA GPIO[10] (@0x40000000) |
-| 14 | B9 | Base design FPGA GPIO[11] (@0x40000000) |
-| 15 | T12 | MSS GPIO_2[0] (@0x20122000) |
-| 16 | U12 | MSS GPIO_2[1] (@0x20122000) |
-| 17 | W13 | MSS GPIO_2[2] (@0x20122000) |
-| 18 | T16 | MSS GPIO_2[3] (@0x20122000) |
-| 19 | W18 | PWM channel 3 (@0x41000000) |
-| 20 | R16 | MSS GPIO_2[4] (@0x20122000) |
-| 21 | AA21 | MSS GPIO_2[5] (@0x20122000) |
-| 22 | AA22 | MSS GPIO_2[6] (@0x20122000) |
-| 23 | AB18 | MSS GPIO_2[7] (@0x20122000) |
-| 24 | AA18 | MSS GPIO_2[8] (@0x20122000) |
-| 25 | V17 | MSS GPIO_2[9] (@0x20122000) |
-| 26 | A12 | MSS GPIO_2[10] (@0x20122000) |
-| 27 | A13 | FPGA GPIO[18] (@0x41100000) |
-| 28 | B14 | FPGA GPIO[19] (@0x41100000) |
-| 29 | B13 | FPGA GPIO[16] (@0x41100000) |
-| 30 | D14 | FPGA GPIO[17] (@0x41100000) |
-| 31 | D13 | FPGA GPIO[0] (@0x41100000) |
-| 32 | B15 | FPGA GPIO[1] (@0x41100000) |
-| 33 | A15 | FPGA GPIO[2] (@0x41100000) |
-| 34 | C15 | FPGA GPIO[3] (@0x41100000) |
-| 35 | C14 | FPGA GPIO[4] (@0x41100000) |
-| 36 | B4 | FPGA GPIO[5] (@0x41100000) |
-| 37 | C4 | FPGA GPIO[6] (@0x41100000) |
-| 38 | C17 | FPGA GPIO[7] (@0x41100000) |
-| 39 | B17 | FPGA GPIO[8] (@0x41100000) |
-| 40 | B18 | FPGA GPIO[9] (@0x41100000) |
-| 41 | A18 | FPGA GPIO[10] (@0x41100000) |
-| 42 | D6 | FPGA GPIO[11] (@0x41100000) |
-| 43 | D7 | FPGA GPIO[12] (@0x41100000) |
-| 44 | D8 | FPGA GPIO[13] (@0x41100000) |
-| 45 | D9 | FPGA GPIO[14] (@0x41100000) |
-| 46 | D18 | FPGA GPIO[15] (@0x41100000) |
-
-### J9: M.2 Interface
-
-| Header Pin | FPGA Pin | Usage |
-|------------|----------|---------------------------------------------------|
-| 1 | n/a | GND |
-| 2 | n/a | 3.3V |
-| 3 | n/a | not connected |
-| 4 | n/a | 3.3V |
-| 5 to 6 | n/a | not connected |
-| 7 | n/a | GND |
-| 8 to 17 | n/a | not connected |
-| 18 | n/a | GND |
-| 19 | n/a | not connected |
-| 20 | R14 | M2_UART_WAKEn |
-| 21 | n/a | not connected |
-| 22 | T13 | M2_UART_RXD - MSS MMUART_1 through FPGA fabric |
-| 24 to 31 | n/a | not connected |
-| 32 | R12 | M2_UART_TXD - MSS MMUART_1 through FPGA fabric |
-| 33 | n/a | GND |
-| 34 | U14 | M2_UART_CTS - MSS MMUART_1 through FPGA fabric |
-| 35 | F22 | M2_PET0_P |
-| 36 | U13 | M2_UART_RTS - MSS MMUART_1 through FPGA fabric |
-| 37 | F21 | M2_PET0_N |
-| 38 | n/a | not connected |
-| 39 | n/a | GND |
-| 40 | n/a | not connected |
-| 41 | G20 | M2_PER0_P |
-| 42 | n/a | not connected |
-| 43 | G19 | M2_PER0_N |
-| 44 | n/a | not connected |
-| 45 | n/a | GND |
-| 46 | n/a | not connected |
-| 47 | n/a | M2_REFCLK_P - 100MHz |
-| 48 | n/a | not connected |
-| 49 | n/a | M2_REFCLK_N - 100MHz |
-| 50 | n/a | M2_32KHZ - connected to 32.687kHz oscillator |
-| 51 | n/a | GND |
-| 52 | E18 | M2_PERST0n |
-| 53 | W19 | M2_CLKREQ0n |
-| 54 | R15 | W _DISABLE2n - pull-up to 3.3V |
-| 55 | R14 | M2_PEWAKEn |
-| 56 | U19 | W _DISABLE1n - pull-up to 3.3V |
-| 57 | n/a | GND |
-| 58 | B1 | MSS I2C1 SDA |
-| 59 | n/a | not connected |
-| 60 | C1 | MSS I2C1 SCL |
-| 61 | n/a | not connected |
-| 62 | U15 | M2_I2C_ALTn |
-| 63 | n/a | GND |
-| 64 to 68 | n/a | not connected |
-| 69 | n/a | GND |
-| 70 to 71 | n/a | not connected |
-| 72 | n/a | 3.3V |
-| 73 | n/a | not connected |
-| 74 | n/a | 3.3V |
-| 75 | n/a | GND |
-| 76 | n/a | GND |
-| 77 | n/a | GND |
+#### DESIGN_VERSION
+Used to specfy the FPGA design version which will be included in the programming bitstream. Please note that care must be taken in selecting a version number if you wish to use program the generated gateware from Linux. Version numbers must be different for gateware programming from Linux to be successfull.
diff --git a/block_diagram.svg b/block_diagram.svg
deleted file mode 100644
index 47d1e52..0000000
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\ No newline at end of file
--
GitLab
From 46f133a0ab38eb2357640b0dc433bea228992428 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Fri, 11 Aug 2023 18:00:58 +0100
Subject: [PATCH 19/19] Changed the silicon signature.
---
BUILD_BVF_GATEWARE.tcl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/BUILD_BVF_GATEWARE.tcl b/BUILD_BVF_GATEWARE.tcl
index e2dbbbf..aa00037 100644
--- a/BUILD_BVF_GATEWARE.tcl
+++ b/BUILD_BVF_GATEWARE.tcl
@@ -115,7 +115,7 @@ if {[info exists DESIGN_VERSION]} {
if {[info exists SILICON_SIGNATURE]} {
set gateware_silicon_signature "$SILICON_SIGNATURE"
} else {
- set gateware_silicon_signature "deadc001"
+ set gateware_silicon_signature "bea913b0"
}
source ./script_support/additional_configurations/functions.tcl
--
GitLab