diff --git a/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl b/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
index 1bb716567cb7d38f147c0403b5ff2bf090656008..e5e1f7882d53177ac849a99ce7f91c3bb87c29b3 100644
--- a/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
+++ b/sources/FPGA-design/script_support/components/BVF_GATEWARE.tcl
@@ -294,6 +294,12 @@ sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E} -value {GND} 
 sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_F} -value {GND} 
 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_RXD} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_CTS} -value {GND} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_TXD} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_RTS} 
+
+
 #-------------------------------------------------------------------------------
 
 source script_support/components/SYZYGY/$syzygy_option/ADD_HIGH_SPEED_CONNECTOR.tcl 
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/ADD_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/ADD_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1e086a0103104a00b029cf92801ed8665e586970
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/ADD_CAPE.tcl
@@ -0,0 +1,114 @@
+puts "======== Add cape option: 4_UARTS ========"
+
+#-------------------------------------------------------------------------------
+# Build cape's submodules
+#-------------------------------------------------------------------------------
+source script_support/components/CAPE/4_UARTS/APB_BUS_CONVERTER.tcl
+source script_support/components/CAPE/4_UARTS/CoreAPB3_CAPE.tcl
+source script_support/components/CAPE/4_UARTS/CoreGPIO_LCD.tcl
+source script_support/components/CAPE/4_UARTS/P8_GPIO_UPPER.tcl
+source script_support/components/CAPE/4_UARTS/CoreGPIO_P9.tcl
+source script_support/components/CAPE/4_UARTS/P9_GPIO.tcl
+source script_support/components/CAPE/4_UARTS/CAPE_DEFAULT_GPIOS.tcl
+source script_support/components/CAPE/4_UARTS/corepwm_C1.tcl
+source script_support/components/CAPE/4_UARTS/CAPE_PWM.tcl
+source script_support/components/CAPE/4_UARTS/CAPE.tcl
+
+#-------------------------------------------------------------------------------
+# Build the Cape module
+#-------------------------------------------------------------------------------
+set sd_name ${top_level_name}
+
+#-------------------------------------------------------------------------------
+# Cape pins
+#-------------------------------------------------------------------------------
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN19} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_11} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_13} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {OUT}
+
+#-------------------------------------------------------------------------------
+# Instantiate.
+#-------------------------------------------------------------------------------
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE} -instance_name {CAPE}
+
+#-------------------------------------------------------------------------------
+# Connections.
+#-------------------------------------------------------------------------------
+
+# Clocks and resets
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "CAPE:PCLK"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "CAPE:PRESETN" }
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_TXD" "P9_13"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MMUART_4_RXD" "P9_11"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_F2M" "CAPE:GPIO_IN"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_M2F" "CAPE:GPIO_OUT"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:GPIO_2_OE_M2F" "CAPE:GPIO_OE"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_PIN13_USER_LED_10" "P8_PIN13_USER_LED_10"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P8_PIN19" "P8_PIN19"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN14" "P9_PIN14"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN16" "P9_PIN16"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:P9_PIN42" "P9_PIN42"}
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE:APB_SLAVE" "BVF_RISCV_SUBSYSTEM:CAPE_APB_MTARGET"}
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_A" "CAPE:INT_A"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_B" "CAPE:INT_B"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_C" "CAPE:INT_C"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_D" "CAPE:INT_D"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:MSS_INT_F2M_E" "CAPE:INT_E"} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_2_TXD} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_2_TXD} -new_port_name {P9_24} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_2_RXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_2_RXD} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_2_RXD} -new_port_name {P9_26} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_0_DI} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_DI} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_0_SS1} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_DI} -new_port_name {P9_18} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_0_SS1} -new_port_name {P9_17} 
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_3_TXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_3_TXD} -port_name {}
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_3_TXD} -new_port_name {P9_21}
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:MMUART_3_RXD} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:MMUART_3_RXD} -port_name {}
+sd_rename_port -sd_name ${sd_name} -current_port_name {MMUART_3_RXD} -new_port_name {P9_22}
+
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:SPI_1_DO} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_DO} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_SS1} -port_name {} 
+sd_connect_pin_to_port -sd_name ${sd_name} -pin_name {BVF_RISCV_SUBSYSTEM:SPI_1_CLK} -port_name {} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_SS1} -new_port_name {P9_28} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_CLK} -new_port_name {P9_31} 
+sd_rename_port -sd_name ${sd_name} -current_port_name {SPI_1_DO} -new_port_name {P9_29} 
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_CTS} -value {VCC} 
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_RTS} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_RXD} 
+sd_clear_pin_attributes -sd_name ${sd_name} -pin_names {BVF_RISCV_SUBSYSTEM:M2_UART_TXD} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_38} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_37} -port_direction {OUT} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:M2_UART_RXD" "P8_38"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:M2_UART_TXD" "P8_37"} 
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/APB_BUS_CONVERTER.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/APB_BUS_CONVERTER.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8e9ecf55c802890de65c48c77177ac9e889cd845
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/APB_BUS_CONVERTER.tcl
@@ -0,0 +1,47 @@
+# Creating SmartDesign APB_BUS_CONVERTER
+set sd_name {APB_BUS_CONVERTER}
+create_smartdesign -sd_name ${sd_name} 
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PADDR} -port_direction {IN} -port_range {[31:0]} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PENABLE} -port_direction {IN} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PSEL} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PSLVERR} -port_direction {OUT} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE_PWDATA} -port_direction {IN} -port_range {[31:0]} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PWRITE} -port_direction {IN} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE_PREADY} -port_direction {OUT} 
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PADDR} -port_direction {OUT} -port_range {[31:0]} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PENABLE} -port_direction {OUT} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PWRITE} -port_direction {OUT} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PSEL} -port_direction {OUT} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PSLVERR} -port_direction {IN} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PWDATA} -port_direction {OUT} -port_range {[31:0]} 
+sd_create_bus_port -sd_name ${sd_name} -port_name {MASTER_PRDATA} -port_direction {IN} -port_range {[31:0]} 
+sd_create_scalar_port -sd_name ${sd_name} -port_name {MASTER_PREADY} -port_direction {IN} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PADDR" "SLAVE_PADDR"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PENABLE" "SLAVE_PENABLE"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PWRITE" "SLAVE_PWRITE"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PSEL" "SLAVE_PSEL"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PSLVERR" "SLAVE_PSLVERR"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PWDATA" "SLAVE_PWDATA"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PRDATA" "SLAVE_PRDATA"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MASTER_PREADY" "SLAVE_PREADY"} 
+
+
+
+
+
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\ "PADDR:SLAVE_PADDR" \
+"PSELx:SLAVE_PSEL" \ "PENABLE:SLAVE_PENABLE" \
+"PWRITE:SLAVE_PWRITE" \ "PRDATA:SLAVE_PRDATA" \ "PWDATA:SLAVE_PWDATA" \ "PREADY:SLAVE_PREADY" \
+"PSLVERR:SLAVE_PSLVERR" }
+
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_MASTER} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {master} -port_bif_mapping {\ "PADDR:MASTER_PADDR" \
+"PSELx:MASTER_PSEL" \ "PENABLE:MASTER_PENABLE" \
+"PWRITE:MASTER_PWRITE" \ "PRDATA:MASTER_PRDATA" \ "PWDATA:MASTER_PWDATA" \ "PREADY:MASTER_PREADY" \
+"PSLVERR:MASTER_PSLVERR" }
+
+save_smartdesign -sd_name ${sd_name} 
+generate_component -component_name ${sd_name} -recursive 0 
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9278603775014eaae4d30ea51510ff96e1bc1e61
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE.tcl
@@ -0,0 +1,226 @@
+# Creating SmartDesign "CAPE"
+set sd_name {CAPE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN13_USER_LED_10} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN19} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN14} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN16} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN42} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN10_USER_LED_7} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN11_USER_LED_8} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN12_USER_LED_9} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN14_USER_LED_11} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN16} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN17} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN18} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN20} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN21} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN22} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN24} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN26} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN28} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN29} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN31} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN32} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN33} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN34} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN35} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN36} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN39} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN3_USER_LED_0} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN40} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN41} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN42} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN43} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN44} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN45} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN46} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN4_USER_LED_1} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN5_USER_LED_2} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN6_USER_LED_3} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN7_USER_LED_4} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN8_USER_LED_5} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P8_PIN9_USER_LED_6} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN12} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN15} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN23} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN25} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN27} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN30} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {P9_PIN41} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PADDR} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PWDATA} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_SLAVE_SLAVE_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_A} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_B} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_C} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_D} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT_E} -port_direction {OUT} -port_range {[7:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_SLAVE_SLAVE_PADDR" \
+"PSELx:APB_SLAVE_SLAVE_PSEL" \
+"PENABLE:APB_SLAVE_SLAVE_PENABLE" \
+"PWRITE:APB_SLAVE_SLAVE_PWRITE" \
+"PRDATA:APB_SLAVE_SLAVE_PRDATA" \
+"PWDATA:APB_SLAVE_SLAVE_PWDATA" \
+"PREADY:APB_SLAVE_SLAVE_PREADY" \
+"PSLVERR:APB_SLAVE_SLAVE_PSLVERR" } 
+
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[4:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {INT_E} -pin_slices {[7:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {INT_E[7:5]} -value {GND}
+# Add APB_BUS_CONVERTER_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {APB_BUS_CONVERTER} -instance_name {APB_BUS_CONVERTER_0}
+
+
+
+# Add CAPE_DEFAULT_GPIOS instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_DEFAULT_GPIOS} -instance_name {CAPE_DEFAULT_GPIOS}
+
+
+
+# Add CoreAPB3_CAPE_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_CAPE} -instance_name {CoreAPB3_CAPE_0}
+
+
+
+# Add P8_GPIO_UPPER_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {P8_GPIO_UPPER} -instance_name {P8_GPIO_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P8_GPIO_UPPER_0:INT} -pin_slices {[7:0]}
+
+
+
+# Add P9_GPIO_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {P9_GPIO} -instance_name {P9_GPIO_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[15:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[20:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {P9_GPIO_0:INT} -pin_slices {[7:0]}
+
+
+
+# Add PWM_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PWM_0:PWM_1}
+
+
+
+# Add PWM_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_1}
+
+
+
+# Add PWM_2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CAPE_PWM} -instance_name {PWM_2}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_0_PAD" "P8_PIN3_USER_LED_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_11_PAD" "P8_PIN14_USER_LED_11" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_12_PAD" "P8_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_13_PAD" "P8_PIN16" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_14_PAD" "P8_PIN17" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_15_PAD" "P8_PIN18" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_17_PAD" "P8_PIN20" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_18_PAD" "P8_PIN21" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_19_PAD" "P8_PIN22" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_1_PAD" "P8_PIN4_USER_LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_20_PAD" "P8_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_21_PAD" "P8_PIN24" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_22_PAD" "P8_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_23_PAD" "P8_PIN26" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_24_PAD" "P8_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_25_PAD" "P8_PIN28" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_26_PAD" "P8_PIN29" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_27_PAD" "P8_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_2_PAD" "P8_PIN5_USER_LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_3_PAD" "P8_PIN6_USER_LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_4_PAD" "P8_PIN7_USER_LED_4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_5_PAD" "P8_PIN8_USER_LED_5" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_6_PAD" "P8_PIN9_USER_LED_6" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_7_PAD" "P8_PIN10_USER_LED_7" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_8_PAD" "P8_PIN11_USER_LED_8" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_9_PAD" "P8_PIN12_USER_LED_9" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_0_PAD" "P8_PIN31" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_10_PAD" "P8_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_11_PAD" "P8_PIN42" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_12_PAD" "P8_PIN43" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_13_PAD" "P8_PIN44" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_14_PAD" "P8_PIN45" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_15_PAD" "P8_PIN46" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_1_PAD" "P8_PIN32" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_2_PAD" "P8_PIN33" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_3_PAD" "P8_PIN34" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_4_PAD" "P8_PIN35" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_5_PAD" "P8_PIN36" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_8_PAD" "P8_PIN39" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:GPIO_9_PAD" "P8_PIN40" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PCLK" "P9_GPIO_0:PCLK" "PCLK" "PWM_0:PCLK" "PWM_1:PCLK" "PWM_2:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_GPIO_UPPER_0:PRESETN" "P9_GPIO_0:PRESETN" "PRESETN" "PWM_0:PRESETN" "PWM_1:PRESETN" "PWM_2:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN13_USER_LED_10" "PWM_2:PWM_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P8_PIN19" "PWM_2:PWM_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_10_PAD" "P9_PIN23" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_12_PAD" "P9_PIN25" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_14_PAD" "P9_PIN27" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_17_PAD" "P9_PIN30" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_19_PAD" "P9_PIN41" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_1_PAD" "P9_PIN12" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_GPIO_0:GPIO_4_PAD" "P9_PIN15" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN14" "PWM_1:PWM_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN16" "PWM_1:PWM_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"P9_PIN42" "PWM_0:PWM_0" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_IN" "GPIO_IN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OE" "GPIO_OE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CAPE_DEFAULT_GPIOS:GPIO_OUT" "GPIO_OUT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_A" "P8_GPIO_UPPER_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_B" "P8_GPIO_UPPER_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_C" "P9_GPIO_0:INT[7:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_D" "P9_GPIO_0:INT[15:8]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"INT_E[4:0]" "P9_GPIO_0:INT[20:16]" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_MASTER" "CoreAPB3_CAPE_0:APB3mmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_BUS_CONVERTER_0:APB_SLAVE" "APB_SLAVE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave0" "PWM_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave1" "P8_GPIO_UPPER_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave2" "P9_GPIO_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave4" "PWM_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_CAPE_0:APBmslave5" "PWM_2:APBslave" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the SmartDesign 
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign "CAPE"
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_CoreAPB.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_CoreAPB.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1ad50600d0bcc5599be8365b8f73545c9dd63fd5
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_CoreAPB.tcl
@@ -0,0 +1,13 @@
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APBSLOT0ENABLE:true" "APBSLOT1ENABLE:true" "APBSLOT2ENABLE:true" "APBSLOT3ENABLE:false" \
+"APBSLOT4ENABLE:false" "APBSLOT5ENABLE:false" "APBSLOT6ENABLE:false" "APBSLOT7ENABLE:false" \
+"APBSLOT8ENABLE:false" "APBSLOT9ENABLE:false" "APBSLOT10ENABLE:false" "APBSLOT11ENABLE:false" \
+"APBSLOT12ENABLE:false" "APBSLOT13ENABLE:false" "APBSLOT14ENABLE:false" "APBSLOT15ENABLE:false" \
+"APB_DWIDTH:32" \
+"IADDR_OPTION:0" \
+"MADDR_BITS:24" \
+"SC_0:false" "SC_1:false" "SC_2:false" "SC_3:false" "SC_4:false" "SC_5:false" \
+"SC_6:false" "SC_7:false" "SC_8:false" "SC_9:false" "SC_10:false" "SC_11:false" \
+"SC_12:false" "SC_13:false" "SC_14:false" \
+"SC_15:false" \
+"UPR_NIBBLE_POSN:5"}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_DEFAULT_GPIOS.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_DEFAULT_GPIOS.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d9bdbaf41d2b7b05f96bdac5e7b912ac2e87e6ec
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_DEFAULT_GPIOS.tcl
@@ -0,0 +1,249 @@
+# Creating SmartDesign CAPE_DEFAULT_GPIOS
+set sd_name {CAPE_DEFAULT_GPIOS}
+create_smartdesign -sd_name ${sd_name}
+
+
+# Add GPIO BIBUFs
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_6_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_7_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_18_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_20_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_21_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_22_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_23_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_24_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_25_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_26_BIBUF}
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_27_BIBUF}
+
+
+
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OUT} -port_direction {IN} -port_range {[27:0]}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[0:0]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[21:21]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[22:22]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[23:23]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[24:24]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[25:25]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[26:26]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OUT} -pin_slices {"[27:27]"}
+
+
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_OE} -port_direction {IN} -port_range {[27:0]}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[0:0]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[21:21]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[22:22]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[23:23]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[24:24]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[25:25]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[26:26]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_OE} -pin_slices {"[27:27]"}
+
+
+sd_create_bus_port -sd_name {CAPE_DEFAULT_GPIOS} -port_name {GPIO_IN} -port_direction {OUT} -port_range {[27:0]}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[0:0]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[1:1]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[2:2]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[3:3]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[4:4]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[5:5]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[6:6]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[7:7]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[8:8]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[9:9]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[10:10]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[11:11]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[12:12]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[13:13]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[14:14]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[15:15]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[16:16]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[17:17]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[18:18]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[19:19]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[20:20]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[21:21]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[22:22]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[23:23]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[24:24]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[25:25]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[26:26]"}
+sd_create_pin_slices -sd_name {CAPE_DEFAULT_GPIOS} -pin_name {GPIO_IN} -pin_slices {"[27:27]"}
+
+
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:D" "GPIO_OUT[0:0]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:D" "GPIO_OUT[1:1]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:D" "GPIO_OUT[2:2]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:D" "GPIO_OUT[3:3]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:D" "GPIO_OUT[4:4]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:D" "GPIO_OUT[5:5]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:D" "GPIO_OUT[6:6]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:D" "GPIO_OUT[7:7]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:D" "GPIO_OUT[8:8]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:D" "GPIO_OUT[9:9]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:D" "GPIO_OUT[11:11]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:D" "GPIO_OUT[12:12]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:D" "GPIO_OUT[13:13]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:D" "GPIO_OUT[14:14]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:D" "GPIO_OUT[15:15]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:D" "GPIO_OUT[17:17]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:D" "GPIO_OUT[18:18]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:D" "GPIO_OUT[19:19]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_20_BIBUF:D" "GPIO_OUT[20:20]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_21_BIBUF:D" "GPIO_OUT[21:21]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_22_BIBUF:D" "GPIO_OUT[22:22]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:D" "GPIO_OUT[23:23]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:D" "GPIO_OUT[24:24]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:D" "GPIO_OUT[25:25]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:D" "GPIO_OUT[26:26]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:D" "GPIO_OUT[27:27]"}
+
+
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:E" "GPIO_OE[0:0]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:E" "GPIO_OE[1:1]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:E" "GPIO_OE[2:2]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:E" "GPIO_OE[3:3]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:E" "GPIO_OE[4:4]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:E" "GPIO_OE[5:5]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:E" "GPIO_OE[6:6]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:E" "GPIO_OE[7:7]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:E" "GPIO_OE[8:8]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:E" "GPIO_OE[9:9]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:E" "GPIO_OE[11:11]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:E" "GPIO_OE[12:12]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:E" "GPIO_OE[13:13]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:E" "GPIO_OE[14:14]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:E" "GPIO_OE[15:15]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:E" "GPIO_OE[17:17]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:E" "GPIO_OE[18:18]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:E" "GPIO_OE[19:19]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_20_BIBUF:E" "GPIO_OE[20:20]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_21_BIBUF:E" "GPIO_OE[21:21]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_22_BIBUF:E" "GPIO_OE[22:22]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:E" "GPIO_OE[23:23]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:E" "GPIO_OE[24:24]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:E" "GPIO_OE[25:25]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:E" "GPIO_OE[26:26]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:E" "GPIO_OE[27:27]"}
+
+
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_0_BIBUF:Y" "GPIO_IN[0:0]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_1_BIBUF:Y" "GPIO_IN[1:1]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_2_BIBUF:Y" "GPIO_IN[2:2]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_3_BIBUF:Y" "GPIO_IN[3:3]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_4_BIBUF:Y" "GPIO_IN[4:4]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_5_BIBUF:Y" "GPIO_IN[5:5]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_6_BIBUF:Y" "GPIO_IN[6:6]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_7_BIBUF:Y" "GPIO_IN[7:7]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_8_BIBUF:Y" "GPIO_IN[8:8]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_9_BIBUF:Y" "GPIO_IN[9:9]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_11_BIBUF:Y" "GPIO_IN[11:11]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_12_BIBUF:Y" "GPIO_IN[12:12]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_13_BIBUF:Y" "GPIO_IN[13:13]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_14_BIBUF:Y" "GPIO_IN[14:14]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_15_BIBUF:Y" "GPIO_IN[15:15]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_17_BIBUF:Y" "GPIO_IN[17:17]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_18_BIBUF:Y" "GPIO_IN[18:18]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_19_BIBUF:Y" "GPIO_IN[19:19]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_20_BIBUF:Y" "GPIO_IN[20:20]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_21_BIBUF:Y" "GPIO_IN[21:21]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_22_BIBUF:Y" "GPIO_IN[22:22]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_23_BIBUF:Y" "GPIO_IN[23:23]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_24_BIBUF:Y" "GPIO_IN[24:24]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_25_BIBUF:Y" "GPIO_IN[25:25]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_26_BIBUF:Y" "GPIO_IN[26:26]"}
+sd_connect_pins -sd_name {CAPE_DEFAULT_GPIOS} -pin_names {"GPIO_27_BIBUF:Y" "GPIO_IN[27:27]"}
+
+
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD} -new_port_name {GPIO_0_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_0} -new_port_name {GPIO_1_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_1} -new_port_name {GPIO_2_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_2} -new_port_name {GPIO_3_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_3} -new_port_name {GPIO_4_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_4} -new_port_name {GPIO_5_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_5} -new_port_name {GPIO_6_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_6} -new_port_name {GPIO_7_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_7} -new_port_name {GPIO_8_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_8} -new_port_name {GPIO_9_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_9} -new_port_name {GPIO_11_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_10} -new_port_name {GPIO_12_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_11} -new_port_name {GPIO_13_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_12} -new_port_name {GPIO_14_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_13} -new_port_name {GPIO_15_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_14} -new_port_name {GPIO_17_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_15} -new_port_name {GPIO_18_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_16} -new_port_name {GPIO_19_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_17} -new_port_name {GPIO_20_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_18} -new_port_name {GPIO_21_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_19} -new_port_name {GPIO_22_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_20} -new_port_name {GPIO_23_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_21} -new_port_name {GPIO_24_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_22} -new_port_name {GPIO_25_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_23} -new_port_name {GPIO_26_PAD}
+sd_rename_port -sd_name {CAPE_DEFAULT_GPIOS} -current_port_name {PAD_24} -new_port_name {GPIO_27_PAD}
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {GPIO_IN[10:10]} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {GPIO_IN[16:16]} -value {GND}
+
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign CAPE_DEFAULT_GPIOS
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_PWM.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_PWM.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e59a793e700e3bf6b651a30c8b44e610d721aa0a
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CAPE_PWM.tcl
@@ -0,0 +1,61 @@
+# Creating SmartDesign CAPE_PWM
+set sd_name {CAPE_PWM}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APBslave_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PWM_0} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PWM_1} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APBslave_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APBslave} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APBslave_PADDR" \
+"PSELx:APBslave_PSEL" \
+"PENABLE:APBslave_PENABLE" \
+"PWRITE:APBslave_PWRITE" \
+"PRDATA:APBslave_PRDATA" \
+"PWDATA:APBslave_PWDATA" \
+"PREADY:APBslave_PREADY" \
+"PSLVERR:APBslave_PSLVERR" } 
+
+# Add corepwm_C1_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {corepwm_C1} -instance_name {corepwm_C1_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {corepwm_C1_0:PWM} -pin_slices {[1:1]}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCLK" "corepwm_C1_0:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PRESETN" "corepwm_C1_0:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PWM_0" "corepwm_C1_0:PWM[0:0]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PWM_1" "corepwm_C1_0:PWM[1:1]" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APBslave" "corepwm_C1_0:APBslave" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign CAPE_PWM
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreAPB3_CAPE.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreAPB3_CAPE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ab9b81e998527110100572f6008a0373b7ecbfe8
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreAPB3_CAPE.tcl
@@ -0,0 +1,42 @@
+# Exporting Component Description of CoreAPB3_CAPE to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreAPB3_CAPE
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_CAPE} -params {\
+"APB_DWIDTH:32"  \
+"APBSLOT0ENABLE:true"  \
+"APBSLOT1ENABLE:true"  \
+"APBSLOT2ENABLE:true"  \
+"APBSLOT3ENABLE:false"  \
+"APBSLOT4ENABLE:true"  \
+"APBSLOT5ENABLE:true"  \
+"APBSLOT6ENABLE:false"  \
+"APBSLOT7ENABLE:false"  \
+"APBSLOT8ENABLE:false"  \
+"APBSLOT9ENABLE:false"  \
+"APBSLOT10ENABLE:false"  \
+"APBSLOT11ENABLE:false"  \
+"APBSLOT12ENABLE:false"  \
+"APBSLOT13ENABLE:false"  \
+"APBSLOT14ENABLE:false"  \
+"APBSLOT15ENABLE:false"  \
+"IADDR_OPTION:0"  \
+"MADDR_BITS:24"  \
+"SC_0:false"  \
+"SC_1:false"  \
+"SC_2:false"  \
+"SC_3:false"  \
+"SC_4:false"  \
+"SC_5:false"  \
+"SC_6:false"  \
+"SC_7:false"  \
+"SC_8:false"  \
+"SC_9:false"  \
+"SC_10:false"  \
+"SC_11:false"  \
+"SC_12:false"  \
+"SC_13:false"  \
+"SC_14:false"  \
+"SC_15:false"  \
+"UPR_NIBBLE_POSN:5"   }
+# Exporting Component Description of CoreAPB3_CAPE to TCL done
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_LCD.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_LCD.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..564801be4ad80028e63e232592fec2f78fb64134
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_LCD.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_P8_UPPER
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P8_UPPER} -params {\
+"APB_WIDTH:32"  \
+"FIXED_CONFIG_0:true"  \
+"FIXED_CONFIG_1:true"  \
+"FIXED_CONFIG_2:true"  \
+"FIXED_CONFIG_3:true"  \
+"FIXED_CONFIG_4:true"  \
+"FIXED_CONFIG_5:true"  \
+"FIXED_CONFIG_6:true"  \
+"FIXED_CONFIG_7:true"  \
+"FIXED_CONFIG_8:true"  \
+"FIXED_CONFIG_9:true"  \
+"FIXED_CONFIG_10:true"  \
+"FIXED_CONFIG_11:true"  \
+"FIXED_CONFIG_12:true"  \
+"FIXED_CONFIG_13:true"  \
+"FIXED_CONFIG_14:true"  \
+"FIXED_CONFIG_15:true"  \
+"FIXED_CONFIG_16:false"  \
+"FIXED_CONFIG_17:false"  \
+"FIXED_CONFIG_18:false"  \
+"FIXED_CONFIG_19:false"  \
+"FIXED_CONFIG_20:false"  \
+"FIXED_CONFIG_21:false"  \
+"FIXED_CONFIG_22:false"  \
+"FIXED_CONFIG_23:false"  \
+"FIXED_CONFIG_24:false"  \
+"FIXED_CONFIG_25:false"  \
+"FIXED_CONFIG_26:false"  \
+"FIXED_CONFIG_27:false"  \
+"FIXED_CONFIG_28:false"  \
+"FIXED_CONFIG_29:false"  \
+"FIXED_CONFIG_30:false"  \
+"FIXED_CONFIG_31:false"  \
+"INT_BUS:0"  \
+"IO_INT_TYPE_0:7"  \
+"IO_INT_TYPE_1:7"  \
+"IO_INT_TYPE_2:7"  \
+"IO_INT_TYPE_3:7"  \
+"IO_INT_TYPE_4:7"  \
+"IO_INT_TYPE_5:7"  \
+"IO_INT_TYPE_6:7"  \
+"IO_INT_TYPE_7:7"  \
+"IO_INT_TYPE_8:7"  \
+"IO_INT_TYPE_9:7"  \
+"IO_INT_TYPE_10:7"  \
+"IO_INT_TYPE_11:7"  \
+"IO_INT_TYPE_12:7"  \
+"IO_INT_TYPE_13:7"  \
+"IO_INT_TYPE_14:7"  \
+"IO_INT_TYPE_15:7"  \
+"IO_INT_TYPE_16:7"  \
+"IO_INT_TYPE_17:7"  \
+"IO_INT_TYPE_18:7"  \
+"IO_INT_TYPE_19:7"  \
+"IO_INT_TYPE_20:7"  \
+"IO_INT_TYPE_21:7"  \
+"IO_INT_TYPE_22:7"  \
+"IO_INT_TYPE_23:7"  \
+"IO_INT_TYPE_24:7"  \
+"IO_INT_TYPE_25:7"  \
+"IO_INT_TYPE_26:7"  \
+"IO_INT_TYPE_27:7"  \
+"IO_INT_TYPE_28:7"  \
+"IO_INT_TYPE_29:7"  \
+"IO_INT_TYPE_30:7"  \
+"IO_INT_TYPE_31:7"  \
+"IO_NUM:16"  \
+"IO_TYPE_0:2"  \
+"IO_TYPE_1:2"  \
+"IO_TYPE_2:2"  \
+"IO_TYPE_3:2"  \
+"IO_TYPE_4:2"  \
+"IO_TYPE_5:2"  \
+"IO_TYPE_6:2"  \
+"IO_TYPE_7:2"  \
+"IO_TYPE_8:2"  \
+"IO_TYPE_9:2"  \
+"IO_TYPE_10:2"  \
+"IO_TYPE_11:2"  \
+"IO_TYPE_12:2"  \
+"IO_TYPE_13:2"  \
+"IO_TYPE_14:2"  \
+"IO_TYPE_15:2"  \
+"IO_TYPE_16:2"  \
+"IO_TYPE_17:2"  \
+"IO_TYPE_18:2"  \
+"IO_TYPE_19:2"  \
+"IO_TYPE_20:0"  \
+"IO_TYPE_21:0"  \
+"IO_TYPE_22:0"  \
+"IO_TYPE_23:0"  \
+"IO_TYPE_24:0"  \
+"IO_TYPE_25:0"  \
+"IO_TYPE_26:0"  \
+"IO_TYPE_27:0"  \
+"IO_TYPE_28:0"  \
+"IO_TYPE_29:0"  \
+"IO_TYPE_30:0"  \
+"IO_TYPE_31:0"  \
+"IO_VAL_0:0"  \
+"IO_VAL_1:0"  \
+"IO_VAL_2:0"  \
+"IO_VAL_3:0"  \
+"IO_VAL_4:0"  \
+"IO_VAL_5:0"  \
+"IO_VAL_6:0"  \
+"IO_VAL_7:0"  \
+"IO_VAL_8:0"  \
+"IO_VAL_9:0"  \
+"IO_VAL_10:0"  \
+"IO_VAL_11:0"  \
+"IO_VAL_12:0"  \
+"IO_VAL_13:0"  \
+"IO_VAL_14:0"  \
+"IO_VAL_15:0"  \
+"IO_VAL_16:0"  \
+"IO_VAL_17:0"  \
+"IO_VAL_18:0"  \
+"IO_VAL_19:0"  \
+"IO_VAL_20:0"  \
+"IO_VAL_21:0"  \
+"IO_VAL_22:0"  \
+"IO_VAL_23:0"  \
+"IO_VAL_24:0"  \
+"IO_VAL_25:0"  \
+"IO_VAL_26:0"  \
+"IO_VAL_27:0"  \
+"IO_VAL_28:0"  \
+"IO_VAL_29:0"  \
+"IO_VAL_30:0"  \
+"IO_VAL_31:0"  \
+"OE_TYPE:0"   }
+# Exporting Component Description of CoreGPIO_P8_UPPER to TCL done
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_P9.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_P9.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..27820629b0db76af2abc65643fdbdbfadd27a9e7
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/CoreGPIO_P9.tcl
@@ -0,0 +1,138 @@
+# Exporting Component Description of CoreGPIO_P9 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component CoreGPIO_P9
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_P9} -params {\
+"APB_WIDTH:32"  \
+"FIXED_CONFIG_0:true"  \
+"FIXED_CONFIG_1:true"  \
+"FIXED_CONFIG_2:true"  \
+"FIXED_CONFIG_3:true"  \
+"FIXED_CONFIG_4:true"  \
+"FIXED_CONFIG_5:true"  \
+"FIXED_CONFIG_6:true"  \
+"FIXED_CONFIG_7:true"  \
+"FIXED_CONFIG_8:true"  \
+"FIXED_CONFIG_9:true"  \
+"FIXED_CONFIG_10:true"  \
+"FIXED_CONFIG_11:true"  \
+"FIXED_CONFIG_12:true"  \
+"FIXED_CONFIG_13:true"  \
+"FIXED_CONFIG_14:true"  \
+"FIXED_CONFIG_15:true"  \
+"FIXED_CONFIG_16:true"  \
+"FIXED_CONFIG_17:true"  \
+"FIXED_CONFIG_18:true"  \
+"FIXED_CONFIG_19:true"  \
+"FIXED_CONFIG_20:true"  \
+"FIXED_CONFIG_21:false"  \
+"FIXED_CONFIG_22:false"  \
+"FIXED_CONFIG_23:false"  \
+"FIXED_CONFIG_24:false"  \
+"FIXED_CONFIG_25:false"  \
+"FIXED_CONFIG_26:false"  \
+"FIXED_CONFIG_27:false"  \
+"FIXED_CONFIG_28:false"  \
+"FIXED_CONFIG_29:false"  \
+"FIXED_CONFIG_30:false"  \
+"FIXED_CONFIG_31:false"  \
+"INT_BUS:0"  \
+"IO_INT_TYPE_0:7"  \
+"IO_INT_TYPE_1:7"  \
+"IO_INT_TYPE_2:7"  \
+"IO_INT_TYPE_3:7"  \
+"IO_INT_TYPE_4:7"  \
+"IO_INT_TYPE_5:7"  \
+"IO_INT_TYPE_6:7"  \
+"IO_INT_TYPE_7:7"  \
+"IO_INT_TYPE_8:7"  \
+"IO_INT_TYPE_9:7"  \
+"IO_INT_TYPE_10:7"  \
+"IO_INT_TYPE_11:7"  \
+"IO_INT_TYPE_12:7"  \
+"IO_INT_TYPE_13:7"  \
+"IO_INT_TYPE_14:7"  \
+"IO_INT_TYPE_15:7"  \
+"IO_INT_TYPE_16:7"  \
+"IO_INT_TYPE_17:7"  \
+"IO_INT_TYPE_18:7"  \
+"IO_INT_TYPE_19:7"  \
+"IO_INT_TYPE_20:7"  \
+"IO_INT_TYPE_21:7"  \
+"IO_INT_TYPE_22:7"  \
+"IO_INT_TYPE_23:7"  \
+"IO_INT_TYPE_24:7"  \
+"IO_INT_TYPE_25:7"  \
+"IO_INT_TYPE_26:7"  \
+"IO_INT_TYPE_27:7"  \
+"IO_INT_TYPE_28:7"  \
+"IO_INT_TYPE_29:7"  \
+"IO_INT_TYPE_30:7"  \
+"IO_INT_TYPE_31:7"  \
+"IO_NUM:21"  \
+"IO_TYPE_0:2"  \
+"IO_TYPE_1:2"  \
+"IO_TYPE_2:2"  \
+"IO_TYPE_3:2"  \
+"IO_TYPE_4:2"  \
+"IO_TYPE_5:2"  \
+"IO_TYPE_6:2"  \
+"IO_TYPE_7:2"  \
+"IO_TYPE_8:2"  \
+"IO_TYPE_9:2"  \
+"IO_TYPE_10:2"  \
+"IO_TYPE_11:2"  \
+"IO_TYPE_12:2"  \
+"IO_TYPE_13:2"  \
+"IO_TYPE_14:2"  \
+"IO_TYPE_15:2"  \
+"IO_TYPE_16:2"  \
+"IO_TYPE_17:2"  \
+"IO_TYPE_18:2"  \
+"IO_TYPE_19:2"  \
+"IO_TYPE_20:2"  \
+"IO_TYPE_21:0"  \
+"IO_TYPE_22:0"  \
+"IO_TYPE_23:0"  \
+"IO_TYPE_24:0"  \
+"IO_TYPE_25:0"  \
+"IO_TYPE_26:0"  \
+"IO_TYPE_27:0"  \
+"IO_TYPE_28:0"  \
+"IO_TYPE_29:0"  \
+"IO_TYPE_30:0"  \
+"IO_TYPE_31:0"  \
+"IO_VAL_0:0"  \
+"IO_VAL_1:0"  \
+"IO_VAL_2:0"  \
+"IO_VAL_3:0"  \
+"IO_VAL_4:0"  \
+"IO_VAL_5:0"  \
+"IO_VAL_6:0"  \
+"IO_VAL_7:0"  \
+"IO_VAL_8:0"  \
+"IO_VAL_9:0"  \
+"IO_VAL_10:0"  \
+"IO_VAL_11:0"  \
+"IO_VAL_12:0"  \
+"IO_VAL_13:0"  \
+"IO_VAL_14:0"  \
+"IO_VAL_15:0"  \
+"IO_VAL_16:0"  \
+"IO_VAL_17:0"  \
+"IO_VAL_18:0"  \
+"IO_VAL_19:0"  \
+"IO_VAL_20:0"  \
+"IO_VAL_21:0"  \
+"IO_VAL_22:0"  \
+"IO_VAL_23:0"  \
+"IO_VAL_24:0"  \
+"IO_VAL_25:0"  \
+"IO_VAL_26:0"  \
+"IO_VAL_27:0"  \
+"IO_VAL_28:0"  \
+"IO_VAL_29:0"  \
+"IO_VAL_30:0"  \
+"IO_VAL_31:0"  \
+"OE_TYPE:0"   }
+# Exporting Component Description of CoreGPIO_P9 to TCL done
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P8_GPIO_UPPER.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P8_GPIO_UPPER.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c9c6df1f88199d6a9c4e6628c99c21a63c57bdc9
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P8_GPIO_UPPER.tcl
@@ -0,0 +1,252 @@
+# Creating SmartDesign "P8_GPIO_UPPER"
+set sd_name {P8_GPIO_UPPER}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_0_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_11_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_13_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_15_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_2_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_3_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_5_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_8_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_9_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[15:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" } 
+
+# Add CoreGPIO_P8_UPPER_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P8_UPPER} -instance_name {CoreGPIO_P8_UPPER_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_IN} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P8_UPPER_0:GPIO_OE} -pin_slices {[9:9]}
+
+
+
+# Add GPIO_0_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_0_BIBUF}
+
+
+
+# Add GPIO_1_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_2_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_2_BIBUF}
+
+
+
+# Add GPIO_3_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_3_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_5_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_5_BIBUF}
+
+
+
+# Add GPIO_8_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_8_BIBUF}
+
+
+
+# Add GPIO_9_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_9_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_11_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_11_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_13_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_13_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_15_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_15_BIBUF}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[0:0]" "GPIO_0_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[11:11]" "GPIO_11_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[13:13]" "GPIO_13_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[15:15]" "GPIO_15_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[2:2]" "GPIO_2_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[3:3]" "GPIO_3_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[5:5]" "GPIO_5_BIBUF:Y" }
+
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:GPIO_IN[6:6]} -value {GND} 
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P8_UPPER_0:GPIO_IN[7:7]} -value {GND} 
+
+
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[8:8]" "GPIO_8_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_IN[9:9]" "GPIO_9_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[0:0]" "GPIO_0_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[11:11]" "GPIO_11_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[13:13]" "GPIO_13_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[15:15]" "GPIO_15_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[2:2]" "GPIO_2_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[3:3]" "GPIO_3_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[5:5]" "GPIO_5_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[8:8]" "GPIO_8_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OE[9:9]" "GPIO_9_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[0:0]" "GPIO_0_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[11:11]" "GPIO_11_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[13:13]" "GPIO_13_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[15:15]" "GPIO_15_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[2:2]" "GPIO_2_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[3:3]" "GPIO_3_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[5:5]" "GPIO_5_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[8:8]" "GPIO_8_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:GPIO_OUT[9:9]" "GPIO_9_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_0_BIBUF:PAD" "GPIO_0_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_11_BIBUF:PAD" "GPIO_11_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_13_BIBUF:PAD" "GPIO_13_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_15_BIBUF:PAD" "GPIO_15_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_2_BIBUF:PAD" "GPIO_2_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_3_BIBUF:PAD" "GPIO_3_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_5_BIBUF:PAD" "GPIO_5_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_8_BIBUF:PAD" "GPIO_8_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_9_BIBUF:PAD" "GPIO_9_PAD" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P8_UPPER_0:INT" "INT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P8_UPPER_0:APB_bif" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the SmartDesign 
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign "P8_GPIO_UPPER"
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P9_GPIO.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P9_GPIO.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9afedc1e3d4b599d8a4efeb9ca66ff4ffe819b79
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/P9_GPIO.tcl
@@ -0,0 +1,233 @@
+# Creating SmartDesign "P9_GPIO"
+set sd_name {P9_GPIO}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_bif_PSLVERR} -port_direction {OUT}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_10_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_12_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_14_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_17_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_19_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_1_PAD} -port_direction {INOUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_4_PAD} -port_direction {INOUT} -port_is_pad {1}
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PADDR} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PWDATA} -port_direction {IN} -port_range {[31:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_bif_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {INT} -port_direction {OUT} -port_range {[20:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_bif} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_bif_PADDR" \
+"PSELx:APB_bif_PSEL" \
+"PENABLE:APB_bif_PENABLE" \
+"PWRITE:APB_bif_PWRITE" \
+"PRDATA:APB_bif_PRDATA" \
+"PWDATA:APB_bif_PWDATA" \
+"PREADY:APB_bif_PREADY" \
+"PSLVERR:APB_bif_PSLVERR" } 
+
+# Add CoreGPIO_P9_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_P9} -instance_name {CoreGPIO_P9_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[0:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[0:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[11:11]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[11:11]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[13:13]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[13:13]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[15:15]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[15:15]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[16:16]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[16:16]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[18:18]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[18:18]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[20:20]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[20:20]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[2:2]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[2:2]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[3:3]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[3:3]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[5:5]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[5:5]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[6:6]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[6:6]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[7:7]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[7:7]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[8:8]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[8:8]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_IN} -pin_slices {[9:9]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_IN[9:9]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[0:0]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[20:20]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[2:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[3:3]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OUT} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OUT[9:9]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[0:0]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[0:0]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[10:10]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[11:11]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[11:11]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[12:12]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[13:13]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[13:13]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[14:14]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[15:15]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[15:15]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[16:16]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[16:16]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[17:17]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[18:18]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[18:18]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[19:19]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[1:1]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[20:20]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[20:20]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[2:2]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[2:2]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[3:3]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[3:3]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[4:4]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[5:5]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[5:5]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[6:6]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[6:6]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[7:7]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[7:7]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[8:8]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[8:8]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_P9_0:GPIO_OE} -pin_slices {[9:9]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_P9_0:GPIO_OE[9:9]}
+
+
+
+# Add GPIO_1_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_1_BIBUF}
+
+
+
+# Add GPIO_4_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_4_BIBUF}
+
+
+
+# Add GPIO_10_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_10_BIBUF}
+
+
+
+# Add GPIO_12_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_12_BIBUF}
+
+
+
+# Add GPIO_14_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_14_BIBUF}
+
+
+
+# Add GPIO_17_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_17_BIBUF}
+
+
+
+# Add GPIO_19_BIBUF instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO_19_BIBUF}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[10:10]" "GPIO_10_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[12:12]" "GPIO_12_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[14:14]" "GPIO_14_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[17:17]" "GPIO_17_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[19:19]" "GPIO_19_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[1:1]" "GPIO_1_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_IN[4:4]" "GPIO_4_BIBUF:Y" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[10:10]" "GPIO_10_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[12:12]" "GPIO_12_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[14:14]" "GPIO_14_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[17:17]" "GPIO_17_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[19:19]" "GPIO_19_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[1:1]" "GPIO_1_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OE[4:4]" "GPIO_4_BIBUF:E" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[10:10]" "GPIO_10_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[12:12]" "GPIO_12_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[14:14]" "GPIO_14_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[17:17]" "GPIO_17_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[19:19]" "GPIO_19_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[1:1]" "GPIO_1_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:GPIO_OUT[4:4]" "GPIO_4_BIBUF:D" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:PRESETN" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_10_BIBUF:PAD" "GPIO_10_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_12_BIBUF:PAD" "GPIO_12_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_14_BIBUF:PAD" "GPIO_14_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_17_BIBUF:PAD" "GPIO_17_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_19_BIBUF:PAD" "GPIO_19_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_1_BIBUF:PAD" "GPIO_1_PAD" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_4_BIBUF:PAD" "GPIO_4_PAD" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_P9_0:INT" "INT" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_bif" "CoreGPIO_P9_0:APB_bif" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the SmartDesign 
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign "P9_GPIO"
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/Readme.md b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/Readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..cffc44f95caccfb45fe2b0ddd94a770a9fd6f165
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/Readme.md
@@ -0,0 +1,103 @@
+#  Default Cape
+
+## P8 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P8_1   | n/a                        |  n/a  | GND         |
+| P8_2   | n/a                        |  n/a  | GND         |
+| P8_3   | MSS GPIO_2[0]              |   53  | User LED 0  |
+| P8_4   | MSS GPIO_2[1]              |   53  | User LED 1  |
+| P8_5   | MSS GPIO_2[2]              |   53  | User LED 2  |
+| P8_6   | MSS GPIO_2[3]              |   53  | User LED 3  |
+| P8_7   | MSS GPIO_2[4]              |   53  | User LED 4  |
+| P8_8   | MSS GPIO_2[5]              |   53  | User LED 5  |
+| P8_9   | MSS GPIO_2[6]              |   53  | User LED 6  |
+| P8_10  | MSS GPIO_2[7]              |   53  | User LED 7  |
+| P8_11  | MSS GPIO_2[8]              |   53  | User LED 8  |
+| P8_12  | MSS GPIO_2[9]              |   53  | User LED 9  |
+| P8_13  | core_pwm[1] @ 0x41500000   |  n/a  | PWM_2:1     |
+| P8_14  | MSS GPIO_2[11]             |   53  | User LED 11 |
+| P8_15  | MSS GPIO_2[12]             |   53  | GPIO        |
+| P8_16  | MSS GPIO_2[13]             |   53  | GPIO        |
+| P8_17  | MSS GPIO_2[14]             |   53  | GPIO        |
+| P8_18  | MSS GPIO_2[15]             |   53  | GPIO        |
+| P8_19  | core_pwm[0] @ 0x41500000   |  n/a  | PWM_2:0     |
+| P8_20  | MSS GPIO_2[17]             |   53  | GPIO        |
+| P8_21  | MSS GPIO_2[18]             |   53  | GPIO        |
+| P8_22  | MSS GPIO_2[19]             |   53  | GPIO        |
+| P8_23  | MSS GPIO_2[20]             |   53  | GPIO        |
+| P8_24  | MSS GPIO_2[21]             |   53  | GPIO        |
+| P8_25  | MSS GPIO_2[22]             |   53  | GPIO        |
+| P8_26  | MSS GPIO_2[23]             |   53  | GPIO        |
+| P8_27  | MSS GPIO_2[24]             |   53  | GPIO        |
+| P8_28  | MSS GPIO_2[25]             |   53  | GPIO        |
+| P8_29  | MSS GPIO_2[26]             |   53  | GPIO        |
+| P8_30  | MSS GPIO_2[27]             |   53  | GPIO        |
+| P8_31  | core_gpio[0] @ 0x41100000  |  126  | GPIO        |
+| P8_32  | core_gpio[1] @ 0x41100000  |  127  | GPIO        |
+| P8_33  | core_gpio[2] @ 0x41100000  |  128  | GPIO        |
+| P8_34  | core_gpio[3] @ 0x41100000  |  129  | GPIO        |
+| P8_35  | core_gpio[4] @ 0x41100000  |  130  | GPIO        |
+| P8_36  | core_gpio[5] @ 0x41100000  |  131  | GPIO        |
+| P8_37  | MMUART1                    |   91  | UART1 TX    |
+| P8_38  | MMUART1                    |   91  | UART1_RX    |
+| P8_39  | core_gpio[8] @ 0x41100000  |  134  | GPIO        |
+| P8_40  | core_gpio[9] @ 0x41100000  |  135  | GPIO        |
+| P8_41  | core_gpio[10] @ 0x41100000 |  136  | GPIO        |
+| P8_42  | core_gpio[11] @ 0x41100000 |  137  | GPIO        |
+| P8_43  | core_gpio[12] @ 0x41100000 |  138  | GPIO        |
+| P8_44  | core_gpio[13] @ 0x41100000 |  139  | GPIO        |
+| P8_45  | core_gpio[14] @ 0x41100000 |  140  | GPIO        |
+| P8_46  | core_gpio[15] @ 0x41100000 |  141  | GPIO        |
+
+## P9 Header
+
+| Signal | Control                    | Irq # | Description |
+|--------|----------------------------|-------|-------------|
+| P9_1   | n/a                        |  n/a  | GND         |
+| P9_2   | n/a                        |  n/a  | GND         |
+| P9_3   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_4   | n/a                        |  n/a  | VCC 3.3V    |
+| P9_5   | n/a                        |  n/a  | VDD 5V      |
+| P9_6   | n/a                        |  n/a  | VDD 5V      |
+| P9_7   | n/a                        |  n/a  | SYS 5V      |
+| P9_8   | n/a                        |  n/a  | SYS 5V      |
+| P9_9   | n/a                        |  n/a  | NC          |
+| P9_10  | n/a                        |  n/a  | SYS_RSTN    |
+| P9_11  | MMUART4                    |   94  | UART4 RX    |
+| P9_12  | core_gpio[1] @ 0x41200000  |  143  | GPIO        |
+| P9_13  | MMUART4                    |   94  | UART4 TX    |
+| P9_14  | core_pwm[0] @ 0x41400000   |  n/a  | PWM_1:0     |
+| P9_15  | core_gpio[4] @ 0x41200000  |  146  | GPIO        |
+| P9_16  | core_pwm[1] @ 0x41400000   |  n/a  | PWM_1:1     |
+| P9_17  | MSS SPI0                   |   54  | SPI0 CS     |
+| P9_18  | MSS SPI0                   |   54  | SPI0 DI     |
+| P9_19  | MSS I2C0                   |   58  | I2C0 SCL    |
+| P9_20  | MSS I2C0                   |   58  | I2C0 SDA    |
+| P9_21  | MSS SPI0                   |   54  | SPI0 DO     |
+| P9_22  | MSS SPI0                   |   54  | SPI0 SCLK   |
+| P9_23  | core_gpio[10] @ 0x41200000 |  152  | GPIO        |
+| P9_24  | MMUART2                    |   92  | UART1 TX    |
+| P9_25  | core_gpio[12] @ 0x41200000 |  154  | GPIO        |
+| P9_26  | MMUART2                    |   92  | UART2 RX    |
+| P9_27  | core_gpio[14] @ 0x41200000 |  156  | GPIO        |
+| P9_28  | MSS SPI1                   |   55  | SPI1 CS     |
+| P9_29  | MSS SPI1                   |   55  | SPI1 DO     |
+| P9_30  | core_gpio[17] @ 0x41200000 |  159  | GPIO        |
+| P9_31  | MSS SPI1                   |   55  | SPI1 SCLK   |
+| P9_32  | n/a                        |  n/a  | VDD ADC     |
+| P9_33  | n/a                        |  n/a  | ADC input 4 |
+| P9_34  | n/a                        |  n/a  | AGND        |
+| P9_35  | n/a                        |  n/a  | ADC input 6 |
+| P9_36  | n/a                        |  n/a  | ADC input 5 |
+| P9_37  | n/a                        |  n/a  | ADC input 2 |
+| P9_38  | n/a                        |  n/a  | ADC input 3 |
+| P9_39  | n/a                        |  n/a  | ADC input 0 |
+| P9_40  | n/a                        |  n/a  | ADC input 1 |
+| P9_41  | core_gpio[19] @ 0x41200000 |  161  | GPIO        |
+| P9_42  | core_pwm[0] @ 0x41000000   |  n/a  | PWM_0:0     |
+| P9_43  | n/a                        |  n/a  | GND         |
+| P9_44  | n/a                        |  n/a  | GND         |
+| P9_45  | n/a                        |  n/a  | GND         |
+| P9_46  | n/a                        |  n/a  | GND         |
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/constraints/cape.pdc b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/constraints/cape.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..1e78b78dbd30ae6c3f9b06c9c3599b7b59c65454
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/constraints/cape.pdc
@@ -0,0 +1,420 @@
+
+set_io -port_name P9_11	\
+    -pin_name B5	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_PIN12	\
+    -pin_name C5	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_13	\
+    -pin_name D19	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_PIN14	\
+    -pin_name C6	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUT
+
+set_io -port_name P9_PIN15	\
+    -pin_name A5	    \
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_PIN16	\
+    -pin_name A6	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUT
+
+set_io -port_name P9_17	\
+    -pin_name C9	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_18	\
+    -pin_name C10	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INPUT
+
+set_io -port_name P9_21	\
+    -pin_name B8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_22	\
+    -pin_name A8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INPUT
+
+
+set_io -port_name P9_PIN23	\
+    -pin_name C12	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_24	\
+    -pin_name B12	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_PIN25	\
+    -pin_name B7	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_26	\
+    -pin_name A7	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INPUT
+
+set_io -port_name P9_PIN27	\
+    -pin_name D11	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_28	\
+    -pin_name C11	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_29	\
+    -pin_name F17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_PIN30	\
+    -pin_name F16	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_31	\
+    -pin_name E18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUTPUT
+
+set_io -port_name P9_PIN41	\
+    -pin_name E15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P9_PIN42	\
+    -pin_name E14	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUT
+
+#-------------------------------------------------------------------------------
+
+set_io -port_name P8_PIN3_USER_LED_0  \
+    -pin_name V22       \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN4_USER_LED_1  \
+    -pin_name W22        \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN5_USER_LED_2  \
+    -pin_name V19       \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN6_USER_LED_3  \
+    -pin_name V20        \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN7_USER_LED_4  \
+    -pin_name V15        \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN8_USER_LED_5  \
+    -pin_name V14       \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN9_USER_LED_6  \
+    -pin_name V21       \
+    -fixed true         \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN10_USER_LED_7  \
+    -pin_name W21       \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN11_USER_LED_8	\
+    -pin_name Y21	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN12_USER_LED_9	\
+    -pin_name Y20        \
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN13_USER_LED_10	\
+    -pin_name B10	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN14_USER_LED_11  \
+    -pin_name B9	\
+    -io_std LVCMOS33  \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+
+set_io -port_name P8_PIN15  \
+    -pin_name T12       \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN16  \
+    -pin_name U12        \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN17  \
+    -pin_name W13        \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN18  \
+    -pin_name T16       \
+    -fixed true          \
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN19	\
+    -pin_name W18	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN20	\
+    -pin_name R16	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN21	\
+    -pin_name AA21	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN22	\
+    -pin_name AA22	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN23	\
+    -pin_name AB18	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN24	\
+    -pin_name AA18	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN25	\
+    -pin_name V17	\
+    -fixed true	\
+    -OUT_DRIVE 12       \
+    -RES_PULL None      \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN26  \
+    -pin_name A12        \
+    -fixed true          \
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN27	\
+    -pin_name A13	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN28	\
+    -pin_name B14	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN29	\
+    -pin_name B13	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN30	\
+    -pin_name D14	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN31	\
+    -pin_name D13	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN32	\
+    -pin_name B15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN33	\
+    -pin_name A15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN34	\
+    -pin_name C15	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN35	\
+    -pin_name C14	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN36	\
+    -pin_name B4	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_37	\
+    -pin_name C4	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION OUT
+
+set_io -port_name P8_38	\
+    -pin_name C17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION IN
+
+set_io -port_name P8_PIN39	\
+    -pin_name B17	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN40	\
+    -pin_name B18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN41	\
+    -pin_name A18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN42	\
+    -pin_name D6	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN43	\
+    -pin_name D7	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN44	\
+    -pin_name D8	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN45	\
+    -pin_name D9	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+
+set_io -port_name P8_PIN46	\
+    -pin_name D18	\
+    -fixed true	\
+    -io_std LVCMOS33  \
+    -DIRECTION INOUT
+	
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/corepwm_C1.tcl b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/corepwm_C1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0eb4a5100d4aeb9dc728774e2b24026b50fe1c41
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/corepwm_C1.tcl
@@ -0,0 +1,144 @@
+# Exporting Component Description of corepwm_C1 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component corepwm_C1
+create_and_configure_core -core_vlnv {Actel:DirectCore:corepwm:4.5.100} -component_name {corepwm_C1} -params {\
+"APB_DWIDTH:32"  \
+"CONFIG_MODE:0"  \
+"DAC_MODE1:false"  \
+"DAC_MODE2:false"  \
+"DAC_MODE3:false"  \
+"DAC_MODE4:false"  \
+"DAC_MODE5:false"  \
+"DAC_MODE6:false"  \
+"DAC_MODE7:false"  \
+"DAC_MODE8:false"  \
+"DAC_MODE9:false"  \
+"DAC_MODE10:false"  \
+"DAC_MODE11:false"  \
+"DAC_MODE12:false"  \
+"DAC_MODE13:false"  \
+"DAC_MODE14:false"  \
+"DAC_MODE15:false"  \
+"DAC_MODE16:false"  \
+"FIXED_PERIOD:1"  \
+"FIXED_PERIOD_EN:false"  \
+"FIXED_PRESCALE:0"  \
+"FIXED_PRESCALE_EN:false"  \
+"FIXED_PWM_NEG_EN1:false"  \
+"FIXED_PWM_NEG_EN2:false"  \
+"FIXED_PWM_NEG_EN3:false"  \
+"FIXED_PWM_NEG_EN4:false"  \
+"FIXED_PWM_NEG_EN5:false"  \
+"FIXED_PWM_NEG_EN6:false"  \
+"FIXED_PWM_NEG_EN7:false"  \
+"FIXED_PWM_NEG_EN8:false"  \
+"FIXED_PWM_NEG_EN9:false"  \
+"FIXED_PWM_NEG_EN10:false"  \
+"FIXED_PWM_NEG_EN11:false"  \
+"FIXED_PWM_NEG_EN12:false"  \
+"FIXED_PWM_NEG_EN13:false"  \
+"FIXED_PWM_NEG_EN14:false"  \
+"FIXED_PWM_NEG_EN15:false"  \
+"FIXED_PWM_NEG_EN16:false"  \
+"FIXED_PWM_NEGEDGE1:0"  \
+"FIXED_PWM_NEGEDGE2:0"  \
+"FIXED_PWM_NEGEDGE3:0"  \
+"FIXED_PWM_NEGEDGE4:0"  \
+"FIXED_PWM_NEGEDGE5:0"  \
+"FIXED_PWM_NEGEDGE6:0"  \
+"FIXED_PWM_NEGEDGE7:0"  \
+"FIXED_PWM_NEGEDGE8:0"  \
+"FIXED_PWM_NEGEDGE9:0"  \
+"FIXED_PWM_NEGEDGE10:0"  \
+"FIXED_PWM_NEGEDGE11:0"  \
+"FIXED_PWM_NEGEDGE12:0"  \
+"FIXED_PWM_NEGEDGE13:0"  \
+"FIXED_PWM_NEGEDGE14:0"  \
+"FIXED_PWM_NEGEDGE15:0"  \
+"FIXED_PWM_NEGEDGE16:0"  \
+"FIXED_PWM_POS_EN1:false"  \
+"FIXED_PWM_POS_EN2:false"  \
+"FIXED_PWM_POS_EN3:false"  \
+"FIXED_PWM_POS_EN4:false"  \
+"FIXED_PWM_POS_EN5:false"  \
+"FIXED_PWM_POS_EN6:true"  \
+"FIXED_PWM_POS_EN7:true"  \
+"FIXED_PWM_POS_EN8:true"  \
+"FIXED_PWM_POS_EN9:true"  \
+"FIXED_PWM_POS_EN10:true"  \
+"FIXED_PWM_POS_EN11:true"  \
+"FIXED_PWM_POS_EN12:true"  \
+"FIXED_PWM_POS_EN13:true"  \
+"FIXED_PWM_POS_EN14:true"  \
+"FIXED_PWM_POS_EN15:true"  \
+"FIXED_PWM_POS_EN16:true"  \
+"FIXED_PWM_POSEDGE1:0"  \
+"FIXED_PWM_POSEDGE2:0"  \
+"FIXED_PWM_POSEDGE3:0"  \
+"FIXED_PWM_POSEDGE4:0"  \
+"FIXED_PWM_POSEDGE5:0"  \
+"FIXED_PWM_POSEDGE6:0"  \
+"FIXED_PWM_POSEDGE7:0"  \
+"FIXED_PWM_POSEDGE8:0"  \
+"FIXED_PWM_POSEDGE9:0"  \
+"FIXED_PWM_POSEDGE10:0"  \
+"FIXED_PWM_POSEDGE11:0"  \
+"FIXED_PWM_POSEDGE12:0"  \
+"FIXED_PWM_POSEDGE13:0"  \
+"FIXED_PWM_POSEDGE14:0"  \
+"FIXED_PWM_POSEDGE15:0"  \
+"FIXED_PWM_POSEDGE16:0"  \
+"PWM_NUM:2"  \
+"PWM_STRETCH_VALUE1:false"  \
+"PWM_STRETCH_VALUE2:false"  \
+"PWM_STRETCH_VALUE3:false"  \
+"PWM_STRETCH_VALUE4:false"  \
+"PWM_STRETCH_VALUE5:false"  \
+"PWM_STRETCH_VALUE6:false"  \
+"PWM_STRETCH_VALUE7:false"  \
+"PWM_STRETCH_VALUE8:false"  \
+"PWM_STRETCH_VALUE9:false"  \
+"PWM_STRETCH_VALUE10:false"  \
+"PWM_STRETCH_VALUE11:false"  \
+"PWM_STRETCH_VALUE12:false"  \
+"PWM_STRETCH_VALUE13:false"  \
+"PWM_STRETCH_VALUE14:false"  \
+"PWM_STRETCH_VALUE15:false"  \
+"PWM_STRETCH_VALUE16:false"  \
+"SEPARATE_PWM_CLK:false"  \
+"SHADOW_REG_EN1:true"  \
+"SHADOW_REG_EN2:true"  \
+"SHADOW_REG_EN3:false"  \
+"SHADOW_REG_EN4:false"  \
+"SHADOW_REG_EN5:false"  \
+"SHADOW_REG_EN6:false"  \
+"SHADOW_REG_EN7:false"  \
+"SHADOW_REG_EN8:false"  \
+"SHADOW_REG_EN9:false"  \
+"SHADOW_REG_EN10:false"  \
+"SHADOW_REG_EN11:false"  \
+"SHADOW_REG_EN12:false"  \
+"SHADOW_REG_EN13:false"  \
+"SHADOW_REG_EN14:false"  \
+"SHADOW_REG_EN15:false"  \
+"SHADOW_REG_EN16:false"  \
+"TACH_EDGE1:false"  \
+"TACH_EDGE2:false"  \
+"TACH_EDGE3:false"  \
+"TACH_EDGE4:false"  \
+"TACH_EDGE5:false"  \
+"TACH_EDGE6:false"  \
+"TACH_EDGE7:false"  \
+"TACH_EDGE8:false"  \
+"TACH_EDGE9:false"  \
+"TACH_EDGE10:false"  \
+"TACH_EDGE11:false"  \
+"TACH_EDGE12:false"  \
+"TACH_EDGE13:false"  \
+"TACH_EDGE14:false"  \
+"TACH_EDGE15:false"  \
+"TACH_EDGE16:false"  \
+"TACH_NUM:1"  \
+"TACHINT_ACT_LEVEL:false"   }
+# Exporting Component Description of corepwm_C1 to TCL done
diff --git a/sources/FPGA-design/script_support/components/CAPE/4_UARTS/device-tree-overlay/cape-gpios.dtso b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/device-tree-overlay/cape-gpios.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..8bbf061f2c3775a478217bfb06b95a291d4f2556
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/CAPE/4_UARTS/device-tree-overlay/cape-gpios.dtso
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+	overlays {
+		DEFAULT-CAPE-GATEWARE = "GATEWARE_GIT_VERSION";
+	};
+};
+
+&{/} {
+	fabric-bus@40000000 {
+		core_pwm0: pwm@41000000 {
+			compatible = "microchip,corepwm-rtl-v4";
+			reg = <0x0 0x41000000 0x0 0xF0>;
+			microchip,sync-update-mask = /bits/ 32 <0>;
+			#pwm-cells = <3>;
+			clocks = <&fabric_clk3>;
+			status = "okay";
+		};
+
+		cape_gpios_p8: gpio@41100000 {
+			compatible = "microchip,core-gpio";
+			reg = <0x0 0x41100000 0x0 0x1000>;
+			clocks = <&fabric_clk3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios=<16>;
+			status = "okay";
+			gpio-line-names = "P8_31", "P8_32", "P8_33", "P8_34",
+			                  "P8_35", "P8_36", "P8_37", "P8_38",
+			                  "P8_39", "P8_40", "P8_41", "P8_42",
+			                  "P8_43", "P8_44", "P8_45", "P8_46";
+		};
+
+		cape_gpios_p9: gpio@41200000 {
+			compatible = "microchip,core-gpio";
+			reg = <0x0 0x41200000 0x0 0x1000>;
+			clocks = <&fabric_clk3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios=<21>;
+			status = "okay";
+			gpio-line-names = "", "P9_12", "", "", "P9_15",
+			                  "", "", "", "", "",
+			                  "P9_23", "", "P9_25", "", "P9_27",
+			                  "", "", "P9_30", "", "P9_41",
+			                  "";
+		};
+
+		bone_pwm_1: pwm@41400000 {
+			compatible = "microchip,corepwm-rtl-v4";
+			reg = <0x0 0x41400000 0x0 0xF0>;
+			microchip,sync-update-mask = /bits/ 32 <0>;
+			#pwm-cells = <3>;
+            status = "okay";
+			clocks = <&fabric_clk3>;
+		};
+
+		bone_pwm_2: pwm@41500000 {
+			compatible = "microchip,corepwm-rtl-v4";
+			reg = <0x0 0x41500000 0x0 0xF0>;
+			microchip,sync-update-mask = /bits/ 32 <0>;
+			#pwm-cells = <3>;
+            status = "okay";
+			clocks = <&fabric_clk3>;
+		};
+	};
+};
+
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
+	gpio-line-names = "P8_3_USER_LED_0", "P8_4_USER_LED_1", "P8_5_USER_LED_2",
+					"P8_6_USER_LED_3", "P8_7_USER_LED_4", "P8_8_USER_LED_5",
+					"P8_9_USER_LED_6", "P8_10_USER_LED_7", "P8_11_USER_LED_8",
+					"P8_12_USER_LED_9", "", "P8_14_USER_LED_11",
+					"P8_15", "P8_16", "P8_17", "P8_18", "",
+					"P8_20", "P8_21", "P8_22",	"P8_23", "P8_24",
+					"P8_25", "P8_26", "P8_27", "P8_28", "P8_29",
+					"P8_30",
+					"M2_W_DISABLE1", "M2_W_DISABLE2",
+					"VIO_ENABLE", "SD_DET";
+	status = "okay";
+
+	vio_enable {
+		gpio-hog;
+		gpios = <30 30>;
+		output-high;
+		line-name = "VIO_ENABLE";
+	};
+
+	sd_det {
+		gpio-hog;
+		gpios = <31 31>;
+		input;
+		line-name = "SD_DET";
+	};
+};
+
+&mmuart1 {
+	status = "okay";
+	symlink = "bone/uart/5";
+};
+
+&mmuart2 {
+	status = "okay";
+	symlink = "bone/uart/1";
+};
+
+&mmuart3 {
+	status = "okay";
+	symlink = "bone/uart/2";
+};
+
+&mmuart4 {
+	status = "okay";
+	symlink = "bone/uart/4";
+};
+
+&spi0 {
+	status = "okay";
+	symlink = "bone/spi/0";
+};
+
+&spi1 {
+	status = "okay";
+	symlink = "bone/spi/1";
+};
diff --git a/sources/FPGA-design/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl b/sources/FPGA-design/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
index 76aaeccefaf55c4a323906df26bf1aa35b9a93ba..cc7e9fe738a5c31ee5976d8ef5ab5f7c2a4b6748 100644
--- a/sources/FPGA-design/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
+++ b/sources/FPGA-design/script_support/components/M2/DEFAULT/PF_PCIE_C0.tcl
@@ -15,7 +15,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:*} -component_name {P
 "UI_PCIE_0_BAR_MODE:Custom"  \
 "UI_PCIE_0_CDR_REF_CLK_NUMBER:1"  \
 "UI_PCIE_0_CDR_REF_CLK_SOURCE:Dedicated"  \
-"UI_PCIE_0_CLASS_CODE:0x0604"  \
+"UI_PCIE_0_CLASS_CODE:0x000604"  \
 "UI_PCIE_0_CONTROLLER_ENABLED:Enabled"  \
 "UI_PCIE_0_DE_EMPHASIS:-3.5 dB"  \
 "UI_PCIE_0_DEVICE_ID:0x1556"  \
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/ADD_M2_INTERFACE.tcl b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/ADD_M2_INTERFACE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d6474c4b02c2fc0e5ee489941ef63d6c4a0ed941
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/ADD_M2_INTERFACE.tcl
@@ -0,0 +1,52 @@
+puts "======== Add M.2 option: PCIE_ONLY ========"
+
+
+source script_support/components/M2/PCIE_ONLY/PCIE_INITIATOR.tcl 
+source script_support/components/M2/PCIE_ONLY/PF_PCIE_C0.tcl 
+source script_support/components/FIC_1_INITIATOR.tcl 
+source script_support/components/M2/PCIE_ONLY/M2_INTERFACE.tcl
+
+#-------------------------------------------------------------------------------
+# Modify the CLOCKS_AND_RESET block to add the required PCIe clocks generation.
+#-------------------------------------------------------------------------------
+
+source script_support/components/CLOCKS_AND_RESETS/ADD_PCIE_CLOCKS_AND_RESETS.tcl 
+sd_update_instance -sd_name ${top_level_name} -instance_name {CLOCKS_AND_RESETS}
+
+#-------------------------------------------------------------------------------
+# Create the M.2 interface block.
+# This block will be stiched up to the rest of the design in the calling script.
+#-------------------------------------------------------------------------------
+
+set sd_name ${top_level_name}
+
+#-------------------------------------------------------------------------------
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
+
+#-------------------------------------------------------------------------------
+
+sd_instantiate_component -sd_name ${sd_name} -component_name {M2_INTERFACE} -instance_name {M2_INTERFACE_0} 
+
+#-------------------------------------------------------------------------------
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_1_ACLK" "M2_INTERFACE_0:ACLK"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_TARGET" "M2_INTERFACE_0:AXI4_INITIATOR"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:FIC_1_AXI4_INITIATOR" "M2_INTERFACE_0:AXI_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"BVF_RISCV_SUBSYSTEM:M2_APB_MTARGET" "M2_INTERFACE_0:APB_TARGET"}
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:CLKS_TO_XCVR" "M2_INTERFACE_0:CLKS_FROM_TXPLL_TO_PCIE_0"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_PCLK" "M2_INTERFACE_0:PCLK"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_3_FABRIC_RESET_N" "M2_INTERFACE_0:PRESETN"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:FIC_1_FABRIC_RESET_N" "M2_INTERFACE_0:ARESETN"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:PCIe_REFERENCE_CLK" "M2_INTERFACE_0:PCIE_REF_CLK"} 
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:PCIe_CLK_125MHz" "M2_INTERFACE_0:PCIE_0_TL_CLK_125MHz"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS:PCIE_INIT_DONE" "M2_INTERFACE_0:PCIE_INIT_DONE"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:PCIE_INTERRUPT" "BVF_RISCV_SUBSYSTEM:PCIE_INT"} 
+
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_INTERFACE_0:M2_PERST0n" "M2_PERST0n"}
+
+sd_rename_port -sd_name ${sd_name} -current_port_name {PCIESS_LANE_RXD0_N} -new_port_name {M2_PER0_N}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PCIESS_LANE_RXD0_P} -new_port_name {M2_PER0_P}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PCIESS_LANE_TXD0_N} -new_port_name {M2_PET0_N}
+sd_rename_port -sd_name ${sd_name} -current_port_name {PCIESS_LANE_TXD0_P} -new_port_name {M2_PET0_P}
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/M2_INTERFACE.tcl b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/M2_INTERFACE.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7f43c3ba463a564fa4a873240441fdb3610c84a1
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/M2_INTERFACE.tcl
@@ -0,0 +1,294 @@
+# Creating SmartDesign M2_INTERFACE
+set sd_name {M2_INTERFACE}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Scalar Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {ACLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PENABLE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSEL} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PWRITE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {ARESETN} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARREADY} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWREADY} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_BVALID} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RLAST} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RVALID} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WREADY} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARVALID} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWVALID} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_BREADY} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RREADY} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WLAST} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WVALID} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_BIT_CLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_PLL_LOCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_PLL_REF_CLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_N} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_P} -port_direction {IN} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_0_TL_CLK_125MHz} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_INIT_DONE} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_REF_CLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_TARGET_PSLVERR} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARVALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWVALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_BREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WLAST} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WVALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_BVALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RLAST} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RVALID} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WREADY} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {M2_PERST0n} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_N} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_P} -port_direction {OUT} -port_is_pad {1}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_INTERRUPT} -port_direction {OUT}
+
+
+# Create top level Bus Ports
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PADDR} -port_direction {IN} -port_range {[25:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PWDATA} -port_direction {IN} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_BID} -port_direction {IN} -port_range {[4:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_BRESP} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_BUSER} -port_direction {IN} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RDATA} -port_direction {IN} -port_range {[63:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RID} -port_direction {IN} -port_range {[4:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RRESP} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_RUSER} -port_direction {IN} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARADDR} -port_direction {IN} -port_range {[37:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARBURST} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARCACHE} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARID} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARLEN} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARLOCK} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARPROT} -port_direction {IN} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARQOS} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARREGION} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARSIZE} -port_direction {IN} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_ARUSER} -port_direction {IN} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWADDR} -port_direction {IN} -port_range {[37:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWBURST} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWCACHE} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWID} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWLEN} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWLOCK} -port_direction {IN} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWPROT} -port_direction {IN} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWQOS} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWREGION} -port_direction {IN} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWSIZE} -port_direction {IN} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_AWUSER} -port_direction {IN} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WDATA} -port_direction {IN} -port_range {[63:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WSTRB} -port_direction {IN} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_WUSER} -port_direction {IN} -port_range {[0:0]}
+
+sd_create_bus_port -sd_name ${sd_name} -port_name {APB_TARGET_PRDATA} -port_direction {OUT} -port_range {[31:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARADDR} -port_direction {OUT} -port_range {[37:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARBURST} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARID} -port_direction {OUT} -port_range {[4:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARLEN} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARPROT} -port_direction {OUT} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARQOS} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARREGION} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_ARUSER} -port_direction {OUT} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWADDR} -port_direction {OUT} -port_range {[37:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWBURST} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWID} -port_direction {OUT} -port_range {[4:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWLEN} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWPROT} -port_direction {OUT} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWQOS} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWREGION} -port_direction {OUT} -port_range {[3:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_AWUSER} -port_direction {OUT} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WDATA} -port_direction {OUT} -port_range {[63:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WSTRB} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR_SLAVE0_WUSER} -port_direction {OUT} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_BID} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_BRESP} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_BUSER} -port_direction {OUT} -port_range {[0:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RDATA} -port_direction {OUT} -port_range {[63:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RID} -port_direction {OUT} -port_range {[7:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RRESP} -port_direction {OUT} -port_range {[1:0]}
+sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_TARGET_MASTER0_RUSER} -port_direction {OUT} -port_range {[0:0]}
+
+
+# Create top level Bus interface Ports
+sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4_INITIATOR} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
+"AWID:AXI4_INITIATOR_SLAVE0_AWID" \
+"AWADDR:AXI4_INITIATOR_SLAVE0_AWADDR" \
+"AWLEN:AXI4_INITIATOR_SLAVE0_AWLEN" \
+"AWSIZE:AXI4_INITIATOR_SLAVE0_AWSIZE" \
+"AWBURST:AXI4_INITIATOR_SLAVE0_AWBURST" \
+"AWLOCK:AXI4_INITIATOR_SLAVE0_AWLOCK" \
+"AWCACHE:AXI4_INITIATOR_SLAVE0_AWCACHE" \
+"AWPROT:AXI4_INITIATOR_SLAVE0_AWPROT" \
+"AWQOS:AXI4_INITIATOR_SLAVE0_AWQOS" \
+"AWREGION:AXI4_INITIATOR_SLAVE0_AWREGION" \
+"AWVALID:AXI4_INITIATOR_SLAVE0_AWVALID" \
+"AWREADY:AXI4_INITIATOR_SLAVE0_AWREADY" \
+"WDATA:AXI4_INITIATOR_SLAVE0_WDATA" \
+"WSTRB:AXI4_INITIATOR_SLAVE0_WSTRB" \
+"WLAST:AXI4_INITIATOR_SLAVE0_WLAST" \
+"WVALID:AXI4_INITIATOR_SLAVE0_WVALID" \
+"WREADY:AXI4_INITIATOR_SLAVE0_WREADY" \
+"BID:AXI4_INITIATOR_SLAVE0_BID" \
+"BRESP:AXI4_INITIATOR_SLAVE0_BRESP" \
+"BVALID:AXI4_INITIATOR_SLAVE0_BVALID" \
+"BREADY:AXI4_INITIATOR_SLAVE0_BREADY" \
+"ARID:AXI4_INITIATOR_SLAVE0_ARID" \
+"ARADDR:AXI4_INITIATOR_SLAVE0_ARADDR" \
+"ARLEN:AXI4_INITIATOR_SLAVE0_ARLEN" \
+"ARSIZE:AXI4_INITIATOR_SLAVE0_ARSIZE" \
+"ARBURST:AXI4_INITIATOR_SLAVE0_ARBURST" \
+"ARLOCK:AXI4_INITIATOR_SLAVE0_ARLOCK" \
+"ARCACHE:AXI4_INITIATOR_SLAVE0_ARCACHE" \
+"ARPROT:AXI4_INITIATOR_SLAVE0_ARPROT" \
+"ARQOS:AXI4_INITIATOR_SLAVE0_ARQOS" \
+"ARREGION:AXI4_INITIATOR_SLAVE0_ARREGION" \
+"ARVALID:AXI4_INITIATOR_SLAVE0_ARVALID" \
+"ARREADY:AXI4_INITIATOR_SLAVE0_ARREADY" \
+"RID:AXI4_INITIATOR_SLAVE0_RID" \
+"RDATA:AXI4_INITIATOR_SLAVE0_RDATA" \
+"RRESP:AXI4_INITIATOR_SLAVE0_RRESP" \
+"RLAST:AXI4_INITIATOR_SLAVE0_RLAST" \
+"RVALID:AXI4_INITIATOR_SLAVE0_RVALID" \
+"RREADY:AXI4_INITIATOR_SLAVE0_RREADY" \
+"AWUSER:AXI4_INITIATOR_SLAVE0_AWUSER" \
+"WUSER:AXI4_INITIATOR_SLAVE0_WUSER" \
+"BUSER:AXI4_INITIATOR_SLAVE0_BUSER" \
+"ARUSER:AXI4_INITIATOR_SLAVE0_ARUSER" \
+"RUSER:AXI4_INITIATOR_SLAVE0_RUSER" } 
+
+sd_create_bif_port -sd_name ${sd_name} -port_name {AXI_TARGET} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredMaster} -port_bif_mapping {\
+"AWID:AXI_TARGET_MASTER0_AWID" \
+"AWADDR:AXI_TARGET_MASTER0_AWADDR" \
+"AWLEN:AXI_TARGET_MASTER0_AWLEN" \
+"AWSIZE:AXI_TARGET_MASTER0_AWSIZE" \
+"AWBURST:AXI_TARGET_MASTER0_AWBURST" \
+"AWLOCK:AXI_TARGET_MASTER0_AWLOCK" \
+"AWCACHE:AXI_TARGET_MASTER0_AWCACHE" \
+"AWPROT:AXI_TARGET_MASTER0_AWPROT" \
+"AWQOS:AXI_TARGET_MASTER0_AWQOS" \
+"AWREGION:AXI_TARGET_MASTER0_AWREGION" \
+"AWVALID:AXI_TARGET_MASTER0_AWVALID" \
+"AWREADY:AXI_TARGET_MASTER0_AWREADY" \
+"WDATA:AXI_TARGET_MASTER0_WDATA" \
+"WSTRB:AXI_TARGET_MASTER0_WSTRB" \
+"WLAST:AXI_TARGET_MASTER0_WLAST" \
+"WVALID:AXI_TARGET_MASTER0_WVALID" \
+"WREADY:AXI_TARGET_MASTER0_WREADY" \
+"BID:AXI_TARGET_MASTER0_BID" \
+"BRESP:AXI_TARGET_MASTER0_BRESP" \
+"BVALID:AXI_TARGET_MASTER0_BVALID" \
+"BREADY:AXI_TARGET_MASTER0_BREADY" \
+"ARID:AXI_TARGET_MASTER0_ARID" \
+"ARADDR:AXI_TARGET_MASTER0_ARADDR" \
+"ARLEN:AXI_TARGET_MASTER0_ARLEN" \
+"ARSIZE:AXI_TARGET_MASTER0_ARSIZE" \
+"ARBURST:AXI_TARGET_MASTER0_ARBURST" \
+"ARLOCK:AXI_TARGET_MASTER0_ARLOCK" \
+"ARCACHE:AXI_TARGET_MASTER0_ARCACHE" \
+"ARPROT:AXI_TARGET_MASTER0_ARPROT" \
+"ARQOS:AXI_TARGET_MASTER0_ARQOS" \
+"ARREGION:AXI_TARGET_MASTER0_ARREGION" \
+"ARVALID:AXI_TARGET_MASTER0_ARVALID" \
+"ARREADY:AXI_TARGET_MASTER0_ARREADY" \
+"RID:AXI_TARGET_MASTER0_RID" \
+"RDATA:AXI_TARGET_MASTER0_RDATA" \
+"RRESP:AXI_TARGET_MASTER0_RRESP" \
+"RLAST:AXI_TARGET_MASTER0_RLAST" \
+"RVALID:AXI_TARGET_MASTER0_RVALID" \
+"RREADY:AXI_TARGET_MASTER0_RREADY" \
+"AWUSER:AXI_TARGET_MASTER0_AWUSER" \
+"WUSER:AXI_TARGET_MASTER0_WUSER" \
+"BUSER:AXI_TARGET_MASTER0_BUSER" \
+"ARUSER:AXI_TARGET_MASTER0_ARUSER" \
+"RUSER:AXI_TARGET_MASTER0_RUSER" } 
+
+sd_create_bif_port -sd_name ${sd_name} -port_name {APB_TARGET} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
+"PADDR:APB_TARGET_PADDR" \
+"PSELx:APB_TARGET_PSEL" \
+"PENABLE:APB_TARGET_PENABLE" \
+"PWRITE:APB_TARGET_PWRITE" \
+"PRDATA:APB_TARGET_PRDATA" \
+"PWDATA:APB_TARGET_PWDATA" \
+"PREADY:APB_TARGET_PREADY" \
+"PSLVERR:APB_TARGET_PSLVERR" } 
+
+sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TO_PCIE_0} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {slave} -port_bif_mapping {\
+"LOCK:CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_PLL_LOCK" \
+"BIT_CLK:CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_BIT_CLK" \
+"REF_CLK_TO_LANE:CLKS_FROM_TXPLL_TO_PCIE_0_PCIE_0_TX_PLL_REF_CLK" } 
+
+# Add AXI_ADDRESS_SHIM_0 instance
+sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI_ADDRESS_SHIM} -instance_name {AXI_ADDRESS_SHIM_0}
+
+
+
+# Add FIC1_INITIATOR instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {FIC_1_INITIATOR} -instance_name {FIC1_INITIATOR}
+
+
+
+# Add PCIE instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PF_PCIE_C0} -instance_name {PCIE}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_INTERRUPT} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_M_RDERR} -value {GND}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_S_WDERR} -value {GND}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_LTSSM}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_M_WDERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_S_RDERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_HOT_RST_EXIT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIE:PCIE_0_DLUP_EXIT}
+
+
+
+# Add PCIE_INITIATOR instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {PCIE_INITIATOR} -instance_name {PCIE_INITIATOR}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"ACLK" "FIC1_INITIATOR:ACLK" "PCIE:AXI_CLK" "PCIE_INITIATOR:ACLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN" "AXI_ADDRESS_SHIM_0:RESETN" "FIC1_INITIATOR:ARESETN" "PCIE:AXI_CLK_STABLE" "PCIE_INITIATOR:ARESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"M2_PERST0n" "PCIE:PCIE_0_PERST_OUT_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:APB_S_PCLK" "PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:APB_S_PRESET_N" "PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:INIT_DONE" "PCIE_INIT_DONE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE0_CDR_REF_CLK_0" "PCIE_REF_CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE_RXD0_N" "PCIESS_LANE_RXD0_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE_RXD0_P" "PCIESS_LANE_RXD0_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE_TXD0_N" "PCIESS_LANE_TXD0_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIESS_LANE_TXD0_P" "PCIESS_LANE_TXD0_P" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIE_0_INTERRUPT_OUT" "PCIE_INTERRUPT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE:PCIE_0_TL_CLK_125MHz" "PCIE_0_TL_CLK_125MHz" }
+
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_TARGET" "PCIE:PCIE_APB_SLAVE" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4_INITIATOR" "PCIE_INITIATOR:AXI4mslave0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_ADDRESS_SHIM_0:AXI4_INITIATOR" "PCIE_INITIATOR:AXI4mmaster0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_ADDRESS_SHIM_0:AXI4_TARGET" "PCIE:AXI_0_MASTER" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_TARGET" "FIC1_INITIATOR:AXI4mmaster0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_FROM_TXPLL_TO_PCIE_0" "PCIE:CLKS_FROM_TXPLL_TO_PCIE_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"FIC1_INITIATOR:AXI4mslave0" "PCIE:AXI_0_SLAVE" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign M2_INTERFACE
+generate_component -component_name ${sd_name}
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PCIE_INITIATOR.tcl b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PCIE_INITIATOR.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..da4cbeb524cd8195d912b8abfde600165d10e489
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PCIE_INITIATOR.tcl
@@ -0,0 +1,1461 @@
+# Exporting Component Description of PCIE_INITIATOR to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS250T_ES-FCVG484E
+# Create and Configure the core component PCIE_INITIATOR
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -component_name {PCIE_INITIATOR} -params {\
+"ADDR_WIDTH:38"  \
+"CROSSBAR_MODE:0"  \
+"DATA_WIDTH:64"  \
+"DWC_ADDR_FIFO_DEPTH_CEILING:64"  \
+"ID_WIDTH:4"  \
+"MASTER0_CHAN_RS:true"  \
+"MASTER0_CLOCK_DOMAIN_CROSSING:false"  \
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+"MASTER13_CLOCK_DOMAIN_CROSSING:false"  \
+"MASTER13_DATA_WIDTH:64"  \
+"MASTER13_DWC_DATA_FIFO_DEPTH:16"  \
+"MASTER13_READ_INTERLEAVE:false"  \
+"MASTER13_READ_SLAVE0:true"  \
+"MASTER13_READ_SLAVE1:true"  \
+"MASTER13_READ_SLAVE2:true"  \
+"MASTER13_READ_SLAVE3:true"  \
+"MASTER13_READ_SLAVE4:true"  \
+"MASTER13_READ_SLAVE5:true"  \
+"MASTER13_READ_SLAVE6:true"  \
+"MASTER13_READ_SLAVE7:true"  \
+"MASTER13_READ_SLAVE8:true"  \
+"MASTER13_READ_SLAVE9:true"  \
+"MASTER13_READ_SLAVE10:true"  \
+"MASTER13_READ_SLAVE11:true"  \
+"MASTER13_READ_SLAVE12:true"  \
+"MASTER13_READ_SLAVE13:true"  \
+"MASTER13_READ_SLAVE14:true"  \
+"MASTER13_READ_SLAVE15:true"  \
+"MASTER13_READ_SLAVE16:true"  \
+"MASTER13_READ_SLAVE17:true"  \
+"MASTER13_READ_SLAVE18:true"  \
+"MASTER13_READ_SLAVE19:true"  \
+"MASTER13_READ_SLAVE20:true"  \
+"MASTER13_READ_SLAVE21:true"  \
+"MASTER13_READ_SLAVE22:true"  \
+"MASTER13_READ_SLAVE23:true"  \
+"MASTER13_READ_SLAVE24:true"  \
+"MASTER13_READ_SLAVE25:true"  \
+"MASTER13_READ_SLAVE26:true"  \
+"MASTER13_READ_SLAVE27:true"  \
+"MASTER13_READ_SLAVE28:true"  \
+"MASTER13_READ_SLAVE29:true"  \
+"MASTER13_READ_SLAVE30:true"  \
+"MASTER13_READ_SLAVE31:true"  \
+"MASTER13_TYPE:0"  \
+"MASTER13_WRITE_SLAVE0:true"  \
+"MASTER13_WRITE_SLAVE1:true"  \
+"MASTER13_WRITE_SLAVE2:true"  \
+"MASTER13_WRITE_SLAVE3:true"  \
+"MASTER13_WRITE_SLAVE4:true"  \
+"MASTER13_WRITE_SLAVE5:true"  \
+"MASTER13_WRITE_SLAVE6:true"  \
+"MASTER13_WRITE_SLAVE7:true"  \
+"MASTER13_WRITE_SLAVE8:true"  \
+"MASTER13_WRITE_SLAVE9:true"  \
+"MASTER13_WRITE_SLAVE10:true"  \
+"MASTER13_WRITE_SLAVE11:true"  \
+"MASTER13_WRITE_SLAVE12:true"  \
+"MASTER13_WRITE_SLAVE13:true"  \
+"MASTER13_WRITE_SLAVE14:true"  \
+"MASTER13_WRITE_SLAVE15:true"  \
+"MASTER13_WRITE_SLAVE16:true"  \
+"MASTER13_WRITE_SLAVE17:true"  \
+"MASTER13_WRITE_SLAVE18:true"  \
+"MASTER13_WRITE_SLAVE19:true"  \
+"MASTER13_WRITE_SLAVE20:true"  \
+"MASTER13_WRITE_SLAVE21:true"  \
+"MASTER13_WRITE_SLAVE22:true"  \
+"MASTER13_WRITE_SLAVE23:true"  \
+"MASTER13_WRITE_SLAVE24:true"  \
+"MASTER13_WRITE_SLAVE25:true"  \
+"MASTER13_WRITE_SLAVE26:true"  \
+"MASTER13_WRITE_SLAVE27:true"  \
+"MASTER13_WRITE_SLAVE28:true"  \
+"MASTER13_WRITE_SLAVE29:true"  \
+"MASTER13_WRITE_SLAVE30:true"  \
+"MASTER13_WRITE_SLAVE31:true"  \
+"MASTER14_CHAN_RS:true"  \
+"MASTER14_CLOCK_DOMAIN_CROSSING:false"  \
+"MASTER14_DATA_WIDTH:64"  \
+"MASTER14_DWC_DATA_FIFO_DEPTH:16"  \
+"MASTER14_READ_INTERLEAVE:false"  \
+"MASTER14_READ_SLAVE0:true"  \
+"MASTER14_READ_SLAVE1:true"  \
+"MASTER14_READ_SLAVE2:true"  \
+"MASTER14_READ_SLAVE3:true"  \
+"MASTER14_READ_SLAVE4:true"  \
+"MASTER14_READ_SLAVE5:true"  \
+"MASTER14_READ_SLAVE6:true"  \
+"MASTER14_READ_SLAVE7:true"  \
+"MASTER14_READ_SLAVE8:true"  \
+"MASTER14_READ_SLAVE9:true"  \
+"MASTER14_READ_SLAVE10:true"  \
+"MASTER14_READ_SLAVE11:true"  \
+"MASTER14_READ_SLAVE12:true"  \
+"MASTER14_READ_SLAVE13:true"  \
+"MASTER14_READ_SLAVE14:true"  \
+"MASTER14_READ_SLAVE15:true"  \
+"MASTER14_READ_SLAVE16:true"  \
+"MASTER14_READ_SLAVE17:true"  \
+"MASTER14_READ_SLAVE18:true"  \
+"MASTER14_READ_SLAVE19:true"  \
+"MASTER14_READ_SLAVE20:true"  \
+"MASTER14_READ_SLAVE21:true"  \
+"MASTER14_READ_SLAVE22:true"  \
+"MASTER14_READ_SLAVE23:true"  \
+"MASTER14_READ_SLAVE24:true"  \
+"MASTER14_READ_SLAVE25:true"  \
+"MASTER14_READ_SLAVE26:true"  \
+"MASTER14_READ_SLAVE27:true"  \
+"MASTER14_READ_SLAVE28:true"  \
+"MASTER14_READ_SLAVE29:true"  \
+"MASTER14_READ_SLAVE30:true"  \
+"MASTER14_READ_SLAVE31:true"  \
+"MASTER14_TYPE:0"  \
+"MASTER14_WRITE_SLAVE0:true"  \
+"MASTER14_WRITE_SLAVE1:true"  \
+"MASTER14_WRITE_SLAVE2:true"  \
+"MASTER14_WRITE_SLAVE3:true"  \
+"MASTER14_WRITE_SLAVE4:true"  \
+"MASTER14_WRITE_SLAVE5:true"  \
+"MASTER14_WRITE_SLAVE6:true"  \
+"MASTER14_WRITE_SLAVE7:true"  \
+"MASTER14_WRITE_SLAVE8:true"  \
+"MASTER14_WRITE_SLAVE9:true"  \
+"MASTER14_WRITE_SLAVE10:true"  \
+"MASTER14_WRITE_SLAVE11:true"  \
+"MASTER14_WRITE_SLAVE12:true"  \
+"MASTER14_WRITE_SLAVE13:true"  \
+"MASTER14_WRITE_SLAVE14:true"  \
+"MASTER14_WRITE_SLAVE15:true"  \
+"MASTER14_WRITE_SLAVE16:true"  \
+"MASTER14_WRITE_SLAVE17:true"  \
+"MASTER14_WRITE_SLAVE18:true"  \
+"MASTER14_WRITE_SLAVE19:true"  \
+"MASTER14_WRITE_SLAVE20:true"  \
+"MASTER14_WRITE_SLAVE21:true"  \
+"MASTER14_WRITE_SLAVE22:true"  \
+"MASTER14_WRITE_SLAVE23:true"  \
+"MASTER14_WRITE_SLAVE24:true"  \
+"MASTER14_WRITE_SLAVE25:true"  \
+"MASTER14_WRITE_SLAVE26:true"  \
+"MASTER14_WRITE_SLAVE27:true"  \
+"MASTER14_WRITE_SLAVE28:true"  \
+"MASTER14_WRITE_SLAVE29:true"  \
+"MASTER14_WRITE_SLAVE30:true"  \
+"MASTER14_WRITE_SLAVE31:true"  \
+"MASTER15_CHAN_RS:true"  \
+"MASTER15_CLOCK_DOMAIN_CROSSING:false"  \
+"MASTER15_DATA_WIDTH:64"  \
+"MASTER15_DWC_DATA_FIFO_DEPTH:16"  \
+"MASTER15_READ_INTERLEAVE:false"  \
+"MASTER15_READ_SLAVE0:true"  \
+"MASTER15_READ_SLAVE1:true"  \
+"MASTER15_READ_SLAVE2:true"  \
+"MASTER15_READ_SLAVE3:true"  \
+"MASTER15_READ_SLAVE4:true"  \
+"MASTER15_READ_SLAVE5:true"  \
+"MASTER15_READ_SLAVE6:true"  \
+"MASTER15_READ_SLAVE7:true"  \
+"MASTER15_READ_SLAVE8:true"  \
+"MASTER15_READ_SLAVE9:true"  \
+"MASTER15_READ_SLAVE10:true"  \
+"MASTER15_READ_SLAVE11:true"  \
+"MASTER15_READ_SLAVE12:true"  \
+"MASTER15_READ_SLAVE13:true"  \
+"MASTER15_READ_SLAVE14:true"  \
+"MASTER15_READ_SLAVE15:true"  \
+"MASTER15_READ_SLAVE16:true"  \
+"MASTER15_READ_SLAVE17:true"  \
+"MASTER15_READ_SLAVE18:true"  \
+"MASTER15_READ_SLAVE19:true"  \
+"MASTER15_READ_SLAVE20:true"  \
+"MASTER15_READ_SLAVE21:true"  \
+"MASTER15_READ_SLAVE22:true"  \
+"MASTER15_READ_SLAVE23:true"  \
+"MASTER15_READ_SLAVE24:true"  \
+"MASTER15_READ_SLAVE25:true"  \
+"MASTER15_READ_SLAVE26:true"  \
+"MASTER15_READ_SLAVE27:true"  \
+"MASTER15_READ_SLAVE28:true"  \
+"MASTER15_READ_SLAVE29:true"  \
+"MASTER15_READ_SLAVE30:true"  \
+"MASTER15_READ_SLAVE31:true"  \
+"MASTER15_TYPE:0"  \
+"MASTER15_WRITE_SLAVE0:true"  \
+"MASTER15_WRITE_SLAVE1:true"  \
+"MASTER15_WRITE_SLAVE2:true"  \
+"MASTER15_WRITE_SLAVE3:true"  \
+"MASTER15_WRITE_SLAVE4:true"  \
+"MASTER15_WRITE_SLAVE5:true"  \
+"MASTER15_WRITE_SLAVE6:true"  \
+"MASTER15_WRITE_SLAVE7:true"  \
+"MASTER15_WRITE_SLAVE8:true"  \
+"MASTER15_WRITE_SLAVE9:true"  \
+"MASTER15_WRITE_SLAVE10:true"  \
+"MASTER15_WRITE_SLAVE11:true"  \
+"MASTER15_WRITE_SLAVE12:true"  \
+"MASTER15_WRITE_SLAVE13:true"  \
+"MASTER15_WRITE_SLAVE14:true"  \
+"MASTER15_WRITE_SLAVE15:true"  \
+"MASTER15_WRITE_SLAVE16:true"  \
+"MASTER15_WRITE_SLAVE17:true"  \
+"MASTER15_WRITE_SLAVE18:true"  \
+"MASTER15_WRITE_SLAVE19:true"  \
+"MASTER15_WRITE_SLAVE20:true"  \
+"MASTER15_WRITE_SLAVE21:true"  \
+"MASTER15_WRITE_SLAVE22:true"  \
+"MASTER15_WRITE_SLAVE23:true"  \
+"MASTER15_WRITE_SLAVE24:true"  \
+"MASTER15_WRITE_SLAVE25:true"  \
+"MASTER15_WRITE_SLAVE26:true"  \
+"MASTER15_WRITE_SLAVE27:true"  \
+"MASTER15_WRITE_SLAVE28:true"  \
+"MASTER15_WRITE_SLAVE29:true"  \
+"MASTER15_WRITE_SLAVE30:true"  \
+"MASTER15_WRITE_SLAVE31:true"  \
+"NUM_MASTERS:1"  \
+"NUM_MASTERS_WIDTH:1"  \
+"NUM_SLAVES:1"  \
+"NUM_THREADS:4"  \
+"OPEN_TRANS_MAX:8"  \
+"OPTIMIZATION:1"  \
+"RD_ARB_EN:false"  \
+"SLAVE0_CHAN_RS:true"  \
+"SLAVE0_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE0_DATA_WIDTH:64"  \
+"SLAVE0_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE0_END_ADDR:0xffffffff"  \
+"SLAVE0_END_ADDR_UPPER:0x1f"  \
+"SLAVE0_READ_INTERLEAVE:false"  \
+"SLAVE0_START_ADDR:0x60000000"  \
+"SLAVE0_START_ADDR_UPPER:0x0"  \
+"SLAVE0_TYPE:0"  \
+"SLAVE1_CHAN_RS:true"  \
+"SLAVE1_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE1_DATA_WIDTH:64"  \
+"SLAVE1_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE1_END_ADDR:0xfff"  \
+"SLAVE1_END_ADDR_UPPER:0x0"  \
+"SLAVE1_READ_INTERLEAVE:false"  \
+"SLAVE1_START_ADDR:0x0"  \
+"SLAVE1_START_ADDR_UPPER:0x0"  \
+"SLAVE1_TYPE:0"  \
+"SLAVE2_CHAN_RS:true"  \
+"SLAVE2_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE2_DATA_WIDTH:64"  \
+"SLAVE2_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE2_END_ADDR:0x17ffffff"  \
+"SLAVE2_END_ADDR_UPPER:0x0"  \
+"SLAVE2_READ_INTERLEAVE:false"  \
+"SLAVE2_START_ADDR:0x10000000"  \
+"SLAVE2_START_ADDR_UPPER:0x0"  \
+"SLAVE2_TYPE:0"  \
+"SLAVE3_CHAN_RS:true"  \
+"SLAVE3_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE3_DATA_WIDTH:64"  \
+"SLAVE3_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE3_END_ADDR:0x1fffffff"  \
+"SLAVE3_END_ADDR_UPPER:0x0"  \
+"SLAVE3_READ_INTERLEAVE:false"  \
+"SLAVE3_START_ADDR:0x18000000"  \
+"SLAVE3_START_ADDR_UPPER:0x0"  \
+"SLAVE3_TYPE:0"  \
+"SLAVE4_CHAN_RS:true"  \
+"SLAVE4_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE4_DATA_WIDTH:64"  \
+"SLAVE4_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE4_END_ADDR:0x27ffffff"  \
+"SLAVE4_END_ADDR_UPPER:0x0"  \
+"SLAVE4_READ_INTERLEAVE:false"  \
+"SLAVE4_START_ADDR:0x20000000"  \
+"SLAVE4_START_ADDR_UPPER:0x0"  \
+"SLAVE4_TYPE:0"  \
+"SLAVE5_CHAN_RS:true"  \
+"SLAVE5_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE5_DATA_WIDTH:64"  \
+"SLAVE5_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE5_END_ADDR:0x2fffffff"  \
+"SLAVE5_END_ADDR_UPPER:0x0"  \
+"SLAVE5_READ_INTERLEAVE:false"  \
+"SLAVE5_START_ADDR:0x28000000"  \
+"SLAVE5_START_ADDR_UPPER:0x0"  \
+"SLAVE5_TYPE:0"  \
+"SLAVE6_CHAN_RS:true"  \
+"SLAVE6_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE6_DATA_WIDTH:64"  \
+"SLAVE6_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE6_END_ADDR:0x37ffffff"  \
+"SLAVE6_END_ADDR_UPPER:0x0"  \
+"SLAVE6_READ_INTERLEAVE:false"  \
+"SLAVE6_START_ADDR:0x30000000"  \
+"SLAVE6_START_ADDR_UPPER:0x0"  \
+"SLAVE6_TYPE:0"  \
+"SLAVE7_CHAN_RS:true"  \
+"SLAVE7_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE7_DATA_WIDTH:64"  \
+"SLAVE7_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE7_END_ADDR:0x3fffffff"  \
+"SLAVE7_END_ADDR_UPPER:0x0"  \
+"SLAVE7_READ_INTERLEAVE:false"  \
+"SLAVE7_START_ADDR:0x38000000"  \
+"SLAVE7_START_ADDR_UPPER:0x0"  \
+"SLAVE7_TYPE:0"  \
+"SLAVE8_CHAN_RS:true"  \
+"SLAVE8_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE8_DATA_WIDTH:64"  \
+"SLAVE8_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE8_END_ADDR:0x47ffffff"  \
+"SLAVE8_END_ADDR_UPPER:0x0"  \
+"SLAVE8_READ_INTERLEAVE:false"  \
+"SLAVE8_START_ADDR:0x40000000"  \
+"SLAVE8_START_ADDR_UPPER:0x0"  \
+"SLAVE8_TYPE:0"  \
+"SLAVE9_CHAN_RS:true"  \
+"SLAVE9_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE9_DATA_WIDTH:64"  \
+"SLAVE9_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE9_END_ADDR:0x4fffffff"  \
+"SLAVE9_END_ADDR_UPPER:0x0"  \
+"SLAVE9_READ_INTERLEAVE:false"  \
+"SLAVE9_START_ADDR:0x48000000"  \
+"SLAVE9_START_ADDR_UPPER:0x0"  \
+"SLAVE9_TYPE:0"  \
+"SLAVE10_CHAN_RS:true"  \
+"SLAVE10_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE10_DATA_WIDTH:64"  \
+"SLAVE10_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE10_END_ADDR:0x57ffffff"  \
+"SLAVE10_END_ADDR_UPPER:0x0"  \
+"SLAVE10_READ_INTERLEAVE:false"  \
+"SLAVE10_START_ADDR:0x50000000"  \
+"SLAVE10_START_ADDR_UPPER:0x0"  \
+"SLAVE10_TYPE:0"  \
+"SLAVE11_CHAN_RS:true"  \
+"SLAVE11_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE11_DATA_WIDTH:64"  \
+"SLAVE11_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE11_END_ADDR:0x5fffffff"  \
+"SLAVE11_END_ADDR_UPPER:0x0"  \
+"SLAVE11_READ_INTERLEAVE:false"  \
+"SLAVE11_START_ADDR:0x58000000"  \
+"SLAVE11_START_ADDR_UPPER:0x0"  \
+"SLAVE11_TYPE:0"  \
+"SLAVE12_CHAN_RS:true"  \
+"SLAVE12_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE12_DATA_WIDTH:64"  \
+"SLAVE12_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE12_END_ADDR:0x902fffff"  \
+"SLAVE12_END_ADDR_UPPER:0x0"  \
+"SLAVE12_READ_INTERLEAVE:false"  \
+"SLAVE12_START_ADDR:0x90000000"  \
+"SLAVE12_START_ADDR_UPPER:0x0"  \
+"SLAVE12_TYPE:0"  \
+"SLAVE13_CHAN_RS:true"  \
+"SLAVE13_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE13_DATA_WIDTH:64"  \
+"SLAVE13_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE13_END_ADDR:0x905fffff"  \
+"SLAVE13_END_ADDR_UPPER:0x0"  \
+"SLAVE13_READ_INTERLEAVE:false"  \
+"SLAVE13_START_ADDR:0x90300000"  \
+"SLAVE13_START_ADDR_UPPER:0x0"  \
+"SLAVE13_TYPE:0"  \
+"SLAVE14_CHAN_RS:true"  \
+"SLAVE14_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE14_DATA_WIDTH:64"  \
+"SLAVE14_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE14_END_ADDR:0x908fffff"  \
+"SLAVE14_END_ADDR_UPPER:0x0"  \
+"SLAVE14_READ_INTERLEAVE:false"  \
+"SLAVE14_START_ADDR:0x90600000"  \
+"SLAVE14_START_ADDR_UPPER:0x0"  \
+"SLAVE14_TYPE:0"  \
+"SLAVE15_CHAN_RS:true"  \
+"SLAVE15_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE15_DATA_WIDTH:64"  \
+"SLAVE15_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE15_END_ADDR:0x90bfffff"  \
+"SLAVE15_END_ADDR_UPPER:0x0"  \
+"SLAVE15_READ_INTERLEAVE:false"  \
+"SLAVE15_START_ADDR:0x90900000"  \
+"SLAVE15_START_ADDR_UPPER:0x0"  \
+"SLAVE15_TYPE:0"  \
+"SLAVE16_CHAN_RS:true"  \
+"SLAVE16_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE16_DATA_WIDTH:64"  \
+"SLAVE16_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE16_END_ADDR:0x90efffff"  \
+"SLAVE16_END_ADDR_UPPER:0x0"  \
+"SLAVE16_READ_INTERLEAVE:false"  \
+"SLAVE16_START_ADDR:0x90c00000"  \
+"SLAVE16_START_ADDR_UPPER:0x0"  \
+"SLAVE16_TYPE:0"  \
+"SLAVE17_CHAN_RS:true"  \
+"SLAVE17_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE17_DATA_WIDTH:64"  \
+"SLAVE17_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE17_END_ADDR:0x911fffff"  \
+"SLAVE17_END_ADDR_UPPER:0x0"  \
+"SLAVE17_READ_INTERLEAVE:false"  \
+"SLAVE17_START_ADDR:0x90f00000"  \
+"SLAVE17_START_ADDR_UPPER:0x0"  \
+"SLAVE17_TYPE:0"  \
+"SLAVE18_CHAN_RS:true"  \
+"SLAVE18_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE18_DATA_WIDTH:64"  \
+"SLAVE18_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE18_END_ADDR:0x914fffff"  \
+"SLAVE18_END_ADDR_UPPER:0x0"  \
+"SLAVE18_READ_INTERLEAVE:false"  \
+"SLAVE18_START_ADDR:0x91200000"  \
+"SLAVE18_START_ADDR_UPPER:0x0"  \
+"SLAVE18_TYPE:0"  \
+"SLAVE19_CHAN_RS:true"  \
+"SLAVE19_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE19_DATA_WIDTH:64"  \
+"SLAVE19_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE19_END_ADDR:0x917fffff"  \
+"SLAVE19_END_ADDR_UPPER:0x0"  \
+"SLAVE19_READ_INTERLEAVE:false"  \
+"SLAVE19_START_ADDR:0x91500000"  \
+"SLAVE19_START_ADDR_UPPER:0x0"  \
+"SLAVE19_TYPE:0"  \
+"SLAVE20_CHAN_RS:true"  \
+"SLAVE20_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE20_DATA_WIDTH:64"  \
+"SLAVE20_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE20_END_ADDR:0x91afffff"  \
+"SLAVE20_END_ADDR_UPPER:0x0"  \
+"SLAVE20_READ_INTERLEAVE:false"  \
+"SLAVE20_START_ADDR:0x91800000"  \
+"SLAVE20_START_ADDR_UPPER:0x0"  \
+"SLAVE20_TYPE:0"  \
+"SLAVE21_CHAN_RS:true"  \
+"SLAVE21_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE21_DATA_WIDTH:64"  \
+"SLAVE21_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE21_END_ADDR:0x91dfffff"  \
+"SLAVE21_END_ADDR_UPPER:0x0"  \
+"SLAVE21_READ_INTERLEAVE:false"  \
+"SLAVE21_START_ADDR:0x91b00000"  \
+"SLAVE21_START_ADDR_UPPER:0x0"  \
+"SLAVE21_TYPE:0"  \
+"SLAVE22_CHAN_RS:true"  \
+"SLAVE22_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE22_DATA_WIDTH:64"  \
+"SLAVE22_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE22_END_ADDR:0x920fffff"  \
+"SLAVE22_END_ADDR_UPPER:0x0"  \
+"SLAVE22_READ_INTERLEAVE:false"  \
+"SLAVE22_START_ADDR:0x91e00000"  \
+"SLAVE22_START_ADDR_UPPER:0x0"  \
+"SLAVE22_TYPE:0"  \
+"SLAVE23_CHAN_RS:true"  \
+"SLAVE23_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE23_DATA_WIDTH:64"  \
+"SLAVE23_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE23_END_ADDR:0x923fffff"  \
+"SLAVE23_END_ADDR_UPPER:0x0"  \
+"SLAVE23_READ_INTERLEAVE:false"  \
+"SLAVE23_START_ADDR:0x92100000"  \
+"SLAVE23_START_ADDR_UPPER:0x0"  \
+"SLAVE23_TYPE:0"  \
+"SLAVE24_CHAN_RS:true"  \
+"SLAVE24_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE24_DATA_WIDTH:64"  \
+"SLAVE24_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE24_END_ADDR:0x926fffff"  \
+"SLAVE24_END_ADDR_UPPER:0x0"  \
+"SLAVE24_READ_INTERLEAVE:false"  \
+"SLAVE24_START_ADDR:0x92400000"  \
+"SLAVE24_START_ADDR_UPPER:0x0"  \
+"SLAVE24_TYPE:0"  \
+"SLAVE25_CHAN_RS:true"  \
+"SLAVE25_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE25_DATA_WIDTH:64"  \
+"SLAVE25_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE25_END_ADDR:0x929fffff"  \
+"SLAVE25_END_ADDR_UPPER:0x0"  \
+"SLAVE25_READ_INTERLEAVE:false"  \
+"SLAVE25_START_ADDR:0x92700000"  \
+"SLAVE25_START_ADDR_UPPER:0x0"  \
+"SLAVE25_TYPE:0"  \
+"SLAVE26_CHAN_RS:true"  \
+"SLAVE26_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE26_DATA_WIDTH:64"  \
+"SLAVE26_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE26_END_ADDR:0x92cfffff"  \
+"SLAVE26_END_ADDR_UPPER:0x0"  \
+"SLAVE26_READ_INTERLEAVE:false"  \
+"SLAVE26_START_ADDR:0x92a00000"  \
+"SLAVE26_START_ADDR_UPPER:0x0"  \
+"SLAVE26_TYPE:0"  \
+"SLAVE27_CHAN_RS:true"  \
+"SLAVE27_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE27_DATA_WIDTH:64"  \
+"SLAVE27_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE27_END_ADDR:0x92ffffff"  \
+"SLAVE27_END_ADDR_UPPER:0x0"  \
+"SLAVE27_READ_INTERLEAVE:false"  \
+"SLAVE27_START_ADDR:0x92d00000"  \
+"SLAVE27_START_ADDR_UPPER:0x0"  \
+"SLAVE27_TYPE:0"  \
+"SLAVE28_CHAN_RS:true"  \
+"SLAVE28_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE28_DATA_WIDTH:64"  \
+"SLAVE28_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE28_END_ADDR:0x932fffff"  \
+"SLAVE28_END_ADDR_UPPER:0x0"  \
+"SLAVE28_READ_INTERLEAVE:false"  \
+"SLAVE28_START_ADDR:0x93000000"  \
+"SLAVE28_START_ADDR_UPPER:0x0"  \
+"SLAVE28_TYPE:0"  \
+"SLAVE29_CHAN_RS:true"  \
+"SLAVE29_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE29_DATA_WIDTH:64"  \
+"SLAVE29_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE29_END_ADDR:0x935fffff"  \
+"SLAVE29_END_ADDR_UPPER:0x0"  \
+"SLAVE29_READ_INTERLEAVE:false"  \
+"SLAVE29_START_ADDR:0x93300000"  \
+"SLAVE29_START_ADDR_UPPER:0x0"  \
+"SLAVE29_TYPE:0"  \
+"SLAVE30_CHAN_RS:true"  \
+"SLAVE30_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE30_DATA_WIDTH:64"  \
+"SLAVE30_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE30_END_ADDR:0x938fffff"  \
+"SLAVE30_END_ADDR_UPPER:0x0"  \
+"SLAVE30_READ_INTERLEAVE:false"  \
+"SLAVE30_START_ADDR:0x93600000"  \
+"SLAVE30_START_ADDR_UPPER:0x0"  \
+"SLAVE30_TYPE:0"  \
+"SLAVE31_CHAN_RS:true"  \
+"SLAVE31_CLOCK_DOMAIN_CROSSING:false"  \
+"SLAVE31_DATA_WIDTH:64"  \
+"SLAVE31_DWC_DATA_FIFO_DEPTH:16"  \
+"SLAVE31_END_ADDR:0x93bfffff"  \
+"SLAVE31_END_ADDR_UPPER:0x0"  \
+"SLAVE31_READ_INTERLEAVE:false"  \
+"SLAVE31_START_ADDR:0x93900000"  \
+"SLAVE31_START_ADDR_UPPER:0x0"  \
+"SLAVE31_TYPE:0"  \
+"SLV_AXI4PRT_ADDRDEPTH:8"  \
+"SLV_AXI4PRT_DATADEPTH:9"  \
+"USER_WIDTH:1"   }
+# Exporting Component Description of PCIE_INITIATOR to TCL done
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PF_PCIE_C0.tcl b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PF_PCIE_C0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..76aaeccefaf55c4a323906df26bf1aa35b9a93ba
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/PF_PCIE_C0.tcl
@@ -0,0 +1,198 @@
+# Exporting Component Description of PF_PCIE_C0 to TCL
+# Family: PolarFireSoC
+# Part Number: MPFS025T-FCVG484E
+# Create and Configure the core component PF_PCIE_C0
+create_and_configure_core -core_vlnv {Actel:SgCore:PF_PCIE:*} -component_name {PF_PCIE_C0} -params {\
+"EXPOSE_ALL_DEBUG_PORTS:false"  \
+"UI_DLL_JITTER_TOLERANCE:Medium_Low"  \
+"UI_EXPOSE_LANE_DRI_PORTS:false"  \
+"UI_EXPOSE_PCIE_APBLINK_PORTS:true"  \
+"UI_GPSS1_LANE0_IS_USED:false"  \
+"UI_GPSS1_LANE1_IS_USED:false"  \
+"UI_GPSS1_LANE2_IS_USED:false"  \
+"UI_GPSS1_LANE3_IS_USED:false"  \
+"UI_IS_CONFIGURED:true"  \
+"UI_PCIE_0_BAR_MODE:Custom"  \
+"UI_PCIE_0_CDR_REF_CLK_NUMBER:1"  \
+"UI_PCIE_0_CDR_REF_CLK_SOURCE:Dedicated"  \
+"UI_PCIE_0_CLASS_CODE:0x0604"  \
+"UI_PCIE_0_CONTROLLER_ENABLED:Enabled"  \
+"UI_PCIE_0_DE_EMPHASIS:-3.5 dB"  \
+"UI_PCIE_0_DEVICE_ID:0x1556"  \
+"UI_PCIE_0_EXPOSE_WAKE_SIG:Disabled"  \
+"UI_PCIE_0_INTERRUPTS:MSI8"  \
+"UI_PCIE_0_L0_ACC_LATENCY:No limit"  \
+"UI_PCIE_0_L0_EXIT_LATENCY:64 ns to less than 128 ns"  \
+"UI_PCIE_0_L1_ACC_LATENCY:No limit"  \
+"UI_PCIE_0_L1_ENABLE:Disabled"  \
+"UI_PCIE_0_L1_EXIT_LATENCY:16 us to less than 32 us"  \
+"UI_PCIE_0_LANE_RATE:Gen2 (5.0 Gbps)"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_0_TABLE:2 GB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_1_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_2_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_3_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_4_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_SIZE_BAR_5_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_0_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_1_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_2_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_3_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_4_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_SOURCE_ADDRESS_BAR_5_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_0_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_1_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_2_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_3_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_4_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TABLE_SIZE_BAR_5_TABLE:4 KB"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_0_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_1_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_2_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_3_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_4_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TRANS_ADDRESS_BAR_5_TABLE:0x0000"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_0_TABLE:64-bit prefetchable memory"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_1_TABLE:Disabled"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_2_TABLE:Disabled"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_3_TABLE:Disabled"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_4_TABLE:Disabled"  \
+"UI_PCIE_0_MASTER_TYPE_BAR_5_TABLE:Disabled"  \
+"UI_PCIE_0_NUM_FTS:63"  \
+"UI_PCIE_0_NUMBER_OF_LANES:x1"  \
+"UI_PCIE_0_PHY_REF_CLK_SLOT:Slot"  \
+"UI_PCIE_0_PORT_TYPE:Root Port"  \
+"UI_PCIE_0_REF_CLK_FREQ:100"  \
+"UI_PCIE_0_REVISION_ID:0x0000"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_0:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_1:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_2:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_3:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_4:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_5:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_6:4 KB"  \
+"UI_PCIE_0_SLAVE_SIZE_TABLE_7:4 KB"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_0:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_1:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_2:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_3:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_4:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_5:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_6:0x0000"  \
+"UI_PCIE_0_SLAVE_SOURCE_ADDRESS_TABLE_7:0x0000"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_0:Enabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_1:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_2:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_3:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_4:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_5:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_6:Disabled"  \
+"UI_PCIE_0_SLAVE_STATE_TABLE_7:Disabled"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_0:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_1:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_2:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_3:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_4:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_5:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_6:0x0000"  \
+"UI_PCIE_0_SLAVE_TRANS_ADDRESS_TABLE_7:0x0000"  \
+"UI_PCIE_0_SUB_SYSTEM_ID:0x0000"  \
+"UI_PCIE_0_SUB_VENDOR_ID:0x0000"  \
+"UI_PCIE_0_TRANSMIT_SWING:Full Swing"  \
+"UI_PCIE_0_VENDOR_ID:0x11AA"  \
+"UI_PCIE_1_BAR_MODE:Custom"  \
+"UI_PCIE_1_CDR_REF_CLK_NUMBER:1"  \
+"UI_PCIE_1_CDR_REF_CLK_SOURCE:Dedicated"  \
+"UI_PCIE_1_CLASS_CODE:0x0000"  \
+"UI_PCIE_1_CONTROLLER_ENABLED:Disabled"  \
+"UI_PCIE_1_DE_EMPHASIS:-3.5 dB"  \
+"UI_PCIE_1_DEVICE_ID:0x1556"  \
+"UI_PCIE_1_EXPOSE_WAKE_SIG:Disabled"  \
+"UI_PCIE_1_INTERRUPTS:MSI1"  \
+"UI_PCIE_1_L0_ACC_LATENCY:No limit"  \
+"UI_PCIE_1_L0_EXIT_LATENCY:64 ns to less than 128 ns"  \
+"UI_PCIE_1_L1_ACC_LATENCY:No limit"  \
+"UI_PCIE_1_L1_ENABLE:Disabled"  \
+"UI_PCIE_1_L1_EXIT_LATENCY:16 us to less than 32 us"  \
+"UI_PCIE_1_LANE_RATE:Gen2 (5.0 Gbps)"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_0_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_1_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_2_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_3_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_4_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SIZE_BAR_5_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_0_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_1_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_2_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_3_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_4_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_SOURCE_ADDRESS_BAR_5_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_0_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_1_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_2_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_3_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_4_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TABLE_SIZE_BAR_5_TABLE:4 KB"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_0_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_1_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_2_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_3_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_4_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TRANS_ADDRESS_BAR_5_TABLE:0x0000"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_0_TABLE:64-bit prefetchable memory"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_1_TABLE:Disabled"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_2_TABLE:Disabled"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_3_TABLE:Disabled"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_4_TABLE:Disabled"  \
+"UI_PCIE_1_MASTER_TYPE_BAR_5_TABLE:Disabled"  \
+"UI_PCIE_1_NUM_FTS:63"  \
+"UI_PCIE_1_NUMBER_OF_LANES:x4"  \
+"UI_PCIE_1_PHY_REF_CLK_SLOT:Slot"  \
+"UI_PCIE_1_PORT_TYPE:Root Port"  \
+"UI_PCIE_1_REF_CLK_FREQ:100"  \
+"UI_PCIE_1_REVISION_ID:0x0000"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_0:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_1:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_2:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_3:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_4:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_5:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_6:4 KB"  \
+"UI_PCIE_1_SLAVE_SIZE_TABLE_7:4 KB"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_0:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_1:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_2:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_3:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_4:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_5:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_6:0x0000"  \
+"UI_PCIE_1_SLAVE_SOURCE_ADDRESS_TABLE_7:0x0000"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_0:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_1:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_2:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_3:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_4:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_5:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_6:Disabled"  \
+"UI_PCIE_1_SLAVE_STATE_TABLE_7:Disabled"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_0:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_1:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_2:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_3:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_4:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_5:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_6:0x0000"  \
+"UI_PCIE_1_SLAVE_TRANS_ADDRESS_TABLE_7:0x0000"  \
+"UI_PCIE_1_SUB_SYSTEM_ID:0x0000"  \
+"UI_PCIE_1_SUB_VENDOR_ID:0x0000"  \
+"UI_PCIE_1_TRANSMIT_SWING:Full Swing"  \
+"UI_PCIE_1_VENDOR_ID:0x11AA"  \
+"UI_PCIESS_LANE0_IS_USED:true"  \
+"UI_PCIESS_LANE1_IS_USED:false"  \
+"UI_PCIESS_LANE2_IS_USED:false"  \
+"UI_PCIESS_LANE3_IS_USED:false"  \
+"UI_PROTOCOL_PRESET_USED:PCIe"  \
+"UI_SIMULATION_LEVEL:RTL"  \
+"UI_TX_CLK_DIV_FACTOR:1"  \
+"UI_USE_EMBEDDED_DLL:true"  \
+"XT_ES_DEVICE:false"   }
+# Exporting Component Description of PF_PCIE_C0 to TCL done
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/constraints/M2.pdc b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/constraints/M2.pdc
new file mode 100644
index 0000000000000000000000000000000000000000..e16a7a74773e32eae4ecc588ad17d3312ea4d29c
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/constraints/M2.pdc
@@ -0,0 +1,32 @@
+
+set_io -port_name M2_PERST0n \
+    -pin_name Y18            \
+    -fixed true              \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name M2_PET0_N    \
+    -pin_name F21 \
+    -DIRECTION OUTPUT
+
+set_io -port_name M2_PET0_P    \
+    -pin_name F22 \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name M2_PER0_N    \
+    -pin_name G19 \
+    -DIRECTION INPUT
+
+set_io -port_name M2_PER0_P \
+    -pin_name G20 \
+    -DIRECTION INPUT
+
+    
+set_io -port_name XCVR_0A_REFCLK_P  \
+    -pin_name L19                \
+    -DIRECTION INPUT
+    
+set_io -port_name XCVR_0A_REFCLK_N  \
+    -pin_name L20                \
+    -DIRECTION INPUT
diff --git a/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/device-tree-overlay/pcie.dtso b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/device-tree-overlay/pcie.dtso
new file mode 100644
index 0000000000000000000000000000000000000000..0de5331d8e7781d2c0678140460ca5bb7bc75b2d
--- /dev/null
+++ b/sources/FPGA-design/script_support/components/M2/PCIE_ONLY/device-tree-overlay/pcie.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+/plugin/;
+
+&{/chosen} {
+	overlays {
+		M2-PCIE-ONLY-GATEWARE = "GATEWARE_GIT_VERSION";
+	};
+};
+
+&pcie {
+	status = "okay";
+};